JPH04192185A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To secure an input voltage margin on both sides of 'H' and 'L' by changing the ratio on the initial stage of input circuit with the use of a sense amplifier driving signal. CONSTITUTION:One shot pulse of 'L' level is generated on N3 by the sense amplifier driving signal phi4 and at the same time an N4 becomes 'L' level by receiving an address signal EXTAi of 'H' level from outside. Then, one shot pulse of 'H' level is generated on N5 by the inside signal phi2. An N1 becomes 'L' level immediately by the EXTAi and N5, and the data are held to a holding circuit. Consequently, the effect of noise at the sensing time can be reduced even if a Vss is left over by the noise due to the sensing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input first stage circuit of a dynamic RAM.

[Conventional technology]

FIG. 3 is a circuit diagram showing an example of an address buffer configured with a conventional input circuit, and FIG. 4 is a timing diagram thereof.

! IfAi is an external address signal, and φ is a signal that takes the external address signal into the internal circuit. After φ2 holds the data of the address signal in the internal holding circuit, if the external address changes, both the P-channel transistor of input φ2 and the N-channel transistor one stage after the inverter are turned off so that the held data does not change.
This is a signal to

Next, the operation will be explained.

First is the row address strobe signal.

! φ1 and φ2 fall in response to the fall of x〒Yokuchi. Therefore, KIT, 6. Data of i is held in the holding circuit after the clocked inverter. Next, if the row address data is "L" and the column address data is "H", the **TAi signal must change from "L" to "H". If the falling point of the column address rope signal TCKl coincides with the timing at which the sense amplifier starts operating, the floating Vss due to the sense amplifier's GND noise will cause the Nl's “H” If φ2 rises before Nl changes due to m, reverse data will be held in the holding circuit, resulting in malfunction. Put it away.

[Problem to be solved by the invention]

The input first stage circuit of a conventional dynamic RAM has the above configuration, so when the input signal changes from "L" level to "H" level, it is not affected by noise generated by the sense amplifier etc. Therefore, it is necessary to change the timing of φ and the ratio of the first input stage, and changing the ratio may reduce the "L" level margin of the input voltage.

This invention was made to solve the above-mentioned problems, and its object is to provide a semiconductor circuit that can change the ratio of the first input stage only at the moment when the sense amplifier starts operating.

[Means to solve the problem]

The semiconductor circuit according to the present invention allows the ratio of the first input stage to be changed using a sense amplifier drive signal.

[Operation] By using the sense amplifier drive signal in the first stage of the input circuit of the present invention, the influence of noise during sensing is reduced, and the ratio of the first stage changes only during sensing, so that the input voltage does not change under normal conditions. In order to have sufficient merging on both the "H" and "L" sides, the ratio of the first stage is set.

〔Example〕

An embodiment of the present invention will be described below.

FIG. 1 is a circuit diagram of an address buffer according to an embodiment of the present invention, and FIG. 2 is a timing diagram thereof.

1! TAi, φ1. φ2 is the same as that described in the conventional circuit. φ becomes “L” due to the falling edge of 1TCτ1.
” and rises to become “H”. φ4 is the drive signal for the sense amplifier. An N-channel transistor is attached to the first output stage of the conventional input circuit as shown in the figure, and the input of the transistor is 3 NOR output.3N
The inputs of the OR are respectively the output (N3) of a circuit which generates one shot when φ and φ4 are input, and the output of an N-channel transistor connected to the power supply via a high resistance as shown in the figure.

Next, the operation will be explained. First, φ4 sets N3 to “L”.
"1 shot pulse is generated, and at the same time 1!?, 6.i receives "H" and becomes N4 or "L" level.

Then, one shot pulse of "H" is generated at N5 by φ3. @X T A Due to i and N5, Nl immediately goes to "L" level, and data is held in the holding circuit. Even if Vss floats due to noise caused by the sense, Nl
By increasing the number of transistors that connect Vss to Vss, the influence of noise during sensing can be reduced.

〔Effect of the invention〕

As described above, according to the present invention, the ratio of the first stage of the input circuit is configured to be changed using the sense amplifier drive signal, and the ratio is changed only at timings that are easily affected by noise. As a result, input voltage margins can be secured on both the "H" and "L2" sides.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a semiconductor circuit showing an embodiment of the present invention, FIG. 2 is a timing chart thereof, FIG. 3 is a circuit diagram of a conventional semiconductor circuit, and FIG. 4 is a timing chart thereof. In the figure, φ indicates an internal signal and φ1 indicates a drive signal.

Claims (1)

[Claims] A semiconductor circuit in a dynamic RAM, characterized in that the ratio of the first input stage is changed using a drive signal of a sense amplifier.