JPH04192173A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor memory which is nonvolatile and capable of nondestructive rewrite of a data by connecting a ferroelectric substance gate FET (MFSFET) in a prescribed method. CONSTITUTION:A gate electrode 12 of the MFSFET 1 is connected to a word line (WL). A source/drain 13 is connected to a plate line (PL), while the other source/drain 14 to a bit line (BL). A substrate electric potential of the MFSFET 1 is the same potential as the PL. Then, one end of WL1-WLn is connected to a WL decoder driver 21, while one end of PL1-PLm to a PL decoder driver 22, and one end of BL1-BLn to sens amplifiers (SA) 23a and 23b. Two kinds of precharged input signals are compared with each other by the SA, and since a signal at a low level is further lower amplified, a signal at a high level being further higher, when a reference signal and a detecting signal are inputted to the SA, binarization is performed in accordance with the level size of both signals, so that the size of the detecting signal can easily be decided.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device using a field effect transistor using a ferroelectric material as a gate insulating film as a memory cell.

(Prior art) Dynamic random access memory (hereinafter abbreviated as DRAM) has traditionally been used as a large-capacity semiconductor storage device.
It has been known. In DRAM, one transistor and one
Since a 1-bit memory cell is constructed with only 1 capacitive element, high integration and large capacity are possible.

Furthermore, like other semiconductor storage devices, since there is no mechanically moving part, it has the advantage of faster operating speed than storage media with moving parts, such as magnetic storage devices and optical disk devices.

In order to further increase the capacity of a DRAM and reduce the bit cost, it is effective to miniaturize the processing dimensions of the elements and reduce the area occupied by the memory cells. However, this requires advanced manufacturing equipment and technology, so
With the miniaturization of processing dimensions, development costs and manufacturing costs increase, causing new problems such as a decrease in yield.

Furthermore, since DRAM is volatile, the stored information is lost when power is removed. Therefore, in order to retain memory, power must be constantly supplied, which poses a problem that the range of use is limited.

To solve these problems, U.S. Patent No. 38327
Specification No. 00, JP-A-51-274, JP-A-51
-21790, etc., as shown in Figure 7,
It has been proposed to use a ferroelectric gate FET (hereinafter referred to as MFSFET) as a memory cell, which uses a ferroelectric material for the gate insulating film and is capable of storing information by the electric polarization effect of the gate insulating film.

In FIG. 7, the surface of the P well in the P substrate 10 has n
Source/drains 13 and 14 are formed, and a gate electrode 12 is formed on the channel region with a ferroelectric film 11 interposed therebetween.

FIG. 8 is a diagram showing the relationship between the polarization P of the ferroelectric film 11 and the applied electric field E, and it is well known that ferroelectric materials have such a hysteresis characteristic.

That is, as the applied electric field increases in the positive direction, the polarization increases and eventually becomes saturated at electric field B. After that, even if the applied electric field is weakened to zero, the polarization does not become zero, and the residual electric polarization P(
0).

Next, when the applied electric field is increased in the opposite direction, the polarization becomes zero when the value of the holding electric field C is reached, and when the applied electric field is further increased, the polarization in the opposite direction is saturated due to the electric field. .

After that, even if the applied electric field in the opposite direction is weakened to zero, the polarization does not become zero, but has a residual electric polarization P(1). Then,
When the applied electric field is increased in the positive direction, the polarization becomes zero when the value of the holding electric field A is reached.

Therefore, an MFSF using a ferroelectric film as a gate insulating film
Data can be written to the ET by setting the residual electric polarization of the ferroelectric material in a predetermined direction.

FIG. 9 is a diagram for explaining the operation of the MFSFET, and schematically represents the energy bands of the gate electrode 12, ferroelectric film 11, and substrate 10 that constitute the MFSFET.

As shown in FIG. 1(a), from the gate electrode 12 to the substrate 1
Once the electric field El is applied in the direction toward 0, the residual electric polarization P is maintained even when the substrate and gate electrode are at ground potential.
(0) causes electrons 90 to concentrate in the channel region.

As a result, the FET functions as a depletion type FET in which the source/drain 13 and 14 are electrically connected and current flows even when no gate voltage is applied.

On the other hand, as shown in Figure (b), once the electric field E2 is set in the direction from the substrate to the gate electrode, the residual electric polarization P
Due to (1), holes 91 are concentrated in the channel.

As a result, the FET functions as an enhanced FET in which the source/drain 13 and 14 are electrically insulated and no current flows when no gate voltage is applied.

FIG. 10 is a diagram showing the relationship between the source/drain current 1d and the gate voltage Vg when the MFSFET functions as a depletion type and an enhancement type.

Utilizing the above characteristics, data writing is performed by applying a voltage in a predetermined direction between the gate electrode 12 and the substrate 10 to set the direction of residual electric polarization, thereby converting the function into a depletion type. Alternatively, data can be read by making the device an enhanced type, and data reading can be determined by whether or not conduction occurs between the source/drain 13 and 14.

(Issue 8 to be solved by the invention) In the above-mentioned prior art, only the operation of a single MFSFET is discussed, and when the MFSFETs are integrated to configure a storage device, the connection method between each MFSFET and the data transfer method are discussed. Reading and writing methods have not been specified, and no specific configuration of a semiconductor memory device using MFSFETs has been proposed.

An object of the present invention is to provide a specific configuration of a semiconductor memory device using MFSFET.

(Means for Solving the Problem) In order to achieve the above-mentioned object, the present invention uses MFSF
In a semiconductor memory device in which ETs are arranged in a matrix,
A word line group that commonly connects the gate electrodes of MFSFETs in each row, a bit line group that commonly connects one of the sources/drains of MFSFETs in each row, and MPSFs in each column.
It is equipped with a plate line group that commonly connects the other source/drain of the ETs and supplies a well potential to each MFSFET, and when reading, the word line and plate line connected to the MFSFET to be compared are set to "H". level, and the potential of the bit line at that time is detected.

When writing, one of the word line and plate line is set to "H° level" and the other is set to "H° level" according to the write data.
It was set to L” level.

(Operation) For example, when writing 1# as data, the word line is set to "H" level and the plate line is set to "L" level. As a result, the aforementioned residual electric polarization P(0) occurs, and the MFSFET comes to function as a depletion type transistor that becomes conductive even when the gate voltage is Ov.

In addition, when writing "0" as data, the word line is set to aLm level and the plate line is set to H" level. As a result, the above-mentioned residual electric polarization P(1) is generated, and the MF SF ET brushing is performed. When the voltage is OV, it functions as an enhancement type transistor that does not become conductive.

On the other hand, when reading the written information, if the word line and plate line are set to the °H" level, if 1° is written as data, the MF S
Since the FET functions as a depletion type transistor, the potential of the bit line becomes "H# level."

Also, if 0" is written as data, the MFSF
Since the ET functions as an enhancement type transistor, the potential of the bit line becomes "L" level.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

Fig. 1 is a circuit diagram showing the configuration of one cell of the memory device of the present invention, and Fig. 2 shows a connection method between each cell when a large number of the memory cells of Fig. 1 are arranged in 0 rows and m columns. FIG.

In FIG. 1, the gate electrode 12 of MFSFETI is connected to a word line (hereinafter abbreviated as WL).

One source/drain 13 is connected to a plate line (hereinafter referred to as
(abbreviated as PL) and the other source/drain 1
4 is connected to a bit line (hereinafter abbreviated as BL).

The substrate potential (well potential) of MFSFETI is the same as the potential of PL.

In addition, in FIG. 2, WLI, WL21. ...One end of WLn is connected to the WL decoder φ driver 21, and the PLI
, PL2,..., PLm are connected to the PL decoder/driver 22, and BLI, BL2,..., BLn
One end of the sense amplifier (hereinafter abbreviated as SA) 23a
, 23b, .

The SA compares two types of precharged human input signals, amplifies and outputs a signal with a low level so that it becomes lower, and a signal with a high level so that it becomes higher. therefore,
If the reference signal and the detection signal are manually input to the SA, the detection signal is binarized according to the magnitude relationship with the reference signal, so that it becomes easy to determine the magnitude of the detection signal.

FIG. 3 is a timing chart of the read operation of the storage device.

For example, when reading the stored information of MFSFETIA in FIG. 2, first set the potential of BLI to OV, then 5A2
The reference potential of the reference line RLI connected to 3a is set to Vcc.
Precharge to (power supply potential)/2.

Next, in order to determine the conduction state of MFSFET IA, the potential of PLI is set to VCC, but at this time,
In order to prevent data from being rewritten due to the potential difference between the gate and the substrate of MFSFETIA, the potential of WLl is also set to VCC to eliminate the potential difference between the gate and the substrate.

Further, PL2 to PLm and WL2 to WLn other than PLI and WLI are in a floating state.

As a result, when "1°" is stored in MFSFETIA, that is, when MFSFETIA functions as a depletion type, the potential of BLl gradually increases as shown by the solid line, and eventually becomes higher than the reference potential Vcc/2. Therefore, if SA23 a is turned on, BLI
The potential of RLI is 5V, and the potential of RLI is Ov as shown by the solid line.
becomes.

On the other hand, if "0" is stored in MFSFETIA, that is, if MFSFETIA is functioning as an enhanced type, the potential of BLI remains Ov as shown by the dotted line, and when 5A23b is turned on, BLI The potential is OV and the potential of RL is 5V as shown by the dotted line.

Therefore, a read operation is possible by detecting these potentials by appropriate means.

FIG. 4 is a timing chart of the write operation of the storage device.

When writing “1” to MFSFETIA, that is,
When the MFSFETIA is to function as a depletion type, the potential of WLI is set to Vcc while the potential of PLI is set to Ov, as shown in FIG. Further, PL and WL other than PLI and WLI are in a floating state.

Similarly, when writing "θ°" to MPSFETIA, that is, when trying to make MFSFETIA function as an enhanced type, as shown in FIG.
The potential of PLI is set to VCC while the potential of PLI is set to Ov. Further, PL and WL other than PLI and WLI are in a floating state.

By the way, in this example, Pb (Z
r, Ti)O3, and the film thickness was set to 0.2 μm. In addition, the composition ratio of Z' in Pb (Zr, Ti) O3 is 0.
．． It is desirable that it is 6 or less. According to such a configuration, when a voltage of 5V is applied between the gate electrode and the substrate, the electric field becomes 250KV/(2), which is a sufficient value as a rewriting voltage.

Further, the rewriting time is 1 us.

Furthermore, in this embodiment, since the potential of the reference signal input to SA is set to Vcc/2, signals can be surely compared regardless of whether the potential of BLI is at "H2 level" or "L" level. It becomes like this.

FIG. 5 is a circuit diagram of another embodiment of the present invention, and this embodiment is characterized in that the reference potential input to 5A23 is supplied from a dummy cell.

In the same figure, MPSFETla is a dummy cell paired with MFSFETIA on the same column, and MFSFETlb is M
It is a dummy cell that forms a pair on the same column as FSFETIB, and MFSFETla and lb each have an MFSFET
Complementary data of IA and IB is stored.

In such a configuration, when reading the stored information of MFSFETIA, as shown in FIG.
, BLldA potential are both set to ov, then WLI, WL
The potential of 1d and PLl is set to vcc.

Further, PL and WL other than PLI and WLI are in a floating state.

As a result, if MFSFETIA stores 1, the potential of BLI increases as shown by the solid line, but in this case, since 0 is stored in dummy cell MFSFET1a, the potential of BLld rises to Ov. If 5A23 is turned on, the potential of BLI becomes 5V.
The potential of BLld remains at Ov.

On the other hand, if "0" is stored in MFSFETIA,
The potential of BLl remains Ov as shown by the dotted line, but in this case, since "1" is stored in the dummy cell MFSFET1a, the potential of BLld gradually increases as shown by the dotted line.

When 5A23 is turned on here, the potential of BLld rises to 5V, and the potential of BLI remains at Ov.

Therefore, as described above, reading operation is possible by detecting these potentials by appropriate means.

According to this embodiment, since the reference potential is supplied from the dummy cell, the probability of occurrence of malfunction is reduced and reliability is improved compared to the case where the reference potential is input separately.

(Effects of the Invention) As is clear from the above description, according to the present invention, it is possible to provide a semiconductor memory device that is nonvolatile and allows data to be rewritten in a nondestructive manner.

[Brief explanation of the drawing]

Figure 81 is a circuit diagram showing the configuration of one cell of the memory device of the present invention, Figure 2 is a circuit diagram showing the connection method between each cell, w4
3 is a timing chart of a read operation, FIG. 4 is a timing chart of a write operation, FIG. 5 is a circuit diagram of another embodiment of the present invention, and FIG. 6 is a timing chart of a read operation of another embodiment. Figure 7 is a cross-sectional view of the MFSFET, the wg diagram is a diagram to explain the function of the ferroelectric, Figure 9 is a diagram to explain the operation of the MFSFET, and Figure 10 is the source/drain current and gate voltage of the MFSFET. Vg
FIG.

Claims (1)

[Scope of Claims] (1) In a semiconductor memory device in which field effect transistors having a pair of source/drain on the well surface and having a ferroelectric gate insulating film are arranged in a matrix, each row A word line group commonly connects the gate electrodes of the transistors, a bit line group commonly connects one of the sources/drains of the transistors in each row, a group of bit lines commonly connects the other source/drain of the transistors in each column, and What is claimed is: 1. A semiconductor memory device comprising a plate line group for supplying a well potential. (2) word line selection means that selectively sets only one word line to a first potential and other word lines to a floating state; selectively sets only one plate line to a second potential;
plate line selection means for setting the other plate lines in a floating state; and potential detection means for detecting the potential of one bit line in response to the selection of the word line selection means and the bit line selection means; 2. The semiconductor memory device according to claim 1, wherein the first and second potentials are the same potential. (3) The potential detection means is a sense amplifier to which a reference potential that is approximately 1/2 of the first and second potentials is input, and the sense amplifier compares the reference potential and the bit line potential. 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device outputs the comparison results. (4) The semiconductor memory device according to claim 2 or 3, wherein during writing, the potential difference between the first and second potentials is set to be equal to or higher than a predetermined potential. (5) In a semiconductor memory device in which field effect transistors having a pair of source/drain on a well surface and having a ferroelectric material as a gate insulating film are arranged in a matrix, the same as each of the above field effect transistors. Paired on the column,
A dummy field effect transistor having a ferroelectric gate insulating film in which data complementary to the field effect transistor is stored; a word line group commonly connecting the gate electrodes of the transistors in each row; and a dummy transistor in each row. a group of dummy word lines that commonly connect the gate electrodes of the transistors; a group of bit lines that commonly connect one of the sources and drains of the transistors in each row; and a group of dummy bit lines that commonly connects one of the sources and drains of the dummy transistors in each row. , a semiconductor comprising a plate line group commonly connecting the other source/drain of the transistors in each column and the other source/drain of the dummy transistor, and supplying a well potential to each transistor and the dummy transistor. Storage device. (6) Word line selection means that selectively sets a pair of word lines and dummy word lines to a first potential and puts other word lines and dummy word lines in a floating state, and only one plate line. is selectively set to a second potential,
Plate line selection means for setting the other plate lines in a floating state; and potential detection means for detecting the potentials of a pair of bit lines and dummy bit lines in response to selection by the word line selection means and the bit line selection means. 6. The semiconductor memory device according to claim 5, wherein the first and second potentials are set to the same potential during reading. (7) The semiconductor memory device according to claim 6, wherein the potential detection means compares a bit line potential and a dummy bit line potential and outputs a comparison result. (8) The semiconductor memory device according to claim 6 or 7, wherein during writing, the potential difference between the first and second potentials is set to be equal to or higher than a predetermined potential. (9) The ferroelectric material constituting the gate insulating film is Pb(Z
9. The semiconductor memory device according to any one of claims 1 to 8, characterized in that the semiconductor memory device is R, Ti)O_3. (10) The semiconductor memory device according to claim 9, wherein the composition ratio of Zr in the Pb(Zr,Ti)O_3 ferroelectric material is 0.6 or less. (11) The semiconductor memory device according to any one of claims 1 to 10, wherein the ferroelectric material constituting the gate insulating film has a thickness of 0.5 μm or less.