JPH04190620A - Halt end control system for protective relay - Google Patents

Halt end control system for protective relay

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Publication number
JPH04190620A
JPH04190620A JP2316091A JP31609190A JPH04190620A JP H04190620 A JPH04190620 A JP H04190620A JP 2316091 A JP2316091 A JP 2316091A JP 31609190 A JP31609190 A JP 31609190A JP H04190620 A JPH04190620 A JP H04190620A
Authority
JP
Japan
Prior art keywords
circuit
output
terminal
defective
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2316091A
Other languages
Japanese (ja)
Inventor
Takamichi Sadagami
貞神 高道
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2316091A priority Critical patent/JPH04190620A/en
Publication of JPH04190620A publication Critical patent/JPH04190620A/en
Pending legal-status Critical Current

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  • Emergency Protection Circuit Devices (AREA)

Abstract

PURPOSE:To prevent device lock at an operating end in case of defective receiving data at a halt end by controlling the other end as a halt end at its own end if a data received at the other end is defective. CONSTITUTION:When a data received at end B is defective, a NOT circuit 3 outputs an output 0, AND circuits 5, 6 also output 0 and thereby the output at terminal Q of an F/F circuit 7 is 0. Since a NOT circuit 9 has output 1, an AND circuit 10 also has output 1 and a defective transmission circuit 11 decides a defective transmission and locks a device. When a forcible control circuit 12 is operated under that state, an AND circuit 13 has output 1 and an OR circuit 14 also has an output 1. Input terminal S of the F/F circuit 7 has 1 while input terminal R thereof has 0 and the output terminal Q has 1 and thereby decision of terminal B halt is made. Consequently, the AND circuit 10 has an output 0 and the defective transmission circuit 11 does not perform detection of defect and the device is unlocked.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は保護継電装置の休止端制御方式に関する。[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a dead end control method for a protective relay device.

(従来の技術) 電流差動リレーは各端子の電流値から事故点電流を検出
するもので、2端子送電線だけでなく、多端子送電線に
も適用できる。そのためには各端子の電流波形を相手端
子へ伝送する必要があり、ディジタルリレーシステムで
は各端子電流の瞬時値データをディジタル量に変換して
符号化し、PCM (PuQse Code Modu
lation)伝送方向で相手端へ伝送している。この
ように伝送されてきた各端子の電流データを収集して判
定処理するマイクロコンピュータで構成したものがディ
ジタル電流差動リレーである。このため、送電線各端子
でデータのサンプリング同期をとって各端子同時刻のデ
ータを抽出し、このデータを加算することで伝送遅れ補
償などの操作なしに正確な差電流を得られるようにして
いる。
(Prior Art) A current differential relay detects a fault point current from the current value of each terminal, and can be applied not only to two-terminal power transmission lines but also to multi-terminal power transmission lines. To do this, it is necessary to transmit the current waveform of each terminal to the other terminal, and in a digital relay system, the instantaneous value data of each terminal current is converted into a digital quantity, encoded, and converted into PCM (PuQse Code Mod).
lation) is being transmitted to the other end in the transmission direction. A digital current differential relay is constructed with a microcomputer that collects and processes the transmitted current data of each terminal in this way. For this reason, by synchronizing data sampling at each terminal of the power transmission line and extracting data at the same time from each terminal, and adding this data, it is possible to obtain an accurate difference current without performing operations such as compensating for transmission delays. There is.

サンプリング同期をとる方法として、信号端局の発生す
る同期信号をもとに、各端子電流の同時サンプリングを
行なう方式と、サンプリング同期機能をリレー側に同層
した方式があるが、本発明では2つの方式の違いは目的
に関連しないため説明は省き、後者の構成についてのみ
第2図で説明する。
There are two methods for achieving sampling synchronization: one is to simultaneously sample the current at each terminal based on the synchronization signal generated by the signal terminal station, and the other is to have the sampling synchronization function on the same layer as the relay side. Since the difference between the two systems is not related to the purpose, the explanation will be omitted, and only the latter configuration will be explained with reference to FIG.

第2図において、入力変換器31はA端子の変流器CT
−1を介した系統電気量iLが入力され、アナログ入カ
ニニット32に導入され、アナログフィルタ33を介し
た後サンプル・ホールド回路(S/H)34、アナログ
・ディジタル変換器(A/D)35で所定のサンプリン
グ同期毎にディジタルデータに変換され、システムバス
36を介して伝送制御ユニット37及び演算ユニット4
1へ導入される。伝送制御ユニット37ではパラレル・
シリアル変換回路(P/5)38により伝送装置を介し
て相手端へデータを送信する。相手端のデータは伝送装
置を介してシリアル・パラレル変換回路(S/P)39
により受信し、システムバス36を介して演算ユニット
41へ導入される。サンプリング同期制御回路(SYN
C)40はサンプル・ホールド回路(S /H)34と
シリアル・パラレル変換回路(S/P)39のサンプル
同期を合せるようサンプル・ホールド回路(S/H)3
4のサンプリングタイミングの制御を行なう。演算ユニ
ット41はディジタル変換器(AD)35のデータとシ
リアル・パラレル変換器39のデータを加算し、差電流
が整定値以上のときしゃ断器CB−1を引外す指令を出
す。
In FIG. 2, the input converter 31 is a current transformer CT at the A terminal.
-1, the system electricity quantity iL is inputted, introduced into the analog input crab unit 32, passed through the analog filter 33, and then sampled and held circuit (S/H) 34 and analog/digital converter (A/D) 35. is converted into digital data at every predetermined sampling synchronization, and sent to the transmission control unit 37 and the arithmetic unit 4 via the system bus 36.
1 will be introduced. In the transmission control unit 37, parallel
The serial conversion circuit (P/5) 38 transmits data to the other end via the transmission device. The data at the other end is sent to the serial/parallel conversion circuit (S/P) 39 via the transmission device.
and is introduced into the arithmetic unit 41 via the system bus 36. Sampling synchronization control circuit (SYN
C) 40 is a sample and hold circuit (S/H) 3 to match the sample synchronization between the sample and hold circuit (S/H) 34 and the serial/parallel conversion circuit (S/P) 39.
The sampling timing of step 4 is controlled. The arithmetic unit 41 adds the data of the digital converter (AD) 35 and the data of the serial/parallel converter 39, and issues a command to trip the circuit breaker CB-1 when the difference current exceeds a set value.

第3図はPCM伝送方式に使用している各端子の情報を
送るための伝送フォーマットで、60Hz系に適用して
いるものの一実施例である。1スーパーフレーム(16
,67鳳S)は900ビツトで構成され1フレーム=7
5ビツトの内訳は、フレーム同期信号6ビツト、各端子
電流の瞬時値データ36ビツト(12ビツトの3相分)
、制御信号12ビツト(制御信号でしゃ断器の入切情報
、点検指令情報および同期制御信号等を送っている。)
およびCRCチエツク信号(CycJic Redan
dancy Check)により構成されている。CR
Cチエツク信号は通信関連で符号誤まりを検出するため
一般的に使用されている方式で本装置では受信4号の誤
まりを検出し、ビットの単発不良を確実に検出させるよ
うにしている。又、制御信号ではフレーム同期およびサ
ンプリング同期の制御をすると共に同期がとれていない
ときは不良検出を行なっている。上記CRCチエツクで
符号誤まり又は同期不良を検出したときは受信データネ
良と判定し、装置ロックおよび警報表示を行なうのが一
般的である。又、電源を切にした場合も上記制御信号を
送れないため受信データネ良と判定される。
FIG. 3 shows a transmission format for sending information from each terminal used in the PCM transmission system, and is an example of the format applied to the 60 Hz system. 1 super frame (16
, 67F) consists of 900 bits, and 1 frame = 7
The 5 bits consist of 6 bits of frame synchronization signal, 36 bits of instantaneous value data of each terminal current (3 phases of 12 bits).
, 12-bit control signal (control signal sends breaker on/off information, inspection command information, synchronous control signal, etc.)
and CRC check signal (CycJic Redan)
dancy Check). CR
The C-check signal is a system generally used to detect code errors in communications, and this device detects errors in received No. 4 to reliably detect single-bit defects. Further, the control signal controls frame synchronization and sampling synchronization, and detects a failure when synchronization is not achieved. When a code error or synchronization failure is detected in the CRC check, it is generally determined that the received data is defective, and the device is locked and an alarm is displayed. Furthermore, even when the power is turned off, the control signal cannot be sent, so it is determined that the received data is defective.

第4図は従来の休止端制御回路でA端子の場合について
示している。1はCF検出回路(受信データネ良検出回
路)、2はB端のCB (Lや断器)空検出回路、3及
び4はN07回路で、CF検出回路1が不良検出したと
きN01回路3は出力01CB切検出回路2が切検出し
たときNOT回路4は出力Oとなる。5及び6はAND
回路で、N01回路3の出力1のとき、CB切切出出回
路2切検出したときはAND回路5が出力1、又、切検
出しないときはAND回路6が出力1となる。7はF/
F回路(フリップフロップ回路)で入力端子Sが1、R
がOのとき出力端子Qは出力1となりB端体止と判定す
る。入力端子SがO,Rが1のとき出力端子Qは出力0
となりB端運用と判定する。又、入力端子S、Rともに
Oのときは出力端子Qは前値保持となっている。8はB
端電流零制御回路でF/F回路7のQの出力1のときは
B端体止と判定し、B端の受信電流データを零に制御す
る。9はN07回路でF/F回路7のQの出力1のとき
出力Oとなる。10はAND回路でCF検出回路1が検
出し、およびB端運用中でOR回路9の出力1のとき出
力1となる。11は伝送不良検出回路で、B端の受信デ
ータネ良のときAND回路10の出力1となると伝送不
良と判定し装置ロックを行なう。
FIG. 4 shows the case of the A terminal in a conventional rest end control circuit. 1 is a CF detection circuit (received data failure detection circuit), 2 is a CB (L or disconnection) empty detection circuit at the B end, 3 and 4 are N07 circuits, and when CF detection circuit 1 detects a defect, N01 circuit 3 is activated. When the output 01CB disconnection detection circuit 2 detects disconnection, the NOT circuit 4 becomes the output O. 5 and 6 are AND
In the circuit, when the output of the N01 circuit 3 is 1, the AND circuit 5 outputs 1 when the CB cutting/cutting circuit 2 detects disconnection, and the AND circuit 6 outputs 1 when the disconnection is not detected. 7 is F/
Input terminal S is 1 and R is F circuit (flip-flop circuit).
When is O, the output terminal Q becomes an output 1, and it is determined that the B end is stopped. When input terminal S is O and R is 1, output terminal Q outputs 0.
Therefore, it is determined that it is B-end operation. Further, when the input terminals S and R are both O, the output terminal Q holds the previous value. 8 is B
The end current zero control circuit determines that the B end is stopped when the Q output of the F/F circuit 7 is 1, and controls the received current data at the B end to zero. 9 is a N07 circuit, and when the Q output of the F/F circuit 7 is 1, the output becomes O. 10 is an AND circuit which is detected by the CF detection circuit 1, and becomes output 1 when the output of the OR circuit 9 is 1 during B-terminal operation. Reference numeral 11 denotes a transmission failure detection circuit, which determines that there is a transmission failure and locks the device if the output of the AND circuit 10 becomes 1 when the received data at the B end is good.

第5図は従来の休止端制御回路の動作を説明するための
図である。以下、第5図の保護系統における第4図の休
止端制御回路の動作について説明する。
FIG. 5 is a diagram for explaining the operation of a conventional rest end control circuit. The operation of the rest end control circuit shown in FIG. 4 in the protection system shown in FIG. 5 will be described below.

第5図のはA、B端共CB入、B端受信データ正常の場
合である。このときはCF検出回路1、CB切切出出回
路2共に検出しないため、AND回路5は出力Oで、N
01回路3.4共出力OのためAND回路6の出力1、
このためF/F回路7の入力端子Sは0、Rは1のため
出力端子Qは出力OとなりB端運用と判定する。このた
めB端電流零制御回路8ではB端の電流データの零制御
は行なわない。又、B端の受信データ正常なためAND
回路10は出力0となり、伝送不良検出回路llも伝送
不良の検出は行なわない。
FIG. 5 shows a case where both the A and B ends have CB input and the B end reception data is normal. At this time, neither the CF detection circuit 1 nor the CB cutout circuit 2 is detected, so the AND circuit 5 outputs O and N
Since both circuits 3 and 4 output O, the output of AND circuit 6 is 1,
Therefore, since the input terminal S of the F/F circuit 7 is 0 and the input terminal R is 1, the output terminal Q becomes an output O, and it is determined that the B-end operation is performed. Therefore, the B-end current zero control circuit 8 does not perform zero control of the B-end current data. Also, since the received data at the B end is normal, AND
The output of the circuit 10 becomes 0, and the transmission failure detection circuit 11 does not detect a transmission failure.

第5図■は、上記■状態からB端CB切操作を行なった
場合である。このときはCB切切出出回路2検出し、A
ND回路5は出力1、AND回路6は出力0に制御する
ためF/F回路7の入力端子Sは1.Rは0のため出力
端子Qは出力1となりB端体止と判定し、B端電流零制
御回路8ではB端の電流データの零制御を行なう。
FIG. 5 (■) shows the case where the B-end CB cutting operation is performed from the above-mentioned state (2). At this time, the CB cutout circuit 2 is detected, and the A
In order to control the ND circuit 5 to output 1 and the AND circuit 6 to output 0, the input terminal S of the F/F circuit 7 is controlled to 1. Since R is 0, the output terminal Q becomes an output 1, and it is determined that the B end is stopped, and the B end current zero control circuit 8 performs zero control of the current data at the B end.

第5図■は、上記■状態からB端電源切のためB端の受
信データネ良となった場合である。このときはCF検出
回路1、CB切切出出回路2共に検出しているが、NO
T回路3は出力0のためAND回路5,6共出力0とな
る。このためF/F回路7の入力端子S、R共0で出力
端子Qの出力は前値保持となるため、第5図■の状態と
同じく出力1となりB端体止と判定したままとなる。こ
のためCF検出回路1が検出してもB端体止のためNO
T回路9は出力OとなりAND回路10は出力0となっ
ている。このためB端の受信データネ良となっても伝送
不良検出回路11では伝送不良と検出しない。
FIG. 5 (■) shows a case where the received data at the B end becomes invalid due to the B end power being turned off from the above state (2). At this time, both the CF detection circuit 1 and the CB cutout circuit 2 are detected, but NO
Since the T circuit 3 has an output of 0, both AND circuits 5 and 6 have an output of 0. For this reason, the input terminals S and R of the F/F circuit 7 are both 0, and the output of the output terminal Q holds the previous value, so the output becomes 1, which is the same as the state shown in Figure 5 (■), and it remains determined that the B end is stopped. . Therefore, even if the CF detection circuit 1 detects it, it will be NO because the B end is stopped.
The T circuit 9 has an output of 0, and the AND circuit 10 has an output of 0. Therefore, even if the received data at the B end is defective, the transmission failure detection circuit 11 does not detect it as a transmission failure.

(発明が解決しようとする課題) 第6図は従来技術の問題点を説明するための図である。(Problem to be solved by the invention) FIG. 6 is a diagram for explaining the problems of the prior art.

第6図■はA、B端共CB切で電源切のため保護機能自
体が停止している。
In Fig. 6 (■), the protection function itself has stopped because the CB is disconnected at both ends A and B, and the power is turned off.

第6図■は上記■状態からA端電源人とした場合である
。A端の保護機能が正常に働いているためB端の受信デ
ータネ良を検出する。このときはCF検出回路1が検出
しNOT回路3は出力Oとなり、AND回路5,6共出
力OでF/F回路7の出力端子Qは前値保持となるが、
通常ディジタル形電流差動リレーの休止端制御方式では
電源切から入とするとき、インシャライズ機能よりF/
F回路7の出力端子Qは出力OでB端運用にセットされ
ている。このため前値のB端運用となる。
Figure 6 (■) shows the case where the A-terminal power source is switched from the above-mentioned state (■). Since the protection function of the A end is working normally, a reception data failure of the B end is detected. At this time, the CF detection circuit 1 detects the output, the NOT circuit 3 outputs O, and the AND circuits 5 and 6 output O, and the output terminal Q of the F/F circuit 7 retains its previous value.
Normally, in the rest end control method of a digital current differential relay, when turning on the power from OFF, the initialize function activates the F/
The output terminal Q of the F circuit 7 is set to the output O and B-end operation. Therefore, the B end of the previous price will be used.

このためCF検出回路1が検出し、NOT回路9は出力
1で、A N ’D回路10は出力1となり伝送不良回
路11が伝送不良と判定し、装置ロックを行なう。
Therefore, the CF detection circuit 1 detects it, the NOT circuit 9 outputs 1, the A N'D circuit 10 outputs 1, and the transmission failure circuit 11 determines that there is a transmission failure and locks the device.

第6図■は上記■状態からA@CB人で片端運用となっ
た場合で、伝送不良と判定され装置ロックされたままと
なっている。このためA、B区間に事故が発生してもA
端の保護装置ではCBの引外しが出来ず、事故除去を行
なうことが出来ない。
Figure 6 (■) shows a case where one-end operation is performed with A@CB person from the above-mentioned state (■), and it is determined that there is a transmission failure and the device remains locked. Therefore, even if an accident occurs in sections A and B,
With the protection device at the end, the CB cannot be tripped and the accident cannot be removed.

このように第6図■〜■の操作を行なうと装置ロックさ
れたままとなるため、必ず第5図■〜■の手順で行なわ
なければならない、しかし、第6図の操作が行なわれる
ことも考えられるので、万−B端電源不良のとき、B@
CB切でA端のみCB人で運用しようとしても受信デー
タネ良検出後B端CB切となるため、A端では伝送不良
を検出し装置ロックとなるため保護装置による事故除去
が期待出来ない。
If you perform the operations shown in Figure 6 ■ to ■ in this way, the device will remain locked, so you must always follow the steps shown in Figure 5 ■ to ■. However, the operations shown in Figure 6 may also be performed. This is possible, so when there is a power failure at the 10,000-B terminal, B@
Even if an attempt is made to operate only the A end by a CB person with the CB turned off, the B end CB will be turned off after detecting a fault in the received data, and the A end will detect a transmission failure and lock the device, so it cannot be expected that the protection device will eliminate the accident.

本発明は上記問題点を解決するためなされたものであり
、休止端の受信データネ良のとき運用端が装置ロックを
生じない保護継電装置の休止端制御方式を提供すること
を目的としている。
The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide an inactive end control method for a protective relay device that does not cause the operating end to lock up when the received data at the inactive end is faulty.

〔発明の構成〕[Structure of the invention]

(課題を解決するための手段) 上記目的を達成するため、本発明は多端子送電線を保護
するために各端子に設けたディジタル形電流差動リレー
の休止端制御方式において、他端子の受信データネ良時
は自端で他端子を休止端扱いに制御出来るよう構成した
、 (作 用) 受信データネ良検出中は休止端制御が出来なかったが1
本発明では受信データネ良中は強制々御条件で休止端制
御を行なうようにした結果、系統のCB操作手順により
運用端が伝送不良により不良に装置ロックされるのを防
止出来るようになった。
(Means for Solving the Problems) In order to achieve the above object, the present invention provides a method for controlling the idle end of a digital current differential relay provided at each terminal in order to protect a multi-terminal power transmission line. When the data is good, the terminal is configured so that other terminals can be controlled as if they are at rest.
In the present invention, as a result of forcibly controlling the idle end of the receiving data channel under controlled conditions, it has become possible to prevent the active end from being improperly locked due to transmission failure through the CB operation procedure of the system.

(実施例) 以下第1図により本発明の詳細な説明する。(Example) The present invention will be explained in detail below with reference to FIG.

第1図ではA端子の場合について、説明しているがB端
子も同様な構成を有している。尚、第1図において第4
図と同一部分については同一符号を付けている。
Although FIG. 1 describes the case of the A terminal, the B terminal also has a similar configuration. In addition, in Figure 1, the 4th
The same parts as those in the figure are given the same reference numerals.

第1図において符号1〜11は第4図と同一の機能のた
め説明を省略し、第4図と相違する部分について説明す
る。12は強制々四回路で切換スイッチ又は切換端子等
により制御する。13はAND回路でB端受信データネ
良のときCF検出回路1が検出し且つ、強制々四回路1
2で制御したとき出力1となる。14はOR回路でAN
D回路5又は13のいずれか出力1のとき出力1となる
。又強制々四回路12は通常は制御していないため、A
ND回路13は出力0となっている。ゆえにF/F回路
7は第4図と同様にAND回路5,6だけで制御されて
いる。このため第5図■〜■の場合は第4図と同じ動作
を行なう。
In FIG. 1, reference numerals 1 to 11 have the same functions as those in FIG. 4, so explanations thereof will be omitted, and only portions that are different from those in FIG. 4 will be explained. Reference numeral 12 is a four-circuit circuit that is controlled by a changeover switch or a changeover terminal. 13 is an AND circuit, which is detected by the CF detection circuit 1 when the B-end received data is good, and forcibly connects the four circuits 1 to 4.
When controlled with 2, the output is 1. 14 is an OR circuit
When the output of either D circuit 5 or 13 is 1, the output becomes 1. Also, since the forced four circuit 12 is not normally controlled, A
The ND circuit 13 has an output of 0. Therefore, the F/F circuit 7 is controlled only by the AND circuits 5 and 6 as in FIG. Therefore, in the cases shown in FIGS. 5-5, the same operations as in FIG. 4 are performed.

次に従来装置で問題となっていた第6図■の場合、B端
受信データネ良のためNOT回路3は出力Oとなり、A
ND回路5,6は出力Oとなる。
Next, in the case of Fig. 6 (■), which was a problem with the conventional device, the NOT circuit 3 outputs O because the B end received data is faulty, and the A
The outputs of the ND circuits 5 and 6 are O.

又F/F回路7の入力端子S、RともにOで出力端子Q
の出力は前値保持のため出力OでB端運用となっている
。このとき、CF検出回路1が不良検出し、B端運用の
ためNOT回路9は出力1となるのでAND回路10は
出力1となり、伝送不良回路11は伝送不良と判定し装
置ロックを行なう。
Also, the input terminals S and R of the F/F circuit 7 are both O, and the output terminal Q
In order to maintain the previous value, the output is set to O for B-end operation. At this time, the CF detection circuit 1 detects a failure, and the NOT circuit 9 has an output of 1 due to B-terminal operation, so the AND circuit 10 has an output of 1, and the transmission failure circuit 11 determines that there is a transmission failure and locks the device.

この状態で強制々四回路12を制御すると、CF検出回
路1が検出しているためAND回路13は出力1となり
、OR回路14も出力1となる。このためF/F回路7
の入力端子Sは1、RはOとなり出力端子Qの出力1で
B端体止と判定する。
If the four circuits 12 are forcibly controlled in this state, the AND circuit 13 will have an output of 1 because the CF detection circuit 1 has detected it, and the OR circuit 14 will also have an output of 1. Therefore, F/F circuit 7
The input terminal S of the input terminal S is 1, and the input terminal R is O, so that the output terminal Q of the output terminal Q is 1, and it is determined that the B end is stopped.

このため、B端電流零制御回路8ではB端の受信データ
を零制御すると共に、NOT回路9を出力Oとするので
AND回路10は出力Oとなり伝送不良回路11は不良
検出を行なわず装置ロックも解除される。
Therefore, the B-terminal current zero control circuit 8 controls the received data at the B-terminal to zero, and the NOT circuit 9 outputs O, so the AND circuit 10 outputs O, and the transmission failure circuit 11 does not detect a failure and locks the device. will also be canceled.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、運用端で強制々御
条件により休止端制御を行なえるため、運用操作上の制
約ない装置ロックの解除が出来る休止端制御を行なうこ
とが可能となる。
As described above, according to the present invention, since the idle end control can be performed under forced control conditions at the active end, it is possible to perform the idle end control that allows the device to be unlocked without any operational restrictions.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による休止端制御方式を説明するための
実施例回路図、第2図はディジタル形電流差動リレーの
構成図、第3図は伝送方式の伝送フォーマット、第4図
は従来の休止端制御回路図、第5図及び第6図は休止端
制御の動作を説明する図である。 1・・・受信データネ良検出回路 2・・・CB切検出回路 3.4.9・・・NOT回路 5、6.10.13・・・AND回路 7・・・フリップフロップ回路 8・・・受信電流零制御回路 11・・・伝送不良検出回路 12・・強制々四回路 14・・・OR回路 代理人 弁理士  則 近 憲 佑 第1図 C鳩子 第4図 Afil                B端A端電
源λ            B端電源入A請V電涛入
            B搗電源、入第5図
Fig. 1 is an embodiment circuit diagram for explaining the dead end control method according to the present invention, Fig. 2 is a configuration diagram of a digital current differential relay, Fig. 3 is a transmission format of the transmission method, and Fig. 4 is a conventional one. The rest end control circuit diagrams of FIGS. 5 and 6 are diagrams for explaining the operation of rest end control. 1... Received data error detection circuit 2... CB disconnection detection circuit 3.4.9... NOT circuit 5, 6.10.13... AND circuit 7... Flip-flop circuit 8... Reception current zero control circuit 11...Transmission failure detection circuit 12...Forced four circuit 14...OR circuit Agent Patent attorney Noriyuki Chika Figure 1 C Hatoko Figure 4 Afil B end A end power supply λ B End power supply A connection V power supply input B power supply, input Figure 5

Claims (1)

【特許請求の範囲】[Claims] 多端子送電線を保護するため各端子に設けた電流差動保
護継電装置の休止端制御方式において、他端子の伝送不
良検出中は自端で他端子を休止端扱いに制御することを
特徴とする保護継電装置の休止端制御方式。
In the idle end control method of a current differential protection relay device installed at each terminal to protect a multi-terminal power transmission line, the other terminal is controlled to be treated as an idle end while a transmission failure is detected at the other terminal. A rest end control method for a protective relay device.
JP2316091A 1990-11-22 1990-11-22 Halt end control system for protective relay Pending JPH04190620A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2316091A JPH04190620A (en) 1990-11-22 1990-11-22 Halt end control system for protective relay

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2316091A JPH04190620A (en) 1990-11-22 1990-11-22 Halt end control system for protective relay

Publications (1)

Publication Number Publication Date
JPH04190620A true JPH04190620A (en) 1992-07-09

Family

ID=18073142

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2316091A Pending JPH04190620A (en) 1990-11-22 1990-11-22 Halt end control system for protective relay

Country Status (1)

Country Link
JP (1) JPH04190620A (en)

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