JPH04189044A - Serial data receiver - Google Patents

Abstract

PURPOSE:To ensure data reception even when a sent serial data is moved by stopping the input of a synchronizing signal to a synchronization matching circuit till a moving direction of a clock change point is discriminated. CONSTITUTION:The position of a change point of a received clock is detected again and the result is fed to a clock inversion/noninversion discrimination circuit 34, and when the result of discriminating the moving direction and a change point of the received clock are discriminated to be inadequate, the phase of the received clock from a synchronizing matching circuit 38 is inverted. Thus, the received clock is fixed within a range of 1/4 of a 1-bit data and even when a deviation exists between the data and the received clock at the fixed position, the clock is fixed to a position where no error takes place.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a serial data receiving device that receives and processes multi-bit serial data without a synchronization signal and a transfer clock from a transmitting side.

[Prior Art] This type of serial data receiving device receives no transfer clock from the transmitting side, and receives only a synchronization signal indicating the start timing of data transfer to receive and process serial data.

Conventionally, as such a serial data receiving device, a third
The one shown in the figure is known. That is, the buffer 1 receives the synchronization signal and multiple bits of serial data from the transmitter T, and supplies the synchronization signal from the buffer 1 to the phase comparator 2 and timing control circuit 3, and also supplies the data to the sampling circuit 4. ing.

The phase comparator 2 includes a low pass filter 5 and a voltage controlled oscillator 6.
, and a frequency divider 7 constitute a PLL (phase locked loop) circuit A, and a signal from a phase comparator 2 is supplied to a voltage controlled oscillator 6 via a low-pass filter 5. Further, the reception clock generated from the voltage controlled oscillator 6 is supplied to the sampling circuit 4, the timing control circuit 3, and the frequency divider 7, respectively, and the output of the frequency divider 7 is supplied to the phase comparator 2. The reception clock generated from the voltage controlled oscillator 6 is adjusted to be synchronized with the input synchronization signal, and the sampling circuit 4 samples data using this reception clock and stores it in the memory 8.

The data stored in the memory 8 is read out under the control of the address generator 10 by the CPU 9 and sent to the main memory 1.
1 is stored.

[Problems to be Solved by the Invention] By the way, there is a time lag between the synchronization signal from the transmitter T and the start timing of data transfer, and the width of this lag differs from transmitter to transmitter. When unreal data transfer is performed at such a high speed that this deviation cannot be ignored, in the conventional device, the reception clock synchronized with the synchronization signal may rise near the end of the data. When a large number of bits are received in this state, there is a problem that the same bit is read twice or one bit of data is omitted due to the difference between the transmitting frequency and the receiving frequency.

Therefore, the present invention provides serial data reception that allows reliable data reception without reading the same bit twice or missing bit data even when data of many bits is serially transferred at one time at high speed. The aim is to provide equipment.

Means for Solving 1 Problem] The present invention provides a serial system that receives multi-bit serial data without a synchronization signal and a transfer clock from a transmitting side, and captures the data in synchronization with a reception clock from a reception clock generation means. In the data receiving device, the reception clock generation means divides 1-bit data into n (n is an integer of 4 or more) and detects in which range of the n-divided data the changing point of the reception clock is located. A change point position detection circuit, a detection result holding circuit that temporarily holds the detection result of this detection circuit, and a clock that compares the detection result held in this holding circuit with the new detection result from the clock change point position detection circuit. A clock change point moving direction determination circuit that determines the moving blade and direction of the change point, and whether or not to invert the phase of the received clock by 180 degrees based on the determination result of this determination circuit and the detection result of the clock change point position detection circuit. A clock inversion/non-inversion determination circuit that determines, a clock inversion circuit that inverts the phase of the reception clock by 180 degrees when this determination circuit determines inversion, and a clock inversion circuit that inverts the phase of the reception clock by 180 degrees, and a shift width of the change point of the reception clock with respect to the bit data to be received. An oscillator whose frequency is set to have a width smaller than 1 of the 1-bit data in the initial signal period, and the frequency from this oscillator is divided to generate n within the 1-bit data width of the received bit data.
A frequency divider that outputs reception clocks with different phases, and a frequency divider output that is selected and synchronized so that the change point of the reception clock is fixed within a range of 1/0 with respect to the manually input synchronization signal. It consists of a synchronization circuit that performs synchronization, and stops inputting a synchronization signal to the synchronization circuit until the clock change point movement direction determination circuit determines the movement direction of the clock change point.

[Operation] In the present invention having such a configuration, when a synchronization signal and serial data are received from the transmitting side, the 1-bit data is divided into n parts, and the change point of the reception clock is located in which range of the n divided data. or detect. This detection result is temporarily held in a detection result holding circuit, and the movement direction of the clock change point is determined by comparing the held detection result with a new detection result from the clock change point position detection circuit.

When the moving direction of the clock changing point is determined by the clock changing point movement direction determining circuit, a synchronization signal is input to the synchronization circuit, and the frequency is divided to be fixed within the range of 1/n of the changing point of the received clock. Synchronization is performed by selecting the device output.

Furthermore, the phase of the received clock is changed to 18 based on the movement direction determination result and the new detection result of the clock change point position detection circuit.
Determine whether or not to invert 0 degrees.

A signal from the synchronization circuit passes through a clock inversion circuit and becomes a reception clock, and data is taken in using the reception clock.

[Example code] Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1, T is a transmitter, and S is a serial data receiving device that receives multi-bit serial data without a synchronization signal and a transfer clock from the transmitter T, and takes in the data.

The serial data receiving device S includes a buffer 21 that receives a synchronization signal and serial data from the transmitter T, a reception clock generation means 22 that receives the synchronization signal and serial data from the buffer 21, and generates a reception clock.
A data holding circuit 23 that takes in and holds serial data from the buffer 21, a memory 24 that stores the data held by this data holding circuit 23, an address generator 25 that specifies an address when accessing this memory 24, and the reception A timing control circuit 26 that supplies timing signals to the clock generation means 22, the data holding circuit 23, and the address generator 25, respectively, and controls access to the memory 24 and the timing control circuit 2.
CPU (Central Processing Unit) 27, which performs control etc. of 6;
The main storage device 28 stores data read from the memory 24 for various processing purposes.

The reception clock generation means 22 divides 1-bit data into n parts, for example, into 4 parts, and includes a clock change point position detection circuit 31 that detects in which range of the 4 parts the received clock change point is located. A detection result holding circuit 32 that temporarily holds the detection result of the circuit 31, this holding circuit 3
Tarock change point movement direction determination circuit 33 that compares the detection result held in 2 and the new detection result from the clock change point position detection circuit 31 to determine the moving direction of the clock change point; A clock inversion/non-inversion determination circuit 34 determines whether or not to invert the phase of the received clock by 180 degrees based on the result and the detection result of the clock change point position detection circuit 31, and when this determination circuit 34 determines inversion, the reception A clock inversion circuit 35 inverts the phase of the clock by 180 degrees, and the frequency is set so that the shift width of the change point of the reception clock with respect to the bit data to be received is smaller than one-fourth of one bit data in one synchronization signal period. an oscillator 36, a frequency divider 37 that divides the frequency from the oscillator 36, and outputs four receive clocks with different phases within the 1-bit data width of the received bit data; The frequency divider 3 is arranged so that the change point of the received clock is fixed within a range of 1/4.
Synchronization circuit 3 that selects the output of 7 and performs synchronization
8 and an AND gate 39.

Data from the buffer 21 is supplied to the clock change point position detection circuit 31, and a synchronization signal is supplied to the synchronization circuit 38 via the AND gate 39.

The gate of the AND gate 39 is closed by the timing control circuit 26 until the clock change point movement direction determination circuit 33 determines the movement direction of the clock change point.
When the moving direction of the clock change point is determined, the timing control circuit 26 opens its gate and supplies the synchronization signal from the buffer 21 to the synchronization circuit 38.

In such an embodiment, the serial data receiver S receives a plurality of synchronization signals and data from the transmitter T in order to synchronize the receive clock with the data from the transmitter T. That is, multiple bits of serial transfer data are received during a synchronization signal period as shown in FIG. 2(a) and one synchronization signal period as shown in FIG. 2(b).

This synchronization period becomes a dummy data transfer period, and during this period, the timing control circuit 26 closes the gate of the AND gate 39 and stops inputting the synchronization signal to the synchronization circuit 38.

The synchronization circuit 38 selects one predetermined clock from among the four clocks having different phases from the frequency divider 37, and outputs it as a reception basic clock as shown in FIG. 2(C). This reception basic clock is supplied to the data holding circuit 23 as a reception clock via the clock inversion circuit 35, as shown in FIG. 2(d).

On the other hand, the clock change point position detection circuit 31
It inputs the data from and detects the changing point of the reception clock or the position of the 1-bit data divided into four.

In the example of FIG. 2, the change point of the received clock exists within the left end region of the four divided regions.

This detection result is held in the detection result holding circuit 32. Then, the clock change point movement direction determination circuit 33 determines whether there has been a movement (deviation) of more than one divided area from the detection result held in the detection result holding circuit 32 and the newly detected change point position by the clock change point position detection circuit 31. Check and
Determine in which direction the change point of the reception clock is moving relative to the data.

Note that since the received clock is asynchronous with the transmitted synchronization signal and data, the phase may shift over time, but the width of the shift between the synchronization signal and data and the reception clock that occurs in one synchronization signal period can be calculated by one pin point data. Width t of the area divided into four. It needs to be contained within. In other words, in Fig. 2, the width of the area divided into four by the difference between the synchronization signal and the reception clock (B-A) and the difference between the data and the reception clock (D-C) is 1.
, must be less than or equal to.

When the clock change point movement direction judgment circuit 33 completes the movement direction judgment, the timing control circuit 26 opens the AND gate 39.

As a result, the synchronization signal from the buffer 21 is supplied to the synchronization circuit 38 via the AND gate 39, the clocks are synchronized in the synchronization circuit 38, and the received clock signal is output from the clock inversion circuit 35. The change point is 4 bits of 1-bit data relative to the synchronization signal.
It becomes fixed within the area of 1/2.

The changing point of the received clock at this time is detected again by the clock changing point position detection circuit 31, and the detection result is supplied to the clock inversion/non-inversion determination circuit 34. Then, in the clock inversion/non-inversion determination circuit 34, based on the movement direction determination result by the clock change point movement direction determination circuit 33 and the detection result from the clock change point position detection circuit 31, 1
When it is determined that the change point of the received clock is at an inappropriate position with respect to the bit data, the determination circuit 34 controls the clock inversion circuit 35 to invert the phase of the received clock from the synchronization circuit 38 by 180 degrees.

For example, if there is a clock change point in the leftmost area of 1-bit data divided into four, and this changing point moves to the left, or if there is a clock change point in the rightmost area, and this changing point moves to the right. In this case, there is a possibility that the clock change point will eventually deviate from the data area, so in this case it is determined that the clock change point is at an inappropriate position.

In this way, the receiving clock can be fixed within a range of 1/4 of the 1 bit data, and the fixed position is a position where no reading error will occur even if there is a discrepancy between the data and the receiving clock within one synchronization signal period. Can be set to

Therefore, the serial data transmitted after the dummy data transfer period can be reliably received without reading the same bit twice or missing bits even at high speed.

Although 1-bit data is divided into four in the above embodiment, it is not necessarily limited to this, and any division into four or more may be sufficient.

[Effects of the Invention] As detailed above, according to the present invention, even when a large number of bits of data are serially transferred at one time at high speed, reading the same bit twice or missing bit data does not occur. Therefore, it is possible to provide a serial data receiving device that can receive data reliably.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram showing the timing of each signal and data, and FIG. 3 is a block diagram showing a conventional example. 22... Reception clock generation means, 26... Timing control circuit, 31... Clock change point position detection circuit, 32... Detection result holding circuit, 33... Clock change point moving direction determination circuit, 34・・・
Clock inversion/non-inversion determination circuit, 35... Clock inversion circuit, 36... Oscillator 36. 37... Frequency divider, 38... Synchronization circuit. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Scope of Claims] In a serial data receiving device that receives multi-bit serial data without a synchronization signal and a transfer clock from a transmitting side, and captures the data in synchronization with a reception clock from a reception clock generation means, The clock generation means includes a clock change point position detection circuit that divides 1-bit data into n (n is an integer of 4 or more) and detects in which range of the n divided data the change point of the received clock is located;
A detection result holding circuit temporarily holds the detection result of this detection circuit, and a detection result held in this holding circuit is compared with a new detection result from the clock change point position detection circuit to determine the moving direction of the clock change point. A clock change point movement direction determination circuit for determining, and a clock inversion/non-inversion for determining whether or not to invert the phase of the received clock by 180 degrees based on the determination result of this determination circuit and the detection result of the clock change point position detection circuit. a determination circuit; a clock inversion circuit that inverts the phase of the reception clock by 180 degrees when the determination circuit determines inversion; An oscillator whose frequency is set to a width smaller than 1/n, and the frequency from this oscillator is divided to output n receive clocks with different phases within the 1-bit data width of the received bit data. Frequency divider and the change point of the received clock with respect to the input synchronization signal is 1/n
and a synchronization circuit that selects and synchronizes the frequency divider output so as to fix it within a range of A serial data receiving device characterized by stopping input of a synchronizing signal to a matching circuit.