JPH04188931A - Line driver circuit - Google Patents

Abstract

PURPOSE:To prevent the fluctuation of the pulse width of a pulse outputted to a line by monitoring a signal outputted to the line in order to detect the pulse width, and transmitting a clock signal whose pulse width is controlled to be an optimal value to an encoder based on this detected result. CONSTITUTION:A pulse width detecting circuit 7 detects the pulse width of the pulse outputted through a buffer 8 to the line, and converted it into a signal such as a voltage or a code. A pulse width controlling circuit 6 controls the pulse width of the clock signal from this signal in order to adjust the pulse width of the output of a driver 2 to be the optimal value. An encoder 1 converts the clock signal whose pulse width is controlled, and inputted data into a transmission path code, and outputs it through the driver 2 and an output transformer 3 to the line. Thus, the change of the pulse width of the pulse outputted to the line, due to the duty change of the clock signal, the variation of the driver circuit, and a temperature characteristic or the like, can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a line driver circuit, and particularly to a line driver circuit that sends a data signal to a transmission path.

[Conventional technology]

In the conventional line driver circuit, as shown in Figure 2,
It included an encoder 20, a driver 21, and an output transformer 22. The clock signal and the data signal are sent to the encoder 20.
The signal is input to the driver 21 and converted into an encoded transmission line signal. It was output to the line via the output transformer 22.

[Problem to be solved by the invention]

The conventional line driver circuit described above has a problem in that the pulse width of the pulse output to the line varies due to clock signals, variations in the driver circuit, temperature characteristics, and aging characteristics.

An object of the present invention is to solve the above-mentioned problems and to provide a line in which the pulse width of the pulse output to the line does not fluctuate due to variations in the driver circuit, temperature characteristics, aging characteristics, or due to input clock signals. The purpose of the present invention is to provide a driver circuit.

[Means to solve the problem]

The present invention provides a line driver circuit comprising an encoder that converts a data signal and a clock signal into a transmission line code, and a driver that outputs the transmission line code signal to a line via an output transformer. a pulse width detection control unit that monitors the signal output to the line to detect the pulse width, and based on the detection result, sends a tarok signal with the pulse width of the clock signal controlled to an optimal value to the encoder; It is characterized by having the following.

Further, the present invention provides the following method based on the data signal and the clock signal.
In a line driver circuit comprising an encoder that converts into a transmission line code and a driver that outputs the signal of the transmission line code to the line via an output transformer, the line driver circuit includes a buffer that monitors the signal output to the front input. , A pulse width detection circuit detects the pulse width from the output signal of this buffer, and based on the signal of this pulse width detection circuit,
The present invention is characterized by comprising a pulse width control circuit that controls the pulse width of the inputted clock signal to an optimum value and sends the clock signal to the encoder.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit block diagram showing one embodiment of the present invention.

This line driver circuit includes an encoder 1, a driver 2, an output transformer 3, and a pulse width detection control section 5,
The pulse width detection control section 5 includes a pulse width control circuit 6, a pulse width detection circuit 7, and a buffer 8.

The pulse width control circuit 6 of the pulse width detection control section 5 receives a clock signal having a predetermined pulse width. It is also connected to the pulse width detection circuit 7, and controls the pulse width of the clock signal input from the clock signal input terminal to an optimum value based on the signal from the pulse width detection circuit 7.

The encoder 1 inputs the data signal and the clock signal from the pulse width control circuit 6, and converts it into a transmission line code.

The driver 2 outputs the signal from the encoder 1 to the line via the output transformer 3.

Buffer 8 monitors the signal output to the line,
The signal is sent to the pulse width detection circuit 7.

The pulse width detection diagram N7 detects the pulse width from the signal from the buffer 8, converts it into a signal such as voltage and sign, and sends it to the pulse width control circuit 6.

Next, the operation of this embodiment will be explained. Driver 2.
The signal output to the line via the output transformer 3 is monitored by a buffer 8. The pulse width detection circuit 7 detects the pulse width of the pulse outputted to the line via the buffer 8, and converts it into a signal such as a voltage or a sign. Based on this signal, the pulse width control circuit 6 controls the pulse width of the clock signal and adjusts the pulse width of the output of the driver 2 to an optimum value. The encoder 1 converts the pulse width into a transmission path code based on the controlled clock and the input data, and the driver 2 . It is output to the line via the output transformer 3.

As explained above, the line driver circuit of the present invention includes a buffer that monitors the waveform output to the line, a pulse width detection circuit that detects the pulse width of the waveform output to the line from the buffer output of this buffer, and a pulse width detection circuit that detects the pulse width of the waveform output to the line from the buffer output of this buffer. A pulse width control circuit that controls the pulse width of a clock signal by the output of the width detection circuit, and a transmission path code based on the clock signal whose pulse width is controlled to an optimal value by this pulse width control circuit and the input data signal. It includes an encoder for conversion and a driver for outputting the output signal of the encoder to a line via an output transformer, and can control the pulse width of the clock signal to an optimal value.

〔Effect of the invention〕

As explained above, the present invention controls the pulse width of the input clock signal to an optimal value, thereby making it possible to change the pulse width of the line output pulse due to changes in the duty of the clock signal, variations in the driver circuit, temperature characteristics, etc. This has the effect of reducing the

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional line driver circuit. 1... Encoder 2... Driver 3... Output transformer 5... Pulse width detection control section 6... Pulse width control circuit 7... Pulse width detection circuit 8... Buffer Figure 1 Figure 2

Claims (2)

[Claims] (1) In a line driver circuit comprising an encoder that converts a data signal and a clock signal into a transmission line code, and a driver that outputs a signal of the transmission line code to the line via an output transformer, the line The pulse width is detected by monitoring the signal output from the
A line driver circuit comprising: a pulse width detection control section that sends a clock signal with the pulse width of the clock signal controlled to an optimum value to the encoder. (2) A line driver circuit comprising: an encoder that converts a data signal and a clock signal into a transmission line code; and a driver that outputs a signal of the transmission line code to the line via an output transformer; A buffer that monitors the signal output from the buffer, a pulse width detection circuit that detects the pulse width from the output signal of this buffer, and a pulse width detection circuit that detects the pulse width based on the signal of this pulse width detection circuit.
A line driver circuit comprising: a pulse width control circuit that controls the pulse width of the inputted clock signal to an optimum value and sends the clock signal to the encoder.