JPH04188920A - Clock generation system - Google Patents

Abstract

PURPOSE:To reduce a bit error rate accompanying the fetch of received data by varying the phase of a clock in accordance with the phase difference between transmitted data and the received data, and outputting a received frame latch clock which applies the fetch timing of each bit of the received data. CONSTITUTION:A phase difference detecting means 13 detects the phase difference between the transmitted data and the received data which are transferred between this device and a terminal equipment connected through a passive bus. A phase shifting means 15 varies the phase of the clock outputted from a reference clock preparing means 11 synchronously with each frame of the received data, according to the phase difference, and outputs the received frame latch clock. Thus, the received data can be exactly fetched even when each bit is not quickly changed due to the deterioration of the waveform of the received data.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a clock generation method for generating a clock that provides the timing for capturing data received from each terminal device via a passive lotus in an 15DNO network terminal device, and is based on a connection form of a basic interface. The purpose of this system is to automatically generate a clock that provides the timing to reliably capture data received from each terminal device, and each frame included in the received data received from the passive bus of the I5DN basic interface to the network terminal device. In a clock generation method that includes a reference clock generation means that detects the frame and generates a clock synchronized with the frame, the phase difference between the frame and the frame included in the transmission data transmitted from the network termination device to the passive bus is detected. The device includes phase difference detection means, and phase shift means that varies the phase of a clock according to the phase difference and outputs a reception frame latch clock that provides the timing for capturing each bit of received data.

[Industrial application field]

The present invention relates to a clock generation method for generating a clock that provides timing for capturing data received from each terminal device via a passive lotus in an I5DNO network terminal device.

[Conventional technology]

The implementation method of the I5DN user/wireless interface differs depending on the type of interface, but the most commonly used basic interfaces include its operation mode, connection form, physical specified point, transmission code, frame structure, frame synchronization, electrical Characteristics, conditions, etc. comply with CCITT Recommendation 1
．． 430. Among these specified items, the difference from the conventional interface is that the network termination equipment (hereinafter referred to as
It is called rNTJ. ) is connected to up to eight terminal devices (hereinafter referred to as rTE) via a full-duplex passive bus, and these TEs asynchronously transmit packets to the NT.
The point is that multiple access is possible.

That is, in order to enable such multiple access, the basic interface configures a frame with a frame period of 250 μs and a length of 48 bits, as shown in FIG. In addition, in the above frame configuration, a frame synchronization pin l-F is arranged at the first focus of each frame, and T
Data sent from E to NT (hereinafter referred to as "received data R")
It's called DJ. ) frames are always transmitted offset (delayed) by 2 bits from frames of data (hereinafter referred to as "transmission data TD") transmitted from the NT to the TE.

On the other hand, the NT receives the 12th .
The D channel bits included as 25, 36, and 47 bits are sequentially returned to the TE as echo channel bits E of the transmitted data TD (FIG. 8). When the TE is not transmitting any data to the NT, it continuously outputs a logic value "l" on the passive bus.

Furthermore, when transmitting to the NT, the TE converts the information to be sent on the D channel of the transmission frame based on predetermined focus processing,
It is transmitted as a focus sequence that does not include "l". therefore,
Other TEs that want to send data to the NT monitor the echo channel bit E included in the transmission data TD, and if the consecutive "7" or more hits are logical "1", the other TEs will not be able to send data. It determines that it has not been sent and starts sending it.

Furthermore, when multiple TEs transmit at the same time, these TEs are connected in parallel on the passive bus, so the AND of the negative logics of the bits transmitted at the same time is taken on the passive bus, and the result is sent to the NT. The echo channel bit E is returned via the echo channel bit E. Therefore, each TE compares the transmitted D channel bit and the received echo channel bit E bit by bit, and if it detects a mismatch between the two bits, it
It recognizes that there has been a collision with the transmitted frame of E, stops transmission, and performs transmission control again. In the basic interface, such a "D channel contention control method" allows only the TE that first transmitted logic "0" to the D channel to continue transmitting, thereby realizing multiple access from a plurality of TEs to the NT.

However, the length of the passive bus connecting the NT and each TE is up to 1000 meters, and
Because of the different distances, the signal is delayed on the passive lotus, and its waveform is distorted and degraded.

Therefore, the basic interface has "3" types of connection configurations, which are defined by appropriately distributing the delay time as internal delay of NT and TE and delay of passive bus line, and taking transmission loss characteristics of the line into consideration. be.

FIG. 9 is a diagram showing the connection form of the user/network interface.

In the figure, TE91. ~91. ．． is connected to NT 93 via passive bus 92. Also, as mentioned above, TE
911-91. , the D channel bits transmitted from N
TE91 as echo channel bit E via T93
．． ~911. and the phase difference of these bits is
It is determined by the above-mentioned return loop delay time (round trip delay time). As shown in FIG. 8, this delay time 5 is due to
10.4 μs (-5.2 μs ×
2) includes a fixed delay time. Furthermore, unless the echo channel bit E is received with a phase difference less than or equal to the bank period of the transmission pin rate with respect to the transmission timing of the D channel bit, the TE cannot compare the two, so the phase difference between the two bits is rl.

It must be less than or equal to bit (5.2μ5 (=250μs/48 bits)). However, this value is actually the waveform deviation of the received data RD, TE91. ~ Considering the variation of internal delay time of ~91fi and NT93, etc. 4
It is about μs. In the simple bus shown in (a), all TE91.~91, (n=1~8
) shall be located within approximately 150 meters of NT 93 along passive lot 92. In the extended bus shown in (2), the round-trip delay time must be within 2 μs, half of the minimum eye pattern width of the received frame, which is approximately 4 μs. Therefore, all TE91. ~91. (n=1~8) is passive lotus 9
The TE91. , the line length must be approximately 1,000 meters or less. At the point shown in (C), a single TE 91 is connected opposite to an NT 93, and a maximum delay of 6 bits can be tolerated between them, resulting in a round trip delay time of 10 to 42 μs.

Therefore, TE91 is about 100 along passive lotus 92.
Must be located within 0 meters.

The NT93 performs predetermined control according to the data RD received via the passive lotus configured with these connection configurations, but the phase of the received data RD is different between the NT93 and the individual T
It varies depending on the line length between the TE and the TE and the transmission timing of that TE. Therefore, the NT93 is equipped with a clock generation circuit that generates a clock to ensure the timing to capture the received data RD corresponding to each TE.

FIG. 10 is a diagram showing an example of the configuration of a conventional clock generation circuit.

In the figure, the received data RD is given to the manual RD of a received frame data detector (RFDET) 101. The output RF of the reception frame data detection section 101 is output from the reception frame latch clock generation section (TDCKGEN) I02.
connected to human-powered RF. The output TDCK of the reception frame latch clock generation section 102 outputs the reception frame latch clock TDCK. Reception frame data detection section 101 and reception frame latch clock generation section 102
The manual MCK of the master black tsuta MCK (frequency =
7.68MHz) is manually operated.

In such a lock generation circuit, the received frame data detection unit 101 detects the falling edge of the frame synchronization bit F (■ in FIG. 8) of each frame of the received data RD and outputs the signal RF (■ in FIG. 11). ). The reception frame latch clock generation unit 102 loads an initial value (~0) into a built-in frequency division counter in response to the signal RF, and further divides the master clock MCK by 40 based on this timing to generate the reception frame. Lunch clock TDCK (Frequency = 192KHzC-1, 68MHz/40 = 250
generate u s /48 bits)). The rise of the clock generated in this way provides the timing for the NT to take in the received data RD, and the width of the eye pattern at the change point of each bit of the received data RD is a maximum of 1.2 μs at the receiving end of the NT. , half value (= 0.6μS)
The frame synchronization pin F rises in advance of the falling edge of the subsequent pin L (Fig. 11 ■) (Fig. 11 ■)
It is set as follows.

[Problem M to be solved by the invention] By the way, in such a conventional clock generation circuit, when the passive bus length between the NT and the TE transmitting data is large in an extended bus or point-to-point connection configuration, In this case, the waveform at the changing point of the received data RD is degraded (Fig. 12 ■), and the master clock MCK is accompanied by jitter (Fig. 12 ■), so the logic level of the received data RD is was not determined, and the NT was unable to normally capture the received data RD (Fig. 12 (■)).

An object of the present invention is to provide a clock generation method that can automatically generate a clock that provides a timing for reliably capturing data received from each terminal device, depending on the connection form of a basic interface.

[Means to solve the problem] FIG. 1 is a block diagram of the principle of the present invention.

In the figure, the reference clock generation means 11 detects each frame included in the received data received by the network terminal device from the passive lot of the I5DN basic interface, and generates a clock synchronized with the frame.

The phase difference detection means 13 detects the phase difference between the frame and the frame included in the transmission data transmitted from the network terminal device to the passive lotus.

The phase shifter 15 is a receiving frame latch clock that varies the phase of the clock according to the phase difference and provides the timing for capturing each bit of the received data.

output.

[For production]

In the present invention, the phase difference detection means 13 detects the phase difference between transmission data and reception data exchanged with a terminal device connected via a passive lotus. The phase shifting means 15 varies the phase of the clock output from the reference clock generating means 11 in synchronization with each frame of received data according to the phase difference, and outputs a received frame latch clock.

The receive frame latch clock output in this way is
The larger the phase difference detected by the phase difference' detecting means 13, the larger the time difference is set to provide the timing to capture each bit of the received data prior to the change point of each bit included in the received data. Therefore, the network terminating device can reliably capture received data even when the waveform of the received data deteriorates and the focus does not change sharply because the passive bus length increases depending on the connection form of the basic interface. I can do it.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 is a diagram showing an embodiment of the present invention.

In the figures, parts having the same configuration and function as those shown in Fig. 10 are designated with the same reference numbers.
The explanation thereof will be omitted here.

Received data RD is provided to input RD of delay circuit (DELAYI) 21 and received frame data detection section 101 . The output RDO of the delay circuit 21 outputs received data RDO delayed by one frame. The output RF of the reception frame data detection section 101 is connected to the input RF of the reception frame latch clock generation section 102 and the clock selection signal generation section (CKSLGEN) 22. The output CKGE (same as the output TDCK shown in FIG. 10) of the reception frame rough clock generation section 102 is connected to a delay circuit (DE
LAY2) is connected to the input CKGE of 23, and its output C
KS 1. CKEX is connected to each data input of selector 24. Output signal CK of clock selection signal generation section 22
SL is given to the selection control input of the selector 24, and the output χ of the selector 24 is the reception frame launch clock TDCK.
Send out. The master clock MCK includes a reception frame data detection section 101 and a reception frame latch clock generation section 1.
02 is given to the manual MCK and clock selection signal generation section 22.

In the clock selection signal generation section 22, a timing signal STIM that provides the transmission timing of the transmission data TD is applied to the load control input of the counter 27 via the delay circuit (DELAY3) 25 and the differentiation circuit 26. The carry output of the counter 27 is connected to the enable input of the counter 27, one data input of the selector 28, and the delay circuit (D
Connected to the input of ELAY4)29. The output of delay circuit 29 is connected to the other data input of selector 28. The output X of the selector 28 is connected to one input of the AND gate 30, and its output is connected to the input input IN of the flip-flop 31. The output Q of the FRI 7 and the front 31 is connected to the selection control input of the selector 28, and outputs a clock selection signal CKSL. The signal RF is applied to the other input of the AND gate 30. A clock signal CKI having a predetermined phase and a period equal to the frame period is applied to the clock input CK of the FRI, PF, and P31. The clock input CK of the counter 27 and the differentiating circuit 26 has the following:
A master clock MCK is provided.

The feature of the present invention is that in this embodiment, a clock selection signal generation section 22 is provided which outputs a clock selection signal CKSL in accordance with the phase difference between transmission data TD and reception data RD, and a reception frame data detection section 101 and the reception frame latch clock generator 102, a delay circuit 23 outputs two reception frame data latch clocks of different phases, and a selector 24 outputs one of these clock signals in accordance with a clock selection signal CKSL. It is at the point that I have set.

Regarding the correspondence between this embodiment and the block diagram shown in FIG. corresponds to the phase difference detection means 13, and the delay circuit 23 and selector 24 correspond to the phase shift means 15.

3 to 6 are operation timing charts of this embodiment.

The operation of this embodiment will be explained below with reference to FIGS. 2 to 6.

The delay circuit 23 receives the reception frame latch clock CKGE.
A clock signal C is delayed and rises 0.6 μs in advance of the falling edge of each bit of the received data RD.
A clock signal CKEX that rises 1.6 μs in advance of KSI is output. The rising timing of these clock signals is half the width of the eye pattern at the conversion point of each bit of the received data RD in each of the simple bus and other connection forms.

In addition, the black and red selection signal generation unit 22 generates a margin (=0 .78μs (=5.2μs XO, 15))
The clock signal selection signal CK is determined according to the magnitude relationship between the actual delay time and the dark value.
Output CL. Here, when the logic value of the clock selection signal CKSL is "1", it corresponds to a connection form of a simple bus with a short passive bus length, and when the logic value is "0", it corresponds to an extension bus or a point-to-point connection form. This supports connection configurations with long passive bus lengths, such as

That is, the counter 27 is initialized according to the timing signal STIM applied to the load control input, and performs a counting operation according to the master clock MCK. In response to such a counting operation, the carry output of the counter 27 has a predetermined pulse width and is 15.49 μs from the fall of the frame synchronization bit F of the transmission data TD.
A pulse signal MM that falls with a delay ((■) in FIG. 3) is output. The delay circuit 29 delays the pulse signal MM, and delays the pulse signal MM from the fall of the frame synchronization focus F by 16 seconds.
．． A pulse signal MM2 that falls with a delay of 27 μs (■ in FIG. 3) is output. The fall timings of the pulse signals MM, , MM2 generated in this way correspond to two values set near the above-mentioned dark value. Note that these values are based on the round trip delay time (14, 4
14.19 μs (=10
9/7.68MHz) and 14.97μs (=115
/7.68MHz), and each value is set to 3 clocks (0°39μs (= 3 /7.68
MHz)), 1 bit (0.13μs (= 1 /7.68M
Hz)) and the jitter width margin (=0.78 μs) of the above-mentioned TH transmission clock signal. These two dark values are based on the phase difference between the transmit data TD and the receive data RD, the receive frame rate, and the clock clock TDCK.
This is used to provide a hysteresis characteristic to the relationship with the phase of the master clock MCK and to avoid frequent inversion of the result of determining the magnitude of the delay time due to jitter of the master clock MCK.

That is, the selector 28 selects the clock selection signal CKSL.
When is the logic "1", the pulse signal MM2 is output as the pulse signal MM (Fig. 3 (■), Fig. 4 (■)). The AND gate 30 provides the input signal IN of the flip-flop 31 with the signal RF that is provided during the period when the logic value of the pulse signal MM is "1".

The flip-flop 31 holds the logic level in accordance with the clock signal CKI which gives the start timing of the next frame following the signal RF, and outputs it as a clock signal selection CKSL (FIG. 3 (2), FIG. 4 (2)).

Further, when the clock selection signal CKSL is logic "0", the selector 28 selects the pulse signal MM and the pulse signal MM.
The output is as shown in Figure 5 ■, Figure 6), and gate 3
0 and the flip-flop 31 similarly output the clock selection signal CKSL (FIG. 5 (2), FIG. 6 (2)).

In this way, when the clock selection signal CKSL is logic "1" in the previous frame, the flip-flop 31 recognizes that the connection type is simple if the signal RF is detected before the pulse signal MM2 falls. clock selection signal CK
The logic of SL should be kept at "1" (Fig. 3 ■), and if the signal RF is not detected before the pulse signal MM2 falls, the connection form will be recognized as extended hash or point-point, and the logic of the clock selection signal CKSL will be changed. is set to "0" (Fig. 4 ■). Moreover, the flip-flop 31 is
If the clock selection signal CKSL is logic "0" in the previous frame, the signal RF is activated before the pulse signal MM falls.
is detected, the connection form is recognized as a simple lotus, and the logic of the clock selection signal CKSL is switched to "1" (Fig.
), if the signal RF is not detected before the pulse signal MM falls, the connection type is recognized as an extended bus or point-to-point, and the logic of the clock selection signal CKSL is changed to "
0" (Fig. 6 ■).

The selector 24 sets the clock selection signal CKSL to logic "0".
”, the clock signal CKEX is selected and output, and when the clock selection signal CKSL is logic “1”, the clock signal CKS I is selected and output, so the output reception frame latch clock TDCK has a simple connection configuration. In the case of bus, 0 at the falling edge of each bit of received data RD.
．． It rises 6 μs in advance, and rises 1.6 μs in advance of the falling edge of each bit of the received data RD when the connection type is extended hash or point-to-point.

Therefore, even if the waveform at the change point of the received data RD is degraded due to the long passive bus length between the TE and the NT, a receive frame latch clock is generated that provides reliable timing for capturing the received data RD. be able to.

In this embodiment, during the transmission of the TE located at the farthest point from the NT (hereinafter referred to as the "farthest TEJ"), the TE located at the closest point to the NT (hereinafter referred to as the "recent TEJ") is transmitted.
It's called E. ) also start transmitting, the NT is given received data RD which is a combination of the transmitted data of these TEs. Each focus of this received data RD is shown in FIG. 7(a).
As shown by diagonal lines in , the bits transmitted from both TEs over a period of 4 μs are combined and may become uncertain. The signal RF output at this time is normally (Fig. 7 (
a) 4 μs earlier than ■) (Figure 7 (a) ■)
To be output to the receive frame latch clock TD
CK is output with one bit missing (Fig. 7 (a) ■)
. Therefore, in such a case, similarly to the conventional configuration, the received frame latch clock 1. Therefore, it is necessary to insert a 1-bit pulse into TDCK to avoid frame synchronization.

In addition, when the farthest TE and the most recent TE are both transmitting (collision state) and only the most recent TE finishes transmitting, the falling timing of the frame synchronization bit F of the frame transmitted from the farthest TE after the end of transmission (Figure 7 (b) ■) is the falling timing during transmission collision (Go to Figure 7) ■)
TDCK is delayed by 4 μs, so there is a 1-bit surplus pulse (Fig. 7(b)
) is added. Therefore, in such a case, similarly to the conventional configuration, the receive frame latch clock TDC
It is necessary to mask and remove this surplus bit from K to avoid frame synchronization.

[Effect of the Invention] As described above, according to the present invention, the larger the phase difference between the transmission data and the reception data exchanged between the network termination device and the terminal device via the passive bus, the more the reception data becomes Up to half the maximum width of the eye pattern at the point of change of each bit,
It is possible to generate a reception frame latch crotter that takes in the received data with a large time difference in advance of the conversion point and gives timing.

Therefore, in the network termination device, it is possible to reduce the bit error rate associated with the acquisition of received data against waveform deterioration caused by the length of the passive bus depending on the connection form of the basic interface.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the principle of the present invention, Fig. 2 is a diagram showing an embodiment of the present invention, Fig. 3 is an operation timing chart (1) of this embodiment, and Fig. 4 is an operation timing of this embodiment. Chart (2), 5th
The figure shows the operation timing chart (3) of this embodiment, FIG. 6 shows the operation timing chart (4) of this embodiment, FIG. 7 shows the operation timing chart (5) of this embodiment, and FIG. 8 shows the basic interface. FIG. 9 is a diagram showing the connection form of the user/network interface. FIG. 10 is a diagram showing an example of the configuration of a conventional clock generation circuit. FIG. 11 is an operation timing chart of the conventional configuration. 1st
FIG. 2 is a diagram illustrating problems with the conventional configuration. In the figure, 11 is a reference clock generation means, 13 is a phase difference detection means, 15 is a phase shift means, 21 is a delay circuit (DELAYI), 22 is a cross shift selection signal generation section (CKSLGEN), 2
3 is a delay circuit (DELAY2), 24.28 is a selector, 25 is a delay circuit (DELAY3), 26 is a differentiation circuit, 27 is a counter, 29 is a delay circuit (DELAY4), 30 is an AND gate, 31 is a flip-flop, 911 ~91. is a terminal equipment (TE), 92 is a passive bus, 93 is a network terminal equipment (NT), 101 is a received frame data detector (RFDET), 1
02 is a reception frame latch block generator (TDCKG)
EN). Principle block diagram of the present invention Figure 1 (a) Operation timing chart of this embodiment (5) Figure 7
Figure (al. Simple bus [available]) Extension bus (C1 point, point user, rope interface connection form shown in Figure 9)
Figure 10 shows an example of the configuration of a conventional clock generation circuit.
Figure ■ Operation timing chart of the conventional configuration Figure ti Diagram explaining the problems of the conventional configuration Figure 12

Claims (1)

[Claims] (1) A clock generation method that includes a reference clock generation means (11) that detects each frame included in the received data received by the network termination device from the passive bus of the ISDN basic interface and generates a clock synchronized with the frame. a phase difference detection means (13) for detecting a phase difference between the frame and a frame included in transmission data transmitted from the network termination device to the passive bus; A clock generation system characterized by comprising: phase shifting means (15) for outputting a receive frame latch clock that is variable and provides a timing for capturing each bit of the received data.