JPH0418762A - Insulated gate field-effect transistor - Google Patents
Insulated gate field-effect transistorInfo
- Publication number
- JPH0418762A JPH0418762A JP2121326A JP12132690A JPH0418762A JP H0418762 A JPH0418762 A JP H0418762A JP 2121326 A JP2121326 A JP 2121326A JP 12132690 A JP12132690 A JP 12132690A JP H0418762 A JPH0418762 A JP H0418762A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- drain
- effect transistor
- field effect
- insulated gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 46
- 239000012535 impurity Substances 0.000 claims abstract description 60
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 20
- 238000009413 insulation Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 3
- 238000004904 shortening Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は絶縁ゲート形電界効果トランジスタに係り、特
に高周波高出力用絶縁ゲート形電界効果１〜ランシスタ
の高周波高出力特性の改善技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulated gate field effect transistor, and particularly to a technique for improving the high frequency and high output characteristics of an insulated gate field effect transistor 1 to a Lancistor for high frequency and high output.
ゲートをマスクとする自己整合形の絶縁ゲート形電界効
果トランジスタの製造方法については特公昭４９１６５
１４ ｒ絶縁ゲート型電界効果トランジスタの製法」
において論じられている。この種の電界効果トランジス
タの周波数特性を改善する方法としては、ゲー１−の・
長さを極めて短くして、短いチャンネルを形成する技術
があり、第２図のような横形ＭＯ８ＦＩＥＴ（金属酸化
膜半導体電界効果トランジスタ）が知られている。A method for manufacturing a self-aligned insulated gate field effect transistor using the gate as a mask is disclosed in Japanese Patent Publication No. 49165.
14. Manufacturing method of insulated gate field effect transistor”
It is discussed in As a method to improve the frequency characteristics of this type of field effect transistor,
There is a technique for forming a short channel by extremely shortening the length, and a lateral MO8FIET (metal oxide semiconductor field effect transistor) as shown in FIG. 2 is known.
この種のＭＯＳＦＥＴでは、半導体表面に極めて短いゲ
ートを形成する技術が必要であり、高度な微細加工技術
が必要となっている。特にソース層と１〜レイン層の不
純物濃度が異なる場合、ゲートの中央部を境にして異な
る不純物濃度の心入を行う必要がある。その場合、微細
化されたゲー１−の中央にそれぞれ異なる不純物導入マ
スクの位置合わせを行う高度な微細加工技術が必要とな
り、製造歩留まりが低下する問題がある。更に、極めて
短いチャンネルを形成する結果、低いドレイン電圧を印
加するだけで、チャンネルにバンチスルー電流がながれ
、トランジスタの動作が停止する問題がある。また、特
に高出力を目的として高耐圧化する場合、第２図のよう
に、ゲー１−１とドレインコンタクト層５の間に低濃度
ドレイン層３を設けた、いわゆるオフセラ１〜ゲート構
造をとり、低濃度ドレイン層３によって高いドレイン耐
圧を確保する技術が実施されている。その場合、十分な
ドレイン耐圧を確保すれば、ドレイン、ソース間のオン
抵抗が高くなるという問題があった。This type of MOSFET requires a technology to form an extremely short gate on the semiconductor surface, and requires advanced microfabrication technology. In particular, when the impurity concentrations of the source layer and the first to rain layers are different, it is necessary to adjust the impurity concentrations to be different from each other at the center of the gate. In that case, a sophisticated microfabrication technique is required to align different impurity introduction masks to the center of the miniaturized gate 1-, which poses a problem of lowering manufacturing yield. Furthermore, as a result of forming an extremely short channel, there is a problem in that even when a low drain voltage is applied, a bunch-through current flows through the channel, stopping the operation of the transistor. In addition, when increasing the breakdown voltage especially for the purpose of high output, a so-called off-cellar 1-gate structure is used, in which a low concentration drain layer 3 is provided between the gate 1-1 and the drain contact layer 5, as shown in FIG. , a technique has been implemented to ensure high drain breakdown voltage using the low concentration drain layer 3. In that case, there is a problem in that if a sufficient drain breakdown voltage is ensured, the on-resistance between the drain and source becomes high.
本発明の目的は、ゲートをマスクとする自己整合形絶縁
ゲート形電界効果トランジスタにおいて、極めて短いゲ
ートを形成せずども短いチャンネルを有するとともに、
パンチスルーが発生しない高周波電界効果トランジスタ
を提供することである。An object of the present invention is to provide a self-aligned insulated gate field effect transistor using a gate as a mask, which has a short channel without forming an extremely short gate.
An object of the present invention is to provide a high frequency field effect transistor in which punch-through does not occur.
更に、高いドレイン耐圧を有するとともに、ドレイン最
大電流を大きくし、オン抵抗の増大を抑えた高周波高出
力電界効果トランジスタを提供することである。Furthermore, it is an object of the present invention to provide a high frequency, high power field effect transistor which has a high drain breakdown voltage, a large drain maximum current, and suppresses an increase in on-resistance.
」１記課題を解決するためには、第１の低濃度ドレイン
層の他にゲートをマスクとする第２の低濃度ドレイン層
を形成し、該第２の低濃度ドレイン層の不純物濃度を第
１の低濃度ドレイン層より低くし、更に、熱拡散によっ
て該第２のドレイン層の深さを大きくして、ゲートのド
への横方向の拡散を制御ことによって達成される。In order to solve problem 1, a second lightly doped drain layer is formed using the gate as a mask in addition to the first lightly doped drain layer, and the impurity concentration of the second lightly doped drain layer is set to a second level. This is achieved by increasing the depth of the second drain layer by thermal diffusion to control the lateral diffusion to the gate.
−ｈ記第２のドレイン層の不純物濃度を第１のドレイン
層の不純物濃度より低くすることによりドレイン耐圧が
高くなる。また、第２のドレイン層の深さを大きくして
ゲートの下への横方向拡散を制御することにより短いチ
ャンネルが形成される。-h By making the impurity concentration of the second drain layer lower than the impurity concentration of the first drain layer, the drain breakdown voltage is increased. Also, a short channel is formed by increasing the depth of the second drain layer to control lateral diffusion below the gate.
第１図は、本発明の第１の実施例を示す。ここに、１は
ゲート、２はソース層、３は第１の低濃度ドレイン層、
４は本発明における第２の低濃度ドレイン層、５はドレ
インコンタクト層であり、ドレイン層４はドレイン層３
より不純物濃度を低くするとともに、第１の低濃度ドレ
イン層３の一部を含む領域に、ゲートをマスクとして深
い拡散層を形成するものである。その結果、横方向の拡
散を制御することにより、ゲート１の下に短いチャンネ
ルを形成することができる。従来技術においては、第２
図に示すように、１くレイン層３がゲート１とオーバー
ラツプして形成するゲート・ドレイン間静電容量Ｃｇｄ
がゲートとソースおよび半導体基板の間で形成されるゲ
ーｌ〜静電容量Ｃｇｓに比較して無視できなかった。そ
のためドレイン層：３をできるだけ浅く形成することに
より、ゲート１−どのオーバーラツプ部分をできるだけ
少なくしＣＫ、ｃ３の低減をはかってきた。そのために
、ゲー１−をマスクとしたイオン打ち込みを使用し、ド
レイン層への不純物導入後の熱的製造工程をできるだけ
制限してきた。その結果、ドレイン層の深さは０ 、３
μ■１ 以下、あるいはゲート長の５分の１を越えるこ
とが制限された。例えば０．５μｍのチャンネルを形成
するためには、１μｍのゲー１〜を形成し、ソース層の
深さを０．２μｍ以下、ドレイン層の深さを０ 、３μ
ｍ以下とする等の制限が必要であった。その場合、不純
物濃度の異なるソース層と８１２１２層を形成するため
には、１μｎ１ゲートの中央に、それぞれ異なるマスク
の位置合わせをする必要があり、高度な微細加工技術が
必要であるという第２の問題があった３、しかし、本発
明においては極めて短いゲーＩ・を形成することなく、
例えば２μｍゲートとし、ドレイン層４の拡散深さを１
−１３μｍとすることによって０．５μＩｎのチャンネ
ルを形成するものである９また、第１図に示すように、
第２のドレイン層４は第１のドレイン層３に比較して低
濃度である。このため第２のドレイン層４の表面側近に
は空乏層が形成されやすい。その結果、第２のドレイン
層４とゲート１とのオーバーラツプ部分の静電容量は前
記従来技術で形成した場合より小さくなる。そのため、
本発明によれば、第２のドレイン層４とゲート１のオー
バーラツプ部分を大きくしても不要なゲート・ドレイン
間静電容量Ｃｇｄが増大しないという効果を有する。す
なわち、第２のドレイン層４とゲー１−１とのオーバー
ラツプ部分の長さが０．３μｍ、あるいはゲート長の５
分の１を越えてもＭ、０８ＦＥＴの特性が劣化しないと
いう効果を有している。更に、ドレイン層４の不純物濃
度が低いために、短いチャンネルのバンチスルーが発生
しない効果がある。更にドレイン電圧が高くなると、ド
レイン層４の空乏層は更に広くなり、その後ドレイン層
３が空乏層となるのでドレイン層４がない場合に比べて
高いドレイン耐圧を達成できる。一方、オン状態におい
てはドレイン層４の一部およびドレイン層３はピンチ抵
抗として作用し、電流が大きくなるに従ってピンチオン
する。FIG. 1 shows a first embodiment of the invention. Here, 1 is a gate, 2 is a source layer, 3 is a first low concentration drain layer,
4 is the second low concentration drain layer in the present invention, 5 is the drain contact layer, and the drain layer 4 is the drain layer 3.
In addition to lowering the impurity concentration, a deep diffusion layer is formed in a region including a part of the first low concentration drain layer 3 using the gate as a mask. As a result, a short channel can be formed under the gate 1 by controlling the lateral diffusion. In the conventional technology, the second
As shown in the figure, the gate-drain capacitance Cgd formed when the first drain layer 3 overlaps with the gate 1
was not negligible compared to the capacitance Cgs formed between the gate, source, and semiconductor substrate. Therefore, by forming the drain layer 3 as shallowly as possible, the overlap between the gate 1 and the gate 1 has been minimized, thereby reducing CK and c3. For this purpose, ion implantation using Ga1 as a mask has been used to limit the thermal manufacturing process after introducing impurities into the drain layer as much as possible. As a result, the depth of the drain layer is 0,3
It was restricted to be less than μ■1 or to exceed one-fifth of the gate length. For example, in order to form a channel of 0.5 μm, a gate of 1 μm is formed, the depth of the source layer is 0.2 μm or less, and the depth of the drain layer is 0.3 μm.
It was necessary to set a limit such as less than m. In that case, in order to form a source layer and an 81212 layer with different impurity concentrations, it is necessary to align different masks in the center of a 1μn1 gate, and the second problem is that advanced microfabrication technology is required. However, in the present invention, without forming an extremely short game I,
For example, the gate is 2 μm, and the diffusion depth of the drain layer 4 is 1 μm.
-13 μm, a channel of 0.5 μIn is formed.9 Also, as shown in FIG.
The second drain layer 4 has a lower concentration than the first drain layer 3. Therefore, a depletion layer is likely to be formed near the surface of the second drain layer 4. As a result, the capacitance of the overlapping portion of the second drain layer 4 and the gate 1 becomes smaller than that when formed using the conventional technique. Therefore,
According to the present invention, there is an effect that even if the overlap portion between the second drain layer 4 and the gate 1 is increased, the unnecessary gate-drain capacitance Cgd does not increase. That is, the length of the overlap portion between the second drain layer 4 and the gate 1-1 is 0.3 μm, or 5 μm of the gate length.
This has the effect that the characteristics of the M,08FET do not deteriorate even if the amount exceeds 1/2. Furthermore, since the impurity concentration of the drain layer 4 is low, there is an effect that bunch-through of short channels does not occur. When the drain voltage further increases, the depletion layer of the drain layer 4 becomes wider, and then the drain layer 3 becomes a depletion layer, so that a higher drain withstand voltage can be achieved than in the case where the drain layer 4 is not provided. On the other hand, in the on state, a part of the drain layer 4 and the drain layer 3 act as a pinch resistance, and pinch-on occurs as the current increases.
その場合、ピンチオフはドレイン層３の１くレインコン
タクト層５側より始まってドレイン層４に達する１、従
って、ピンチオフに伴うドレイン最大電流はドレイン層
４より不純物濃度が高いドレイン層２３の抵抗で決定す
ることになる。また、ドレイン層４は低いドレイン電圧
、すなわちオン電圧でも空乏層となるので、ドレイン層
４の長さ奈短くすることにより、オン抵抗に寄与する割
合を小さくすることができる。以上のように、本発明に
よれば、オン抵抗を大きくすることなく、高いドレイン
耐圧を有し、ドレイン最大電流が大きく、かつ短いチャ
ンネルを有するとともにパンチスルーのない絶縁ゲート
形電界効果トランジスタを形成することができる。In that case, the pinch-off starts from the drain contact layer 5 side of the drain layer 3 and reaches the drain layer 4. Therefore, the maximum drain current accompanying the pinch-off is determined by the resistance of the drain layer 23, which has a higher impurity concentration than the drain layer 4. I will do it. In addition, since the drain layer 4 becomes a depletion layer even at a low drain voltage, that is, an on-voltage, by shortening the length of the drain layer 4, the proportion contributing to the on-resistance can be reduced. As described above, according to the present invention, an insulated gate field effect transistor is formed which has a high drain breakdown voltage, a large maximum drain current, a short channel, and no punch-through without increasing the on-resistance. can do.
第３図は、本発明の第２の実施例を示す。本実施例は第
１の実施例（第１図）の変形であり、ドレイン層８をゲ
ー １・端より離して形成し、たものでま）る、これに
よって、クー１〜端部に集中する電界強度を緩和するこ
とができ、より高いドレイン耐圧を達成することができ
る。FIG. 3 shows a second embodiment of the invention. This embodiment is a modification of the first embodiment (FIG. 1), in which the drain layer 8 is formed away from the edge of the drain layer 8, thereby concentrating on the edge of the drain layer 8. This makes it possible to reduce the electric field strength and achieve higher drain breakdown voltage.
第４図は、本発明の第３の実施例を示す。本実施例は、
ドＩツイン層３をドレインコンタクト層５より浅くし、
ドレイン層３と同じ不純物濃度で、同じ深さのソース層
２１をゲー１−をマスクとして形成し、ソース層２はゲ
ート端より離して形成し、更に、ドレインコンタ９８層
５の一部あるいは全部を囲む第３のドレイン層６を形成
し、その不純物濃度をドレインコンタク１−層５および
ドレイン層３の不純物濃度より小さくし、その深さをド
レインコンタクＩ・層５より大きくしたものである。FIG. 4 shows a third embodiment of the invention. In this example,
The drain I twin layer 3 is made shallower than the drain contact layer 5,
A source layer 21 with the same impurity concentration and the same depth as the drain layer 3 is formed using the gate 1- as a mask, the source layer 2 is formed away from the gate end, and a part or all of the drain contour 98 layer 5 is formed. A third drain layer 6 is formed surrounding the drain layer 6, and its impurity concentration is lower than that of the drain contact layer 1-layer 5 and drain layer 3, and its depth is larger than that of the drain contact layer 1-layer 5 and drain layer 3.
本実施例により、ゲートとソース層の重なりによる入力
静電容量が低減される。また、ドレイン層６の空乏層の
広がりが大きくなるので、ドレイン層の中で半導体基板
に対する電位が最も高くなるドレインコンタクト領域５
からドレイン層６を通って半導体基板に流れる高周波電
流の損失を小さくすることができる。更に、ドレイン層
６は１くレイン層・１と同じ不純物濃度で、同じ深さに
することができ、同時に形成することができるので、製
造上程を簡Ｉ４ｉ、化することができる。This embodiment reduces the input capacitance due to the overlap between the gate and source layers. In addition, since the depletion layer of the drain layer 6 expands, the drain contact region 5 has the highest potential with respect to the semiconductor substrate in the drain layer.
The loss of the high frequency current flowing from the drain layer 6 to the semiconductor substrate can be reduced. Further, since the drain layer 6 can have the same impurity concentration and the same depth as the drain layer 1, and can be formed simultaneously, the manufacturing process can be simplified.
第５図は、本発明の第４の実施例を示す。ここに、３１
はドレイン層として作用するものであり、従来は第２図
のドレイン層３のようにゲートをマスクどして形成され
たが、本発明では少なくともソースの一部およびゲート
の下部にわたる領域にも形成される。従って、本実施例
ではデイプリージョンモード動作となる。更に１本実施
例では、Ｐ形不純物層４１をゲート１−をマスクとして
ドレイン耐圧界
する。ｉｔ６． Ｐ形不純物層はイオン打ち込みと熱拡
散によって少なくともソース層より深く拡散する。FIG. 5 shows a fourth embodiment of the invention. Here, 31
acts as a drain layer, and conventionally was formed by masking the gate as shown in the drain layer 3 in FIG. be done. Therefore, this embodiment operates in depletion mode. Furthermore, in this embodiment, the P-type impurity layer 41 is subjected to a drain breakdown voltage field using the gate 1- as a mask. it6. The P-type impurity layer is diffused at least deeper than the source layer by ion implantation and thermal diffusion.
また、該Ｐ形不純物層の表面不純物濃度は上記ドレイン
層３１の■）形不純物濃度より小さく設定するので、該
ｐ形不純物層が形成された部分のｒｌ形不純物濃度は極
めて低くなる。その結果、該Ｐ形不純物層のゲートの下
部における横方向の拡散を制御することにより、ゲート
１の１；に短いチャンネルを形成することができる。更
に、ゲ・−１へ１に接するドレイン層３１の不純物濃度
を極めて低くすることができるので、低い１くレイン電
圧で空乏層となり、高いドレイン電圧を印加してもチャ
ンネルのパンチスルーは発生しない特長がある。Furthermore, since the surface impurity concentration of the P-type impurity layer is set to be lower than the (1) type impurity concentration of the drain layer 31, the rl-type impurity concentration in the portion where the p-type impurity layer is formed becomes extremely low. As a result, a short channel can be formed in the gate 1 by controlling the lateral diffusion of the P-type impurity layer under the gate. Furthermore, since the impurity concentration of the drain layer 31 in contact with Ge-1 can be made extremely low, it becomes a depletion layer at a low drain voltage, and channel punch-through does not occur even when a high drain voltage is applied. It has its features.
第６図は、本発明の第５の実施例を示す。本実施例は、
第４の実施例（第５図）のゲート］の下部、少なくとも
チャンネルが形成される領域にゲートをマスクとして第
２のｐ形不純物層７を設けたものである。該ｐ形不純物
層の不純物濃度はゲートの下部のチャンネル形成層のｎ
形不純物濃度をｐ形に転換するに十分なものであり、し
きい電圧を調整するものである。その結果、本実施例に
おいては、エンハンスメントモード動作とすることがで
きる。本実施例は従来のＤＳＡ（二重拡散）形電界効果
トランジスタとは、半導体基板の不純物がｐ形である点
でＤＳＡ形とは構造的に、またチャンネルが形成される
領域において異なるものである。FIG. 6 shows a fifth embodiment of the invention. In this example,
A second p-type impurity layer 7 is provided below the gate of the fourth embodiment (FIG. 5), at least in the region where the channel is formed, using the gate as a mask. The impurity concentration of the p-type impurity layer is equal to n of the channel forming layer below the gate.
This is sufficient to convert the type impurity concentration to p-type, and adjusts the threshold voltage. As a result, this embodiment can operate in enhancement mode. This embodiment differs from the conventional DSA (double diffused) type field effect transistor in that the impurity of the semiconductor substrate is p-type, and is structurally different from the DSA type in the region where the channel is formed. .
第７図は、本発明の第６の実施例を示す。本実施例は、
第１の実施例においてソース層２の一部およびゲー１−
の下部にわたって、ゲートをマスクとし、てＰ形イく鈍
物層７を形成したものである。これによって、ドレイン
耐圧によって決まる半導体基板の不純物濃度とは独立に
チャンネルのしきい電圧を調整することができる。本実
施例は、ＤＳＡ（二重拡散自己整合）形電界効果トラン
ジスタどは、半導体も（板の不純物がｐ形である点で、
またチャンネルが形成される領域において異なるもので
ある。FIG. 7 shows a sixth embodiment of the invention. In this example,
In the first embodiment, part of the source layer 2 and the gate 1-
A P-type blunt layer 7 is formed over the lower part of the gate using the gate as a mask. Thereby, the threshold voltage of the channel can be adjusted independently of the impurity concentration of the semiconductor substrate determined by the drain breakdown voltage. In this embodiment, a DSA (double diffused self-aligned) field effect transistor is similar to a semiconductor (in that the impurity of the plate is p-type).
They also differ in the region where the channel is formed.
第８図は、本発明の第７の実施例を示す。本実施例は、
特にｐ形高濃度基板の上に形成されたｐ形基板を基体と
して形成されるもので、ソース層２の中に、あるいはソ
ース層２の一部を含んでソース層の近傍に、ｐ形高濃度
半導体基板に達する、あるいは近接するソーススルー溝
９を形成し、該ソーススルー溝にあわせてｐ形コンタク
ト層１０を形成し、たちのである。その結果、半導体基
板表面のソース端子をなくし、該裏面によりソース接地
を行うことができ、ソース共通インダクタンスを低減す
ることができる。３更に、本実施例においては、ドレイ
ン層３へのコンタク［へ溝８を形成し、該コンタタト溝
にあわせてドレインコンタク１−層５あるいはドレイン
層６を形成したものである。FIG. 8 shows a seventh embodiment of the invention. In this example,
In particular, it is formed using a p-type substrate formed on a p-type high concentration substrate as a base. A source through groove 9 reaching or close to the doped semiconductor substrate is formed, and a p-type contact layer 10 is formed in line with the source through groove. As a result, the source terminal on the front surface of the semiconductor substrate can be eliminated, the source can be grounded from the back surface, and the common source inductance can be reduced. 3. Furthermore, in this embodiment, a groove 8 is formed in the contact groove to the drain layer 3, and a drain contact layer 5 or a drain layer 6 is formed in accordance with the contact groove.
その結果、ドレインコンタクト領域の全面積を変えずに
、あるいは大きくして、平面積は小さくすることができ
る。そのため、ドレイン層の中で最も電位が高く、かつ
半導体基板との接合静電容量が最も大きくなるドレイン
コンタクＩ−領域の直下において、ドレイン層より半導
体基板に流れる高周波電流を小さくすることができる。As a result, the planar area can be reduced while the total area of the drain contact region remains unchanged or is increased. Therefore, directly under the drain contact I- region, which has the highest potential among the drain layers and has the largest junction capacitance with the semiconductor substrate, it is possible to reduce the high-frequency current flowing into the semiconductor substrate rather than the drain layer.
更に、本実施例においては、ドレインコンタクト層５あ
るいはドレイン層の一部あるいは全部にわたって絶縁層
あるいは半絶縁層１１を、高エネルギーイオン打ち込み
等によって形成したものである。これによって、ドレイ
ン層およびドレインコンタクト層５より半導体基板に流
れる高周波電流を極めて小さくすることができる。Furthermore, in this embodiment, an insulating layer or semi-insulating layer 11 is formed over part or all of the drain contact layer 5 or the drain layer by high-energy ion implantation or the like. Thereby, the high frequency current flowing from the drain layer and drain contact layer 5 to the semiconductor substrate can be made extremely small.
以上、ｎチャンネル絶縁ゲート形電界効果トランジスタ
について説明したが、ｐチャンネル絶縁ゲー１〜形電界
効果トランジスタの場合は、ｎ形不純物層をｐ形不純物
層、ｐ形不純物層をｎ形不純物層とすることによって本
発明に含まれるものである。The above has explained the n-channel insulated gate field effect transistor, but in the case of the p-channel insulated gate field effect transistor, the n-type impurity layer is the p-type impurity layer, and the p-type impurity layer is the n-type impurity layer. Therefore, it is included in the present invention.
以４−のように、本発明を自己整合形絶縁ゲート形電界
効果トランジスタに適用すれは、極めて短いゲートを形
成せずとも、極めて短いチャンネルを有するとともに、
高周波動作が可能であり、かつ、高いドレイン電圧でも
パンチスルーが発生しない絶縁グー１−形電界効果Ｉ〜
ランジスタを提供することができる。また、極めて短い
ゲートを形成する必要がないため、製造上の歩留まりを
高くすることかできる。更に、本発明によれば、ドレイ
ン層から半導体基板に流れる高周波電流の損失を小さく
することができ、ドレイン効率を高くすることができる
。As described in 4- below, when the present invention is applied to a self-aligned insulated gate field effect transistor, it has an extremely short channel without forming an extremely short gate, and
Insulation type 1-type field effect I that enables high frequency operation and does not cause punch-through even at high drain voltages
transistors can be provided. Furthermore, since it is not necessary to form an extremely short gate, manufacturing yield can be increased. Further, according to the present invention, loss of high frequency current flowing from the drain layer to the semiconductor substrate can be reduced, and drain efficiency can be increased.
第１図は本発明の第１の実施例、第２図は従来の自己整
合型絶縁ゲート型電界効果トランジスタの構造、第３図
は本発明の第２の実施例、第４図は本発明の第３の実施
例、第５図は本発明の第４の実施例、第６図は本発明の
第５の実施例、第７図は本発明の第６の実施例、第８図
は本発明の第７の実施例を示す図である。FIG. 1 shows a first embodiment of the present invention, FIG. 2 shows the structure of a conventional self-aligned insulated gate field effect transistor, FIG. 3 shows a second embodiment of the present invention, and FIG. 4 shows a structure of a conventional self-aligned insulated gate field effect transistor. FIG. 5 is a fourth embodiment of the present invention, FIG. 6 is a fifth embodiment of the present invention, FIG. 7 is a sixth embodiment of the present invention, and FIG. 8 is a third embodiment of the present invention. It is a figure which shows the 7th Example of this invention.
Claims (1)
ソース層とし、ｎ形低濃度不純物層を第１のドレイン層
とし、第１のドレイン層と少なくとも一部が重なるよう
にｎ形高濃度不純物層を形成し、これをドレインコンタ
クト層とするｎ形絶縁ゲート形電界効果トランジスタに
おいて、第１のドレイン層の一部を含む領域にゲートを
マスクとしてｎ形低濃度不純物層を形成し、これを第２
のドレイン層とし、そのゲート下部への横方向拡散深さ
を第１のドレイン層の拡散深さより大きくしたことを特
徴とする絶縁ゲート形電界効果トランジスタ。 ２、特許請求の範囲第１項記載の絶縁ゲート形電界効果
トランジスタにおいて、上記第２のドレイン層の不純物
濃度を第１のドレイン層の不純物濃度より小さくしたこ
とを特徴とする特許請求の範囲第１項記載の絶縁ゲート
形電界効果トランジスタ。 ３、特許請求の範囲第１項、および第２項記載の絶縁ゲ
ート形電界効果トランジスタにおいて、上記第１のドレ
イン層をゲートをマスクとして自己整合によって形成し
たことを特徴とする特許請求の範囲第１項、および第２
項記載の絶縁ゲート形電界効果トランジスタ。 ４、特許請求の範囲第１項、第２項、および第３項記載
の絶縁ゲート形電界効果トランジスタにおいて、上記第
２の低濃度ドレイン層のゲート下部への横方向拡散深さ
を０．３μｍあるいはゲート長の５分の１よりも大きく
したことを特徴とする特許請求の範囲第１項、第２項、
および第３項記載の絶縁ゲート形電界効果トランジスタ
。 ５、ｐ形半導体基板に形成されたｎ形不純物層をソース
層とし、少なくとも該ソース層の一部とゲートの下を含
んでドレイン側に伸びるｎ形低濃度不純物層をドレイン
層とし、該ドレイン層の一部にｎ形高濃度不純物層を形
成し、これをドレインコンタクト層とするｎ形絶縁ゲー
ト形電界効果トランジスタにおいて、該ドレイン層のド
レイン側の一部にゲートをマスクとしてｐ形不純物層を
形成し、その表面不純物濃度を該ドレイン層の表面不純
物濃度より小さくしたことを特徴とする絶縁ゲート形電
界効果トランジスタ。 ６、特許請求の範囲第５項記載の絶縁ゲート形電界効果
トランジスタにおいて、上記ｐ形不純物層の深さを該ソ
ース層の深さより大きくしたことを特徴とする特許請求
の範囲第５項記載の絶縁ゲート形電界効果トランジスタ
。 ７、特許請求の範囲第１項、第２項、第３項、第４項、
第５項、および第６項記載の絶縁ゲート形電界効果トラ
ンジスタにおいて、上記ドレインコンタクト層の一部あ
るいは全部を囲む第３のドレイン層を形成し、その不純
物濃度を該ドレインコンタクト層の不純物濃度より小さ
くし、その深さを該ドレインコンタクト層より大きくし
たことを特徴とする特許請求の範囲第１項、第２項、第
３項、第４項、第５項、および第６項記載の絶縁ゲート
形電界効果トランジスタ。 ８、特許請求の範囲第１項、第２項、第３項、および第
４項記載の絶縁ゲート形電界効果トランジスタに関する
特許請求の範囲第７項記載の絶縁ゲート形電界効果トラ
ンジスタにおいて、上記第３のドレイン層を上記第２の
ドレイン層と同じ不純物濃度および同じ深さに形成した
ことを特徴とする特許請求の範囲第７項記載の絶縁ゲー
ト形電界効果トランジスタ。 ９、特許請求の範囲第１項、第２項、第３項、第４項、
第５項、第６項、第７項、および第８項記載の絶縁ゲー
ト形電界効果トランジスタにおいて、該ソース層の一部
およびゲートの下部にわたって、ゲートをマスクとして
ｐ形不純物層を形成し、これを該ソース層より深くした
ことを特徴とする特許請求の範囲第１項、第２項、第３
項、第４項、第５項、第６項、第７項、および第８項記
載の絶縁ゲート形電界効果トランジスタ。 １０、特許請求の範囲第１項、第２項、第３項、第４項
、第５項、第６項、第７項、第８項、および第９項記載
の絶縁ゲート形電界効果トランジスタにおいて、ドレイ
ンコンタクト層のコンタクト穴にあわせてコンタクト溝
を形成し、該コンタクト溝に合わせて該ドレインコンタ
クト層、および取りだし電極を形成したことを特徴とす
る特許請求の範囲第１項、第２項、第３項、第４項、第
５項、第６項、第７項、第８項、および第９項記載の絶
縁ゲート形電界効果トランジスタ。 １１、ｐ形高濃度半導体基板の上に形成されたｐ形層を
基体として形成された特許請求の範囲第１項、第２項、
第３項、第４項、第５項、第６項、第７項、第８項、第
９項、および第１０項記載の絶縁ゲート形電界効果トラ
ンジスタにおいて、該ソース層の近傍、あるいは該ソー
ス層の一部を含む領域にわたって、該半導体基板にソー
ススルー溝を形成し、該ソーススルー溝に合わせてｐ形
コンタクト層を形成し、該コンタクト層が上記ｐ形高濃
度半導体基板に達するか、少なくとも近接するようにし
たことを特徴とする特許請求の範囲第１項、第２項、第
３項、第４項、第５項、第６項、第７項、第８項、第９
項、および第１０項記載の絶縁ゲート形電界効果トラン
ジスタ。 １２、特許請求の範囲第１項、第２項、第３項、第４項
、第５項、第６項、第７項、第８項、第９項、第１０項
、および第１１項記載の絶縁ゲート形電界効果トランジ
スタにおいて、少なくともドレインコンタクト層を含む
ドレイン層の下部の半導体基板に絶縁層あるいは半絶縁
層を形成したことを特徴とする特許請求の範囲第１項、
第２項、第３項、第４項、第５項、第６項、第７項、第
８項、第９項、第１０項、および第１１項記載の絶縁ゲ
ート形電界効果トランジスタ。 １３、特許請求の範囲第１項、第２項、第３項、第４項
、第５項、第６項、第７項、第８項、第９項、第１０項
、第１１項、および第１２項記載のｎ形絶縁ゲート形電
界効果トランジスタのｎ形不純物をｐ形不純物、ｐ形不
純物をｎ形不純物とした絶縁ゲート形電界効果トランジ
スタ。[Claims] 1. An n-type high-concentration impurity layer formed on a p-type semiconductor substrate is used as a source layer, an n-type low-concentration impurity layer is used as a first drain layer, and at least a portion of the n-type low concentration impurity layer is formed on a p-type semiconductor substrate. In an n-type insulated gate field effect transistor in which an n-type high-concentration impurity layer is formed so as to overlap and this is used as a drain contact layer, an n-type low-concentration impurity layer is formed in a region including a part of the first drain layer using the gate as a mask. Form a concentrated impurity layer and apply it to the second layer.
1. An insulated gate field effect transistor, characterized in that the lateral diffusion depth to the lower part of the gate is greater than the diffusion depth of the first drain layer. 2. In the insulated gate field effect transistor according to claim 1, the impurity concentration of the second drain layer is lower than the impurity concentration of the first drain layer. The insulated gate field effect transistor according to item 1. 3. In the insulated gate field effect transistor according to claims 1 and 2, the first drain layer is formed by self-alignment using the gate as a mask. 1st term, and 2nd term
The insulated gate field effect transistor described in . 4. In the insulated gate field effect transistor according to claims 1, 2, and 3, the lateral diffusion depth of the second lightly doped drain layer to the lower part of the gate is 0.3 μm. Alternatively, claims 1 and 2 are characterized in that the gate length is larger than one-fifth of the gate length.
and the insulated gate field effect transistor according to item 3. 5. An n-type impurity layer formed on a p-type semiconductor substrate is used as a source layer, an n-type low concentration impurity layer extending toward the drain side including at least a part of the source layer and under the gate is used as a drain layer, and the drain In an n-type insulated gate field effect transistor in which an n-type high concentration impurity layer is formed in a part of the layer and this is used as a drain contact layer, a p-type impurity layer is formed in a part of the drain side of the drain layer using the gate as a mask. 1. An insulated gate field effect transistor comprising a drain layer having a surface impurity concentration lower than that of the drain layer. 6. The insulated gate field effect transistor according to claim 5, characterized in that the depth of the p-type impurity layer is greater than the depth of the source layer. Insulated gate field effect transistor. 7. Claims 1, 2, 3, 4,
In the insulated gate field effect transistor according to Items 5 and 6, a third drain layer is formed to surround part or all of the drain contact layer, and the impurity concentration thereof is lower than the impurity concentration of the drain contact layer. The insulation according to claims 1, 2, 3, 4, 5, and 6, characterized in that the insulation layer is made smaller and has a depth greater than that of the drain contact layer. Gate field effect transistor. 8. The insulated gate field effect transistor according to claim 7, which relates to the insulated gate field effect transistor according to claims 1, 2, 3, and 4, 8. The insulated gate field effect transistor according to claim 7, wherein the drain layer No. 3 is formed to have the same impurity concentration and the same depth as the second drain layer. 9.Claims 1, 2, 3, 4,
In the insulated gate field effect transistor according to items 5, 6, 7, and 8, a p-type impurity layer is formed over a portion of the source layer and under the gate using the gate as a mask, Claims 1, 2, and 3 are characterized in that the layer is deeper than the source layer.
8. The insulated gate field effect transistor according to item 1, item 4, item 5, item 6, item 7, and item 8. 10. Insulated gate field effect transistor according to claims 1, 2, 3, 4, 5, 6, 7, 8, and 9 Claims 1 and 2 are characterized in that a contact groove is formed in alignment with the contact hole of the drain contact layer, and the drain contact layer and lead-out electrode are formed in alignment with the contact groove. , 3, 4, 5, 6, 7, 8, and 9. 11. Claims 1 and 2, which are formed using a p-type layer formed on a p-type high concentration semiconductor substrate as a base.
In the insulated gate field effect transistor according to paragraphs 3, 4, 5, 6, 7, 8, 9, and 10, A source through groove is formed in the semiconductor substrate over a region including a part of the source layer, a p-type contact layer is formed in alignment with the source through groove, and the contact layer reaches the p-type high concentration semiconductor substrate. , Claims 1, 2, 3, 4, 5, 6, 7, 8, and 9
and the insulated gate field effect transistor according to item 10. 12. Claims 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, and 11 In the insulated gate field effect transistor described above, an insulating layer or a semi-insulating layer is formed on the semiconductor substrate below the drain layer including at least a drain contact layer.
The insulated gate field effect transistor according to items 2, 3, 4, 5, 6, 7, 8, 9, 10, and 11. 13. Claims 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and an insulated gate field effect transistor in which the n-type impurity is a p-type impurity and the p-type impurity is an n-type impurity in the n-type insulated gate field effect transistor according to item 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2121326A JPH0418762A (en) | 1990-05-14 | 1990-05-14 | Insulated gate field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2121326A JPH0418762A (en) | 1990-05-14 | 1990-05-14 | Insulated gate field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0418762A true JPH0418762A (en) | 1992-01-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2121326A Pending JPH0418762A (en) | 1990-05-14 | 1990-05-14 | Insulated gate field-effect transistor |
Country Status (1)
| Country | Link |
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| JP (1) | JPH0418762A (en) |
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| US5386134A (en) * | 1993-11-23 | 1995-01-31 | Vlsi Technology, Inc. | Asymmetric electro-static discharge transistors for increased electro-static discharge hardness |
| JPH07335834A (en) * | 1994-06-07 | 1995-12-22 | Nippon Motorola Ltd | Output driver of semiconductor integrated circuit device |
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