JPH04186983A - Wide television receiver - Google Patents

Abstract

PURPOSE:To display the video signal of an aspect ratio of 4:3 on a double speed scanning display of 16 : 9 by supplying an output signal of a real/ interpolating scanning line signal generating circuit (EDTV processor) to a time base compression memory, and executing simultaneously the double speed conversion and the aspect ratio conversion. CONSTITUTION:By a video signal inputted from an input terminal 101, a real scanning line signal R and an interpolating scanning line I are generated by an EDTV processor 102. Subsequently, it is converted to a signal of compression to 3/4, and also, a double speed scan in the horizontal direction by a compression clock and a control signal supplied from a memory control circuit 11, and thereafter, displayed on a 16:9 display 104. A read-out system control signal of the memory 103 supplies an output signal obtained by frequency-dividing a clock generated in a first PLL 106 by a write control generating circuit 107, to a second PLL 109. It is reproduced by a read-out control generating circuit 108 from a new clock generated by this 109, and a write reference signal outputted from 107.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a wide television receiver having a display with an aspect ratio of 16:9, and particularly capable of displaying a video signal having an aspect ratio of 4:3. The present invention relates to a television signal processing device for processing.

[Conventional technology]

In recent years, MU S E (Mul, tiple 5ub-
(Niquist Sampling Encoding)
Conventional N T
S C (National Te1evision
Broadcasting of video signals with an aspect ratio of 16:9, which is different from the System Communications system, is about to begin.

However, due to the high penetration rate of the current NTSC television system, in order for high-definition broadcasting formats such as MUSE broadcasting and second generation HDTV broadcasting to become widespread, it is difficult to match the NTSC format, which currently has a high penetration rate. 16 for compatibility
It is necessary to display 4:3 NTSC video on a 9:9 display.

Aspect ratio 4 on a 16:9 aspect ratio display
An example of a conventional technique related to a method for displaying NTSC video of 3:3 is disclosed in Japanese Patent Application Laid-Open No. 194783. An overall block diagram of this circuit is shown in FIG.

In FIG. 7, 701 is a video signal input terminal, 702 is a Y/C separation/color demodulation circuit, 703 is a line memory, and 70
4 is a display, 705 is a horizontal synchronization separation circuit, 706
is the first PLL, 707 is the second (7) PLL, 708 is the Mth) PLL, 709 is the selector, 710 is the horizontal synchronization oscillation circuit, 711 is the vertical synchronization separation circuit, 712 is the vertical scanning variable circuit, and 713 is the vertical It is a drive circuit.

The input video signal 701 is separated into Y/C and color demodulation circuit 7
02, the luminance signal and the color difference signal are separated and color signal demodulation is performed, and the output signal of the Y/C separation/color demodulation circuit 702 is time-base compressed in the line memory 703, and the output signal of the line memory 703 is It is displayed on the display 704. Further, a horizontal synchronization component of the video input signal is separated by a horizontal synchronization separation circuit 705, and a first PLL 706 uses the output signal from the horizontal synchronization separation circuit 705 to generate a write clock for the line memory 703. A first read clock is generated. Further, the output signal from the horizontal synchronization separation circuit 705 is transmitted to the second PLL.
707 and a third PLL 708 to generate a second read clock for the line memory 703 and a third read clock for the line memory 703, respectively. The selector 709 has the first, second and third
read clocks are supplied, and one of these read clocks is selected and supplied to the line memory 703. At the same time, the horizontal synchronization oscillation circuit 710 oscillates a horizontal synchronization signal for the display 704 from the output signal from the horizontal synchronization separation circuit 705 and supplies it to the display 704. Further, a vertical synchronization signal is separated from the video input signal by a vertical synchronization separation circuit 711, and the vertical scan range of the display 704 is varied by a vertical scan variable circuit 712 using the separated vertical synchronization signal. An output signal from this vertical scanning variable circuit 712 is supplied to the display 704 by a vertical drive 713.

The characteristic of the conventional example shown in FIG. 7 is that by switching the clocks from multiple PLLs and making the vertical deflection width of the display variable, it is possible to produce a 4:3 image of current television broadcasting and a 16:3 image of high-definition television broadcasting. 9 images and horizontally long movie software images can be displayed on a single display in full screen size.

Another conventional example is Japanese Patent Application Laid-Open No. 194784. A block diagram of this main part is shown in FIG. 8(a).

In FIG. 8(a), 801 is a video input signal, 802 is a memory, 803 is a display, 804 is a synchronization input signal, 805 is a write synchronization generation circuit, 806 is a read synchronization generation circuit, 807 is a selector, and 808 is a delay synchronization generation circuit. A circuit 809 indicates a horizontal synchronous oscillation circuit.

A video input signal 801 is time-axis compressed in a memory 802.
It is displayed on the display 803. A write synchronization generation circuit 805 generates a write synchronization signal for the memory and a first read signal for the memory from the synchronization input signal 804. A synchronization generation circuit 806 reads from the synchronization input signal.
, a second read signal for the memory is created, and a selector 807 selects the first read signal and the second read signal and supplies them to the memory. A delay synchronization generation circuit 808 generates a synchronization signal delayed with respect to the write synchronization signal from the synchronization input and the output signal of the read synchronization generation circuit 808.
A horizontal synchronous oscillation circuit 809 oscillates a horizontal synchronizing signal for the display from the output signal.

The characteristics of this circuit are shown in FIGS. 8(b) and (C).

By delaying the memory read synchronization signal with respect to the memory write synchronization signal as shown in (d), images can be displayed at any position on the display, and when a signal with a lot of synchronization fluctuation is input, the memory A discrepancy occurs between the write synchronization period and the read synchronization period,
It is possible to prevent a phenomenon in which a read reset is inputted before a write reset and the image shifts within the field (for convenience, this will be referred to as overtaking).

In this way, 16:9 images can be displayed on a 16:9 display with 4
:3 images could also be displayed.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, when inputting a video signal with a different screen display area, such as current broadcasting, cinema-sized movie software, or Vista-sized movie software, as a video input signal, the movie software can be displayed on the screen in a 4:3 ratio. The advantage was that the signal could be displayed anywhere on the 16:9 screen.

However, with the above conventional technology, when a signal that is likely to cause synchronization fluctuation, such as a VTR signal, is input, the vertical line on the screen appears as a curvature, and consideration is not taken during double-speed scanning, resulting in the following problems. There was a problem.

1. No consideration was given to image compression in systems that display double-speed signals such as EDTV.

2. A PLL for clock generation on the signal processing side and a PLL for synchronized playback on the display side are required independently, and the two PLLs respond differently to synchronization fluctuations such as jitter and skew, making it difficult to fully absorb this fluctuation. do not have.

In view of the above, the first object of the present invention is to provide a double-speed display wide television receiver that enables image compression. A second object is to provide a receiver that suppresses image shaking as much as possible due to input signal jitter and skew.

[Means to solve the problem]

The first object is to provide an actual supplementary scanning line signal generation circuit that generates an actual scanning line signal and an interpolation signal from an input video signal of standard speed scanning with an aspect ratio of 4:3, and the actual supplementary scanning line signal generation circuit. a signal conversion memory circuit for storing an output signal from the signal converting memory circuit and generating a time-doubled scanning image signal in which the information range of the image is less than half of the information range of the standard speed scanning video signal; and the output signal of the signal converting memory circuit. a double-speed scanning wide aspect ratio display that displays a double-speed scanning wide aspect ratio display, and a time obtained by subtracting the double-speed scanning time from the information range time of the standard-speed scanning video signal by subtracting the information range time of the double scanning image signal from the video signal. a memory control circuit that generates an image compression clock signal and a control signal for the signal conversion memory circuit and supplies them to the signal conversion memory circuit; This can be achieved by simultaneously realizing double-speed scanning conversion processing and aspect ratio conversion processing using the signal conversion memory circuit.

Next, the second object is to provide the wide television receiver with a standard synchronous reproducing circuit that reproduces a standard synchronous signal from an input interlaced scanning video signal, and a standard synchronous reproducing circuit that reproduces a standard synchronous signal from an input interlaced video signal. a write clock generation circuit that reproduces a write system clock of the memory from the output signal of the memory, and a write control signal for the signal conversion memory circuit that generates a write control signal of the signal conversion memory circuit from the output signal from the standard synchronous reproduction circuit and the clock from the write clock reproduction. a write control signal generation circuit; a read clock generation circuit that reproduces a read clock from an output signal of the write control signal generation circuit; and a double-speed read control signal for the signal conversion memory circuit from the write control signal and the read clock generation circuit. and a read control signal generation circuit to be created.

[Effect]

The actual supplementary scanning line signal generation circuit generates an actual scanning line signal for sequential scan conversion and an interpolation scanning line signal from the input video signal, and supplies them to the signal conversion memory circuit. The memory control circuit generates an image compression clock signal and a control signal for the signal conversion memory circuit, and supplies the image compression clock signal and control signal to the signal conversion memory, so that the signal is horizontally compressed and double-speed converted from the signal conversion memory circuit. A signal can be output and supplied to the display.

Further, the double-speed synchronization reproduction circuit generates a double-speed synchronization signal from the image compression clock signal and supplies it to the display.

Therefore, a standard-speed scanning video signal with an aspect ratio of 4:3 can be displayed on the double-speed scanning display with an aspect ratio of 16:9.

Further, the write clock generation circuit and the write control signal generation circuit generate signals that control the write system of the signal conversion memory circuit, and the read clock generation circuit and the read control signal generation circuit generate signals that control the read system of the signal conversion memory circuit. Since the display is driven by a double-speed synchronization signal synchronized with the readout system by a double-speed synchronization reproducing circuit, the readout image signal and the synchronization signal are configured to have the same fluctuations, so it is not susceptible to jitter or skew. It is possible to suppress image shaking.

〔Example〕

An embodiment of the present invention is shown in FIG. 1 below.

In FIG. 1, 101 is an input terminal for a video signal, and 102 is an actual supplementary scanning line signal generation circuit (hereinafter abbreviated as HDTV processor) that generates an actual scanning line signal R and an interpolated scanning line signal I.
, 103 is a time axis compression memory, 104 is a 16:9 display, 105 is a standard synchronous playback circuit, and 106 is a first (7th)
) PLL, 107 is a write control generation circuit, 108 is a read control generation circuit, 109 is a second PLL, 11o is a double speed synchronous reproducing circuit, 111 is the double speed conversion memory 10
This is a memory control circuit that controls 3.

The video signal inputted from the input terminal 101 is converted into an actual scanning line signal R and an interpolated scanning line signal by the EDTV processor 102, and then sent to the memory control circuit 1 by the double speed conversion memory 103.
The signal is compressed to 3/4 in the horizontal direction and converted into a double-speed scanning signal by the compression clock and control signals supplied from 11, and then displayed on the 16:9 display 104.

A write control signal for the memory 103 is generated by a write control generation circuit 107 using a clock generated by the first PLL l06 from the output signal of the standard synchronization reproducing circuit 105.

The read control signal for the memory l○3 is generated by the write control generation circuit 107 by dividing the clock generated by the first PLL 106 and supplying the output signal to the second PLL 109. The read control generation circuit 108 uses the newly generated lock and the write reference signal which is the output signal of the write control generation circuit 107.
It will be played at.

Further, the double-speed synchronous regeneration circuit 110 generates a double-speed synchronous signal based on the read clock signal generated by the second PLL 109 and the read reference signal generated by the read control signal generation circuit 108, and supplies it to the 16:9 display 104. do.

゛ The feature of this circuit is that by supplying the output signal of the EDTV processor to the time-base compression memory 103, the time-base compression memory 103 simultaneously realizes double speed conversion and aspect ratio conversion. The purpose of this technology is to make it possible to display a video signal with a wide aspect ratio on a double-speed scanning display with a wide aspect ratio.

Next, the configuration of the time axis compression memory 103 will be described in detail. FIG. 3 shows an example of the configuration of an HDTV processor and time-base compression memory, and a timing chart of memory control signals.

In FIG. 3, 301 is a double speed conversion memory, 302 is an aspect ratio conversion memory, WRES is a memory write reset signal, RRES is a memory read reset signal,
WCK indicates a memory write clock, and RCK indicates a memory read clock. Also, Figure 3 (1) to (7)
shows a schematic waveform diagram of each signal.

The operation of each memory will be explained below along with waveforms.

From the video input signal 101, an actual scanning line signal R and an interpolated scanning line signal (2) are generated by an HDTV processor 102 and supplied to a time-base compression memory 103. After the output signal of the HDTV processor 102 is subjected to double-speed scanning line conversion processing in the double-speed conversion memory 301, the aspect ratio conversion memory 30
2, horizontal compression conversion is performed. In the double speed conversion memory 301,
RRESl (Figure 3 (2)) is converted to WRESI (Figure 3 (1)
)) and read clock RCK.
1 (Figure 3 (5)) as the writing clock wCK
Double speed conversion is performed by doubling the frequency of 1 ((4) in FIG. 3). In the aspect ratio conversion memory 302, RC
The frequency of K2 (Fig. 3 (7)) is changed to WCK2 (Fig. 3 (5)
)) is 4/3 times the frequency. In addition, in order to determine the reference position in the horizontal direction, WRES2 (Figure 3 (4))
In order to supply RRES2 (Figure 3 (4)) at a double speed cycle and to minimize the number of waveforms of WCK2 and RCK2 in the ] line, time axis compression can be achieved accurately by stopping RCK2 for 1/4 line. can.

With such a configuration, the time axis compression memory 103
can realize double speed conversion and aspect ratio conversion at the same time.

Furthermore, other configuration examples of the time axis compression memory 103 will be described. FIG. 4 shows an example of another configuration of the EDTV processor and the time axis compression memory, and a timing chart of memory control signals.

In FIG. 4, circuit blocks that are the same as those in FIG. 1 are denoted by the same reference numerals. WRES is a memory write reset signal, RRES is a memory read reset signal, W
CK is the memory write clock, RCK is the memory read clock, D■ is the input video signal to the memory, DO
indicates the output video signal from the memory. Also, Figure 4 (1
) to (6) show waveform diagrams of the respective signals.

An actual scanning line signal R and an interpolated scanning line signal I are generated from the input signal 101 by the HDTV processor 102 as shown in FIG. 4 (3).
The data is supplied to the time axis compression memory 103 at a timing such as .

That is, the video signal has a color subcarrier frequency of 3.58M H
z (abbreviated as fsc), one horizontal scanning period (Ths) of the input video signal is composed of 910 clocks, and the information period (Tes) of the video is 740 clocks. clock, and the rest is the retrace period.

In the time axis compression memory 103, RRES (Fig.
)) is half the period (Th
p#1/2XThs) to perform double speed conversion. Furthermore, the frequency of RCK (Figure 4 (5)) is changed to WCK.
Thp near 4/3 times the frequency of (Figure 4 (2))
Set the frequency so that the number of waveforms becomes an integer in the period of 1/
By stopping RCK for four lines, the clocks of WCK and RCK for one line are made exactly the same to perform time axis compression. For example, in the example shown in FIG. 4, if the RCK frequency is 9/7 x 4 fsc, there will be 1170 clocks per double-speed horizontal scanning period. this house,
The information period (Tep) of a double-speed image is 740 clocks, so in order to correctly perform double-speed conversion and aspect ratio conversion, one horizontal period (Thp) of double-speed scanning is required.
) and the above information period (Tep) (Thp+Tep) is the standard speed information period (Tes
), each memory control signal (WRE
S, WCK, RRES, RCK,) must be provided. That is, Tep (seconds) > Tes (seconds) - T
hp (seconds) □ (1) If this condition is not met, the above-mentioned overtaking phenomenon will occur on either the actual scanning line or the interpolated scanning line of the double-speed signal (changes depending on the RRES position). occurs, resulting in an incomplete double-speed conversion operation. According to the condition (1) above, the output of the time axis compression memory 103 is
), it is possible to obtain a signal with a double-speed period and a compressed time axis. In this way, the double speed conversion memory and the aspect ratio conversion memory can be shared.

In addition, in the above embodiment, the frequency generated by the second PLL 109 was set to 9/7X4fsc, but the two frequency ratios (frequency division ratio) and the number of phase comparisons per line are summarized when other frequencies are used. This is shown in Figure 2. The output signal of the EDTV processor 102 may be configured to multiplex the actual scanning line signal and the interpolated scanning line signal and supply it to the double-speed memory 103 at 8 fsc. Therefore, for convenience, the number of pixels per line is set to twice 910. This will be explained below as 1820.

In Figure 2, if the frequency division ratio between the read clock and the write clock is M:N, then the number of pixels per line of the video signal read from the memory is K (K is a natural number) = (M/N) 1820- It is expressed by the formula (2,). Further, the distortion ratio α of the image displayed on the display is expressed by α=(4/3)/(M/N)−(3). The read frequency f of the memory is f = M/NX 8 f sc (4)
It is a formula. In addition, the number of PLL phase comparisons per line of input signal β is β = 1820/N According to the above equation (5), under good conditions with an image distortion ratio of 95% or more, the number of PLL phase comparisons that is the most The result is that the circumferential ratio is 9/7. Furthermore, since the frequency division ratio is represented by the simplest integer ratio, there is an advantage that the number of stages of the frequency division counter can be reduced.

A detailed block diagram of the second PLL in the embodiment of the present invention is shown in FIG.
is vco,! 506 is an unlock determination circuit, 507 is a counter, 508 is a decoder, 509 is an M frequency dividing circuit, 5.
10 indicates a selector.

The write control circuit is regenerated by the write control generation circuit 107 based on the synchronization signal inputted to the input terminal 501, and the output clock of the write control signal synchronization circuit is divided by N by the N frequency divider circuit 502. The unlock determination circuit 506 compares the internal reset signal of the N frequency divider circuit 502 (the reset signal generated by the decoder 508) and the external reset signal (the reset signal generated by the write control generation circuit 107), and determines whether the internal If the reset signal and the external reset signal exist within a certain period of time, it is determined that the device is in a locked state, and if not, it is determined that it is in an unlocked state. In the unlock determination circuit 506, a decoder 508 generates the output of a counter 507 that counts the clocks generated by the second PLLI 09, and compares the output signal of the decoder 508 with the output signal of the write control generation circuit 107. A signal for determining the synchronization state of the second PLL 109 is supplied to the selector 510, and according to this selection signal, the output of the decoder 508 is reset when locked, and the write control generation circuit 1 is reset when unlocked.
Select 07 output reset.

The phase comparator 503 compares the phases of the output signal of the N frequency dividing circuit 502 and the output signal of the write control generation circuit 107, extracts the low frequency component from the output using the LPF 504, and extracts the low frequency component from the output using the LPF 504. generates a clock controlled by the domain components.

The unlock determination circuit 506 locks once in one field, and then if it is in the locked state, makes the counter 507 run freely by an internal reset signal, and if it is determined to be unlocked, first the counter 507 is forcibly reset externally. By resetting with a signal, the time required for the second PLL to lock again when it loses lock is shortened.

With such a configuration, the transmission output of the second PLL l09 can be made to accurately follow the synchronization of the incoming video signal.

Furthermore, a second PLL embodiment of the present invention is shown in FIG.

In FIG. 6, 601 is a switch, 602 is a vertical synchronizing signal input terminal, and 603 is a continuous lock detection circuit.

The characteristic point of FIG. 6 compared to FIG. 5 is that the phase comparator 5
Switch 601 for signal disconnection between 03 and LPF504
and a continuous unlock detection circuit 603 that controls the disconnection switch 601. If there is a continuous unlocking within one field, the continuous unlocking detection circuit 603 counts the number of consecutive unlockings in one field, and switches the disconnection switch 601.
The input of LPF 504 is held until the next field is reached.

In this way, in this embodiment, when the lock is lost for a long period, the input to the LPF 504 is cut off and the internal voltage is maintained, so that the second P
It has the feature of making the LL a free-running oscillation state and reducing the curvature of vertical lines in the image due to synchronous fluctuations of the input signal.

A block diagram of another embodiment of the present invention is shown in FIG. In FIG. 9, circuit blocks that are the same as those in FIGS. 1 and 3 are marked with the same circuit symbols. 902: a write control generation circuit; 903: a memory with three or more lines for aspect conversion; 904: a fixed frequency generation circuit; 90:
5 is a clock switching circuit.

The configuration of this embodiment is almost the same as in FIGS. 1 and 3, but
The generation method of the memory read clock and the memory capacity are different. That is, a constant frequency generated by a fixed frequency oscillation circuit 904 is used as the read clock for the aspect conversion memory 903. Also, since the double speed conversion memory 301 is used independently as in FIG. 3, the WRESI of the double speed conversion memory 301 (FIG. 3 (1))
・RRESI (Figure 3 (2)) ・WRES2 (3rd
Figure (3)) Write clock WCKI (Figure 3 (
4)) A read clock RCK1 and a write clock WCK2 ((5) in FIG. 3) are each generated by a write control generation circuit 902. Furthermore, since read synchronization and write synchronization are asynchronous, a memory capacity of 3 lines or more is required, which is larger than in the cases of FIGS. 1 and 3, in order to prevent overtaking that occurs between resets.

The feature of this circuit is that the read clock of the aspect conversion memory 903 is generated at a constant frequency by the oscillation circuit 904, thereby reducing jitter. Furthermore, when a configuration is adopted in which the clock switching circuit 905 can switch between the output clock from the write control signal generation circuit 105 and the output clock from the read control signal generation circuit 108, and the video is displayed on the entire wide screen,
It is also possible to select whether to compress the display. Also in this embodiment, the double speed conversion memory 902 is similar to FIG.
It goes without saying that the capacity can be reduced by using the same memory as the aspect conversion memory 903 and the aspect conversion memory 903.

〔Effect of the invention〕

According to the present invention, it is possible to provide a double-speed display wide television receiver that enables image compression. In addition, the memory capacity mounted on the circuit can be reduced, which is economical. Furthermore, image shake can be suppressed due to jitter and skew, improving performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing the frequency ratio of two PLLs and the number of phase comparisons in one line in an embodiment of the present invention, and FIG. 3 is a diagram showing the EDTV processor and An example of the configuration of a time axis compression memory and a timing chart of a memory control signal, FIG. 4 is a memory configuration and a timing chart of a memory control signal when the double speed conversion memory and the time axis compression memory of an EDTV processor are shared,
FIG. 5 is a detailed block diagram of the second PLL in an embodiment of the present invention, FIG. 6 is another detailed block diagram of the second PLL of the present invention, and FIG. 7 is a conventional wide aspect ratio display. Block diagram of a television with
Figures (b), (c), (
d) is a diagram showing the position of the frame during horizontal compression in another conventional example, and FIG. 9 is a block diagram of another embodiment of the present invention. 101...Video input terminal, 102...EDTV processor, 103...Time axis compression memo 1c 104--
Bow 6:9 display, 105... standard synchronous reproducing circuit, 106... first PLL, 107... write control generation circuit, 108... read control generation circuit, 10
9... Second PLL, 110... Double speed synchronous regeneration circuit, 111... Memory control circuit, 301... Double speed conversion memory, 302... Aspect ratio conversion memory, 501
...Synchronization signal input terminal, 502...N frequency dividing circuit, 5
03...Phase comparator circuit, 504...LPFl 50
5...VCO1506...Unlock judgment circuit, 5
07... Counter, 508... Decoder, 509...
...M frequency divider circuit, 510...selector, 601...
Switch, 602... Vertical synchronization signal input terminal, 603
. . . Continuous unlock detection circuit, 701 . . . Video input terminal, 702 . . . Y/C separation/color demodulation circuit, 703.
...Memory, 704...Display, 705...
Horizontal synchronization separation circuit, 706...first PLL, 707
...Second PLL, 708...Third PLL, 70
9...Selector, 710...Horizontal synchronous oscillation circuit, 7
11... Vertical synchronization separation circuit, 712... Vertical scanning variable circuit, 713... Vertical drive circuit, 801...
Video input terminal, 802...Memory, 803...Synchronization input, 804...Write synchronization generation circuit, 805...
・Read synchronization generation circuit, 806...Selector, 80
7...Delayed horizontal synchronization generation circuit, 902...Write control generation circuit, 903...Aspect conversion memo 1c9
04... Fixed frequency oscillation circuit, 905... Clock switching circuit.

Claims (1)

[Claims] 1. The image information range is Tes seconds and the horizontal scanning period is Ths.
an input terminal for inputting an interlaced scanning video signal with an aspect ratio of 4:3 seconds; a double-speed scanning display having a wide aspect ratio and a horizontal scanning period of Thp seconds, which is approximately half of Ths seconds; an actual supplementary scanning line signal generation circuit that generates an actual scanning line signal and an interpolated scanning line signal from an input video signal; a signal conversion memory circuit that generates a double-speed scanning image signal with a horizontal scanning period of Thp seconds and supplies it to the display; >Tes (seconds) - Thp (seconds); a memory control circuit that generates an image compression clock signal and a control signal for the signal conversion memory circuit and supplies them to the signal conversion memory circuit; and an image output from the memory control circuit. a double-speed synchronization reproducing circuit that generates a double-speed synchronization signal with a horizontal scanning period Thp (seconds) from the compression clock signal and supplies it to the display; the signal conversion memory circuit simultaneously realizes double-speed scan conversion and aspect ratio conversion; A wide television receiver characterized by displaying a 4:3 interlaced scanning video signal on a wide aspect ratio double-speed scanning display. 2. The wide television receiver according to claim 1, wherein the memory control circuit includes: a standard synchronous reproducing circuit that reproduces a standard synchronous signal from an input interlaced video signal; and an output signal from the standard synchronous reproducing circuit. a write clock generation circuit that regenerates a write system clock of the memory; and a write control signal that generates a write control signal for the signal conversion memory circuit from the output signal from the standard synchronous regeneration circuit and the clock of the write clock generation circuit. a read clock generating circuit that reproduces a read clock from the output signal of the write control signal generating circuit; and a read clock generating circuit that generates a double-speed read control signal for the signal conversion memory circuit from the write control signal and the read clock generating circuit. A wide television receiver comprising a control signal generating circuit. 3. The wide television receiver according to claim 2, wherein the read clock generation circuit uses an output signal obtained by dividing the write clock from the write control signal generation circuit by N as a reference signal, and generates a phase difference three or more times per line. A wide television receiver characterized by being configured with a comparative PLL circuit. 4. The wide television receiver according to claim 2 or 3, wherein the write control signal generation circuit generates a write reference signal, the read control signal generation circuit generates a read reference signal, and the two standards a lock/unlock determination circuit that determines the synchronization state of the two control signal generation circuits from the signals; a selector that switches between the write reference signal and the read reference signal; and the selector that uses the output signal of the lock/unlock determination circuit. , and initializes the readout control signal generation circuit with the output signal of the selector. 5. The wide television receiver according to claim 2, wherein the read clock generation circuit generates a fixed frequency clock.