JPH04186849A - Enhancement type heterojunction field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce source resistance and obtain a stably operating E-FET, by a method wherein a second semiconductor layer in contact with the same side as a gate electrode of a first semiconductor layer with which the gate electrode is in contact is provided, and third semiconductor layers of ohmic junction which have source and drain electrodes on the second semiconductor layer are provided. CONSTITUTION:In an enhancement type heterojunction field-effect transistor, a second semiconductor layer 9 in contact with the same side as a gate electrode 15 of first semiconductor layers 8-2 with which the gate electrode 15 is in contact is provided, and third semiconductor layers 10-12 of ohmic junction which have a source electrode 13 and a drain electrode 14 are provided on the second semiconductor layer 9. For example, semiconductor layers 2-12 and an SiO2 film 16 are formed on a semi-insulating GaAs substrate 1; a hole is opened in a P<+>-GaAs cap layer 12; thereon a source electrode 13 and a drain electrode 14 are formed; a gate pattern is formed, and etching is performed as far as this side of an undoped AlGaAs layer 8; after Al is evaporated, a gate electrode 15 is formed by lifting-off.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a heterojunction field effect transistor manufactured by epitaxial growth, and particularly to an enhancement type field effect transistor that is effective for digital circuits.

[Conventional technology 1 FET (Fie) manufactured by epitaxial growth
, dEffect Transistor (abbreviation for field effect transistor), the source electrode, drain electrode, and gate electrode are attached on the same epitaxial layer, or as described in, for example, JP-A-63-60
As described in Japanese Patent No. 570, a structure was adopted in which a source electrode and a drain electrode were attached on the same epitaxial layer with a thick film cap layer formed for the purpose of reducing source resistance interposed therebetween. Regarding the reduction of resistance in P-channel FET, for example, IE Transaction on Electron Devices, Vol. ED-34 (198
7) page 1889 [IEEE Transaction
onElectron Devices, 34 (19
87) As described in 1889), M I S (Met
al-Insulator-5emiconducto
(abbreviation for r) FET, this was done by ion implantation. [Problem to be solved by the invention] Heterozygous enhancement type
t) In order for an FET (hereinafter abbreviated as E-FET) to operate normally, at least the channel layer directly under the gate must be depleted when no voltage is applied to the gate.On the other hand, when a gate voltage is applied, the channel layer must be depleted. Sufficient carrier density is required not only directly under the gate but also under the source and drain electrodes.However, as an E-FET, a region with the same semiconductor structure as the gate is required between the gate and other electrodes. If the P-channel FET is
In a heterojunction device using an aAs strained layer channel,
In ion implantation as described in the above IE Transaction on Electron Devices, InGaA
There were problems such as deterioration of the characteristics of the s-layer. In order to solve this problem, an N-channel HEMT (High E
lectron Mobility Transiste
In the method of thickening the cap layer in r), D-FET (D
(abbreviation of ippletion FET), it could not be applied to E-FET. Therefore, it is an object of the present invention to solve the above-mentioned conventional problems, and the first object is to reduce the source resistance, which greatly contributes to the performance of FET, and to improve stable operation of the E-FE.
The second purpose is to provide the above E-FET
An object of the present invention is to provide a manufacturing method that can easily realize the following. [Means for Solving the Problems] The first object is to provide an enhancement type heterojunction field effect transistor in which a first semiconductor layer in contact with a gate electrode is provided with a second semiconductor layer in contact with the same side as the gate electrode. This is achieved by an enhancement type heterojunction field effect transistor having an ohmic junction third semiconductor layer having source and drain electrodes on the second semiconductor layer. The second object is to provide a method for manufacturing an enhancement type heterojunction field effect transistor.
When the channel layer is an N channel, an n--GaAs layer is stacked on the semiconductor layer, and when the channel layer is a P-channel, a p-GaAs layer is stacked as the second semiconductor layer, and this second semiconductor layer is etched only directly below the gate. A gate electrode is formed on the removed and exposed first semiconductor layer, a thickened cap layer is formed as a third semiconductor layer on the second semiconductor layer, and a third semiconductor layer is partially buried in the cap layer. This is achieved by a method for manufacturing an enhancement type heterojunction field effect transistor in which source and drain electrodes are formed in the same state. [Function] The E-FET requires that no current flow between the source and drain when no voltage is applied to the gate. For this reason, the carrier density at least in the channel portion directly under the gate needs to be reduced. For example, P channel HE M T (High Electron Mob
Although the carrier is a hole, it is called this for convenience. ) will be considered below. FIG. 2 shows the band structure for electrons directly below the gate 15. As shown in the figure, the energy of the part of the InGaAs layer 5 closest to the AIGaAs layer 6.7.8 (hereinafter referred to as the channel) is the Fermi energy (]00. display). Therefore, when no voltage is applied,
Holes cannot flow from source to drain. That is, the region between the source and drain is in an off state. If the band structure directly below the source and drain electrodes is the same as that directly below the gate electrode, even when a voltage is applied to the gate, holes will not accumulate in the channel directly below the source and drain, and it will remain in an off state, operating as a FET. do not. Here, when the band structure directly under the source or drain electrode becomes as shown in Figure 3 (in this figure, the source electrode 1
3), p--Ga which becomes the second semiconductor layer
Since the As layer 9 is sandwiched between the first semiconductor layer 8 and the source electrode 13, the energy in the region below the p-AlGaAs layer 7, which is also one of the first semiconductor layers, is as shown in the figure. Therefore, the energy of the channel portion indicated by diagonal lines is higher than the Fermi energy of 100. As a result, there are holes in the channel that can contribute to conduction even when no voltage is applied. When a voltage is applied, holes are accumulated in the channel even in a portion directly below the gate 15, and the region between the source and drain is turned on, as shown in FIG. With such a mechanism,
E-FET operates stably. However, by sandwiching such a second semiconductor layer 9, the source resistance increases. For this reason, a thick high-concentration dope layer as one of the third semiconductor layers is provided as a cap layer directly under the source 13 and drain 14 electrodes, and each electrode is semi-buried in this structure. Accordingly, the source resistance can be reduced.

【Example】

An embodiment of the present invention will be specifically described below using the drawings. Example 1 FIG. 1 shows a heterojunction field effect transistor (
2 is a cross-sectional structural diagram of a P-channel E-FET in HEMT structure). The manufacturing process will be sequentially explained below. First, undoped GaAsN (thickness: 0.3 pm) was deposited on a semi-insulating GaAs substrate 1 using an MBE (molecular beam epitaxy) device at a substrate temperature of 650°C.
, undoped A I XG a l XA S M (
X”0.45,0.:bm) 3. Undoped Ga
A s reservoir (50 nm) 4, undoped I nyGai
yAs layer (y=0.2+20 nm) 5, undoped A
1 xG a , XAS layer (x=0.45.2-
10 nm)6, p-AlxGa, xAs layer (x20.
45. Concentration: ], 5X10"/cm2, 25nm) 7
, undoped A I XG a , xA s layer (x=
0.45.15 nm) 8. p-GaAs layer (30n
m) 9, undoped A1. Ga1-As layer (x=0.4
5,3 nm) 10, undoped GaAs layer (50 nm
) 11, and finally, at a substrate temperature of 500°C, a p-GaAs layer (concentration: 3X]O” was grown as a cap layer.
cm/2,160 nm) 'J, 2 is deposited. In the above structure, layers 8 and below constitute a first semiconductor layer, layer 9 constitutes a second semiconductor layer, and layers 10 to 12 constitute a third semiconductor layer. Undoped A I G a A s N 6 is P type A
IGaAs is a layer that suppresses the diffusion of P-type impurity atoms (Be) in M7 into the channel layer 5, and is usually
10 nm is appropriate. Further, the undoped AlGaAs layer 8, which is the first semiconductor layer, is a layer in contact with the gate 15, and is provided to suppress gate leakage current. Next, after performing inter-element isolation for forming sources and drains by mesa etching, SiO
2 films (thickness: 300 nm) 16 are formed, and holes for the source electrode] 3 and the drain electrode 14 are formed by a normal photolithography process. S]02 film 16 on the surface of this hole is scraped with a 6-layer + chip, and then a p-GaAs cap layer 1 is removed.
A hole of about 40 nm is formed through wet etching. At this time, when the thickness of the cap/1112 is about 160 nm, etching of about 30 nm or more produces the effect of lowering the resistance, and the most practically preferable etching depth is 40 to 50 nm. Furthermore, the Si○2 film 16
Side-etch the film using a 6-etch etch to create a shape that facilitates lift-on. On top of this A u / M o / to u Z n / M
Deposit o/A u and heat treatment (400℃, 2 minutes)
Then, a source electrode 13 and a drain electrode 14 are formed. Furthermore, a gate pattern is formed using an EB (electron beam) lithography method. At that time, the p-GaAs cap layer 12
2F2/He-based selective tri-etching is provided to remove the undoped AlGaAs layer 10 with good controllability, and furthermore, the gate electrode 15 is
- In order to avoid contact with the GaAs cap 112,
The p-GaAs cap layer 12 is side-etched to form a 0
．． 05~0, a gap 17 of about 1 llIn is provided,
In addition, undoped AIG a As F@10 and p-GaAsJii9 were etched. This step is necessary to increase the withstand voltage. Furthermore, C.C.
By selective I, F2/He based tri-etching, the undoped AIG a As layer 8 was etched away with good controllability. Undoped A becomes this first semiconductor layer
The lGaAs layer 8 also plays the role of an etching stopper when the second semiconductor layer 9 is dry-etched selectively and with good control. Further, after depositing A1, lift-off was performed to form a gate electrode 15 having a gate length of 0.1 μm and a gate width of 50 μm. In this way, a P-channel E-FET having the structure shown in FIG. 1 was realized. The E-FET according to this embodiment has a breakdown voltage of 26V, a mutual conductance ga: 203rnS/mrn, a source resistance Rs: 7.0Ω・mm, and a value of 3.3mS/mrn.
It showed high performance with a V of 10 μm. Furthermore, in Figure 5,
The relationship between the embedding depth when embedding the source 13 and drain 14 electrodes into the cap layer 12 and the source resistance R5 is shown. As shown in the figure, an embedding depth of 40 to 50 nm is practically most preferable and indicates a source resistance Rs near, 0 Ω·mm. Further, FIG. 6 shows the relationship between drain voltage and drain current using gate voltage v6 as a parameter. As shown in the figure, good characteristics as an E-FET were obtained. Note that when epitaxial crystal growth is performed in the manufacturing process, similar results can be obtained by using a device that can control growth on an atomic layer basis, such as MOCVD, instead of the MBE used here. Further, the thickened cap layer 12 may be formed later using a technique such as MOCVD selective growth, for example. In addition, the cap N12 is not limited to GaAs.
For example, a material that facilitates ohmic contact, such as InGaAs, may be used. Also, undoped A directly under the gate
The IGaAs layer 8 is made of p-AlGaAs with an IX 10"/cm2 or less so as not to reduce the withstand voltage.
may also be used. At this time, the breakdown voltage deteriorates a little, but the source-gate resistance Rs becomes smaller. Further, if this layer 8 is an undoped or p-layer, the ohmic alloy layer does not penetrate into the region between the source electrode 13 and the gate electrode 14, so the layer thickness is preferably 15 nm or less. but,
If it is too thin, the withstand voltage will be low, so a thickness of about 5 nm is necessary. Ultimately, the thickness of the undoped N8 as the first semiconductor layer is appropriately and preferably about 5 to 15 nm. In this example, 0.45 was used as the Al concentration X of the AlxGalxAs layer, and 0.2 was used as the Inli degree y of the InyGa□yAs layer, but these values were used to increase the carrier concentration of the channel layer 5. Similar results can be obtained by using values of approximately 0.2 to 0.5 for X and approximately 0.05 to 0.4 for y. Further, although InGaAs is used for the channel layer 5, GaAs may of course be used. In addition, the layer structure is also Ga
Not limited to the A s / A I G a As system, but also other types, such as 1. I n Ga As on nP substrate
Similar results can be obtained even in systems where the lattice constants are the same or slightly different, such as the A I G a As system. Furthermore, if a similar structure is used, but the conductivity type is opposite to that of this embodiment, the N-channel E-FET can be used instead of the P-channel E-FET.
FETs can also be made. Needless to say, this can be achieved by replacing all the P-doped layers in FIG. 1 with N-doped layers. The values used in this example are In concentration y=0.2 in the InyGa1yAs layer, AlxGa1. The A1 concentration x in the As layer is 0,3, and the thickness of each layer is the same as in the case of the P channel. Here again, X is 0.2 to 0
．． Similar results can be obtained by using any value of about 5 and about 0.05 to 0.4 for y. Example 2゜This example is HIG FET (Heteroju
nctjonInsulated Gate F E
This figure shows an example of a P-channel E-FET in a heterojunction field effect transistor having a T) structure, and will be described below with reference to the cross-sectional structural diagram of FIG. First, on a semi-insulating GaAs substrate] A1, -G a
s layer (thickness: 0.3 pm) 2, undoped AlxG
a, x As layer (x = 0.45, 0.3 inch) 3, p-
InyGa, yAs layer (y=0.2. Concentration: 1.3X)
O”/cm2.lo nm)-18, undoped A 1
xG a 1 xA s layer (x=0.45.] Onm
) 8, p-G a As M (30 nm) 9,
Undoped A 1 xG a 1xA s layer (x=0
．． 45.3 nm)10. Undoped G a As layer (
50 nm) 11, and finally a p-GaAs layer (concentration = 3χ101'l/c) as a camp layer.
m2, 25 nm)]2 is deposited. The following process is the same as in Example 1. In other words, in this example, N4 to N7 of Example 1 were replaced with p-InG.
It has a structure in which the aAs layer 18 is substituted. The characteristics of the E-FET shown in FIG. 7 obtained in this way are as follows:
Withstand voltage 26■, mutual conductance g: 305 m S
/ mrn, source resistance Rs: 13.2Ω・mm
, it showed high performance with a value of 3.1rnS/V10μm. Note that similar results can be obtained for crystal growth using an apparatus 1 that can control growth on an atomic layer basis, such as MOCVD, instead of MBE. Also, the undoped A I directly under the gate
The GaAs layer 8 is made of
I X 1018/cm p-AIG a below
A s may also be used. At this time, the breakdown voltage deteriorates a little, but the source-gate resistance Rs becomes smaller. In addition, as described in Example 1, if the conductivity type of the epitaxial layer is set to the opposite conductivity type, N
Channel E-FETs can be made. In other words, in this case, the P-tope layer of the above embodiment is completely changed to an N-tope layer. [Effects of the Invention] According to the present invention, by using an epitaxial layer with a thin carrier concentration, carriers contributing to conduction are always present under the source and drain electrodes, and when no voltage is applied, carriers are present under the gate. A great effect can be obtained when applied to a heterojunction semiconductor device that operates as an E-FET, in which only the channel layer is depleted and carriers accumulate in the channel when voltage is applied.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional structural diagram of a heterojunction semiconductor device according to an embodiment of the present invention applied to a HEMT structure, and FIG. 2 is an energy band structure for electrons directly under the gate electrode.
The figure shows the energy band structure for electrons directly under the source and drain electrodes, and FIG. 4 shows the energy band structure for electrons directly under the gate electrode when gate voltage is applied.
FIG. 5 is a characteristic curve diagram showing the dependence of the source resistance on the buried depth of the source and drain electrodes, and FIG.
FIG. 7 is a characteristic curve diagram showing the drain voltage dependence of the drain current of an FET, and is a cross-sectional structural diagram of a heterojunction semiconductor device according to another embodiment of the present invention applied to a HIGFET structure. Explanation of symbols> 1. Semi-insulating GaAs substrate, 2. Undoped G
aAs layer, 3... undoped AlGaAsN, 4...
Undoped GaAs layer, 5... undoped InGaA
s layer, 6... undoped AlGaAs layer, 7-p (n)
-AlGaAs layer 8・Undoped AlGaAsW! j
, 9-p(n)-GaAs layer, 11.
...Undoped GaAs layer, 12-p (n
)-GaAs layer 13・source electrode, 14・
...Drain electrode, 17. Gate electrode and p(n)-G
aAs layer gap, 18-p(n)-InGa
As layer, 100 Fermi energy 101...Energy band 102・Burning depth dependence curve of source resistance 103 to 10
8. Drain current curve.

Claims (1)

[Claims] 1. In an enhancement type heterojunction field effect transistor, the first semiconductor layer in contact with the gate electrode has a second semiconductor layer in contact with the same side as the gate electrode,
and an enhancement type heterojunction field effect transistor comprising, on the second semiconductor layer, an ohmic junction third semiconductor layer having source and drain electrodes. 2. The enhancement type heterojunction field effect transistor according to claim 1, wherein the second semiconductor layer is an undoped or lightly doped layer. 3. The enhancement type heterojunction field effect transistor according to claim 1, wherein the third semiconductor layer is made of a highly concentrated impurity and is made thick. 4. The source and drain electrodes provided in the third semiconductor layer are semi-buried, and the distance from the source and drain electrodes to the channel in the first semiconductor layer is
4. The enhancement type heterojunction field effect transistor according to claim 1, wherein the enhancement type heterojunction field effect transistor has a thickness of 150 nm or less. 5. The first semiconductor layer is AlGaAs, the second semiconductor layer is GaAs, and the third semiconductor layer is GaAs.
The enhancement type heterojunction field effect transistor according to any one of claims 1 to 4. 6. The enhancement type heterojunction field effect transistor according to any one of claims 1 to 5, wherein the first, second, and third semiconductor layers are all made of p-type semiconductor layers, and the channel layer is made of a p-channel. 7. The enhancement type heterojunction field effect transistor according to any one of claims 1 to 5, wherein the first, second, and third semiconductor layers are all made of n-type semiconductor layers, and the channel layer is made of an n-channel type. 8. In the method for manufacturing an enhancement type heterojunction field effect transistor, when the channel layer is N-channel as the second semiconductor layer on the first semiconductor layer,
When the n^--GaAs layer is P channel, p^
--GaAs is stacked, the second semiconductor layer is etched away only directly under the gate, a gate electrode is formed on the exposed first semiconductor layer, and a third semiconductor layer is formed on the second semiconductor layer. A method for manufacturing an enhancement type heterojunction field effect transistor, which comprises forming a thick cap layer and forming source and drain electrodes in a semi-buried state in the cap layer.