JPH04184935A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the resit trailing and prevent the generation of shoulder part in a gold-plated wiring, by forming an inorganic insulating film between a gold thin film for an electrode and a positive type resist for a gold-plating mask at the time of gold-plating. CONSTITUTION:After a layer insulating film 102 is deposited on an Si substrate 101, a gold thin film 103 is vapor-deposited, on which an Si oxide film 104 is deposited. Positive type resit 105 is applied, and exposure and development are performed. The film 104 is etched, and, in this case, a little side etching is performed. Gold 109 is grown in a resist aperture part by plating treatment. The resist 105 is eliminated. Finally, when the film 103 is eliminated, a gold wiring pattern 110 is formed. Thereby the trailing of resist can be avoided, so that the generation of shoulder part in the pattern 109 is restrained, and the adhesion to a substratum gold thin film and the shape of gold wiring can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming fine gold wiring using a gold plating method.

[Conventional technology]

In recent years, as computer LSIs have become faster and more highly integrated, studies have been conducted to use gold, which has excellent migration resistance, as a fine wiring material.

Among them, in the gold plating method, pattern formation is determined by the resolution of the resist used as a plating mask, so it may be possible to miniaturize the pattern relatively easily.

FIG. 2 shows a method of forming a wiring pattern using a conventional gold plating method. FIG. 2(a) shows a state in which a thin gold film 203, which will become an electrode for gold plating, is sputter-deposited on an interlayer insulating film 202 by about 500 to 1000 people.

Next, a positive resist 204, which will become a plating mask, is spin-coated to a thickness of 1 to 2 μm considering the thickness of the gold to be plated (Fig. 2(b)), and then normal exposure and development are performed as shown in Fig. 2. The position shown in (c) will be obtained.

Next, sodium gold sulfite (A u Na S 04)
After growing gold 206 in a plating solution containing the like (FIG. 2(d)), the resist is removed using a resist stripping solution or oxygen plasma (FIG. 2(e)). Finally, gold thin film 2
When 03 is removed by milling or the like, a gold wiring pattern 207 shown in FIG. 2 ( ) is formed.

[Problem to be solved by the invention]

In this conventional method of forming gold wiring by gold plating, when forming a resist pattern on the gold thin film 203, it is necessary to increase the adhesion of the positive resist to improve the resistance to the plating solution. There was a problem in that it was easy to cause stains. Therefore, when gold plating is performed using the resist pattern as a mask, a constriction occurs at the gold plating interface, and when the wiring width is around 1 μm, the adhesion deteriorates and it easily peels off.When plasma growing or coating an interlayer insulating film on the gold wiring, There is a problem in that a space is created at the constriction, which tends to cause later reliability problems.

[Means to solve the problem]

The method for forming a gold wiring pattern of the present invention is to form an inorganic insulating film between a thin gold film and a positive resist to eliminate the streaking.

A silicon oxide film or a silicon nitride film is used as the inorganic insulating film. At this time, the thickness of the inorganic insulating film is set to a thickness that does not cause scum residue due to multiple interference effects at the resist/inorganic insulating film interface.

For example, in the case of a silicon oxide film, when exposed to G-line (436 nm), approximately 1500 people (or multiples thereof) and I-line (365 nm)
The film thickness is adjusted to approximately 1260 nm (or a multiple thereof) by exposure (silicon nitride film is approximately 0.7 times that of silicon oxide film). At this time, the exposure light intensity at the resist/inorganic insulating film interface increases due to the multiple interference effect, and no resist scum remains.

Furthermore, when etching the inorganic insulating film, if isotropic etching is performed so that there is some side etching, the wiring width at the plating interface can be increased and the adhesion will be improved. Furthermore, if oxygen plasma treatment is performed after side etching the inorganic insulating film, the protrusions at the interface of the inorganic insulating film are removed, thereby improving the shape of the gold-plated wiring and further improving the adhesion.

[Actual example]

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view of an embodiment of the present invention. Figure 1 (a
), after depositing the interlayer insulating film 102, the gold thin film 103 is deposited at a thickness of 500 nm.
This figure shows a state in which a silicon oxide film 104 is deposited by about 1,500 people (in the case of G-line exposure) by plasma chemical vapor deposition or sputtering. Next, a positive resist 105 is spin-coated to a thickness of 1 to 2 μm, and after exposure and development using a stepper (b and g) shown in FIG. 1, the state shown in FIG. The intensity of the exposure light at the oxide film interface increases and the solubility of the positive resist increases, so no scum remains.Furthermore, the silicon is etched by wet etching with a hydrofluoric acid buffer or dry etching with reactive gas plasma such as CF4 or SF. Etch the oxide film 104. At this time, take the wiring width dimension into consideration and add some side etching. For example, in the case of a 1 μm wide wiring, side etching is performed by about 0.2 μm on both sides (see Figure 1).
d)). Furthermore, if the resist protrusions 108 near the silicon oxide film are removed by oxygen plasma treatment before gold plating, the shape of the gold wiring can be further improved (see Fig. 1 (e)).

Figure 1 ('') shows sodium sulfite (A u N a S
This figure shows the cross-sectional structure after gold was grown in the resist openings while keeping the temperature of the plating solution containing O4) at 40 to 60°C.

Next, the resist is removed using a removal solution or oxygen plasma treatment, and the silicon oxide film is further removed using a hydrofluoric acid buffer (FIG. 1(g)). Finally, the gold thin film 103 is removed by milling treatment using Ar ions, etc., as shown in Fig. 1 (h).
A gold wiring pattern 109 shown in is formed.

As described above, when the present invention is applied to the fine gold wiring format, the streaking of the positive resist is eliminated, thereby suppressing the occurrence of constrictions in the gold wiring, and the positive resist is also formed by side etching of the silicon oxide film and oxygen plasma treatment. By removing the convex portions, it is possible to improve the adhesion with the underlying gold thin film and the shape of the gold wiring.

In the previous example, a silicon oxide film was used, but similar effects can be obtained using a silicon nitride film.

However, when a silicon nitride film is used, the film thickness condition under which streaking does not occur at the positive resist/silicon nitride film interface due to multiple buffering effects is about 1260 (and multiples thereof). Also, some side etching is added during dry etching using CF4 or CH2F2. Furthermore, the adhesion and shape of the gold-plated wiring can be further improved by removing resist protrusions near the silicon nitride film interface by oxygen plasma treatment.

〔Effect of the invention〕

As explained above, the present invention eliminates resist warpage by introducing an inorganic insulating film between the gold thin film for electrodes during gold plating and the positive resist of the gold plating mask, and solves the problem of constriction in gold-plated wiring. It has the effect of eliminating

Furthermore, by side etching the inorganic insulating film and removing the protrusions at the bottom of the resist opening by oxygen plasma treatment,
This has the effect of forming gold wiring with excellent adhesion and shape.

[Brief explanation of drawings]

FIG. 1 illustrates an example of the present invention, and FIG. 2 illustrates a conventional example. 101.201...Silicon substrate, 102゜2
02... Interlayer insulating film, 103, 203...
...Gold thin film to serve as an electrode during gold plating, 104...River silicon oxide film, 105,204...Positive resist, 106.205...Resist opening, 1
o7・Old...Side etched part of silicon oxide film, 1o8
- Old: Convex portion of positive resist, 109,206... River: Gold grown by plating process, 110,207... Mark: Gold wiring pattern. Agent Patent Attorney Uchihara Sound (bn (C) Fig. 1 cdn Ce) Fig. l (,?) Fig. 1 (α) (b) <C) Fig. 2 (d) Ce> Fig. 2

Claims (5)

[Claims] (1) In the step of forming a gold wiring pattern using a plating method, a step of forming a gold thin film for a gold plating electrode, a step of forming an inorganic insulating film thereon, a step of applying a positive resist and exposing the wiring pattern, A step of developing, a step of etching the inorganic insulating film using the positive resist as a mask, a step of growing gold in the openings of the resist by a plating method, and after etching the positive resist and the inorganic insulating film, a thin gold film for gold plating electrodes. A method for manufacturing a semiconductor device, comprising a step of removing. (2) The method of manufacturing a semiconductor device according to claim 1, wherein a silicon oxide film or a silicon nitride film is used as the inorganic insulating film. (3) In forming the inorganic insulating film, use a positive resist/
3. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the inorganic insulating film is set so that no scum remains at the interface of the inorganic insulating film due to multiple interference. (4) The method of manufacturing a semiconductor device according to claim 1, 2 or 3, characterized in that in etching the inorganic insulating film, isotropic etching is added to perform a certain amount of side etching. (5) After the side etching of the inorganic insulating film, a convex portion of the positive resist in the positive resist/inorganic insulating film interface region is removed by oxygen plasma treatment.