JPH04183431A - Sample hold pulse generation circuit for electronic endoscope device - Google Patents

Abstract

PURPOSE:To enable a sample hold to be always realized at optimum timing by generating a sample hold pulse while eliminating a modulated signal from an input image signal. CONSTITUTION:The end of a scope section 10 is provided with a solid state image pickup element (CCD image pickup element) and a CCD output signal is branched to two passages after a transformer 21. The first passage is provided with a narrow band high gain amplifier 22 tuned to 7.15MHz, and a modulated signal is removed from a CCD output signal to be entered, thereby obtaining a 7.15MHz signal. This signal is negative and, therefore, reversed for use as a sample hold pulse. On the other hand, a CCD output signal after the second passage is applied to the source of a field effective transistor(FET) 27. The gate of the aforesaid transistor is supplied with a sample hold pulse from the first passage. During the sample period when the pulse is being supplied, the gate is turned on, while the gate is turned off in the hold period. The CCD output signal passing the FET 27 during the sample period is charged to a capacitor 28, and the terminal voltage thereof is read out during the hold period.

Description

[Detailed Description of the Invention] : Industrial Application Field] The present invention relates to a sample-hold pulse generation circuit for an electronic endoscope device, and particularly relates to a sample-hold pulse generation circuit for an electronic endoscope device, and particularly to a sample-hold pulse generation circuit for generating a video signal from a solid-state image sensor at the tip of a scope section and a sample-hold pulse generation circuit in a processor. The present invention relates to a sample-and-hold pulse generation circuit for an electronic endoscope device that compensates for the timing relationship with pulses.

Conventional technology] Ordinary broadcast or commercial cameras use a solid-state image sensor (
The CCD image sensor) is mounted 2.3 inches from the processor. This allows the phase relationship between the sample-and-hold pulse for the sample-and-hold circuit and the video signal to be set to be suitable for optimal sampling of the video signal during the entire life of the camera.

On the other hand, inspections using electronic endoscope devices are performed using various videoscopes. In these videoscopes, the CCD imager is arranged at the end of a coaxial cable that varies in length and diameter depending on the inspection procedure being performed.

[Problems to Be Solved] By the way, as the length, diameter, rolled cable, and manufacturing method of videoscope cables change, the electrical characteristics of each videoscope also differ from each other.

That is, the CCD image sensor is driven by a driving pulse applied from a CCD driver in the processor via a cable, and outputs a video signal corresponding to the incident light to the processor via the cable, while the processor After the video signal is sampled and held through a sample and hold circuit, predetermined signal processing is performed.The sample and hold pulse that determines the timing of this sample and hold is applied from a timing generation circuit that also applies timing pulses to the CCD driver, etc. There is.

Therefore, if the length of the cable changes due to replacement of the videoscope, the input point of the peak value of the video signal applied from the CCD image sensor and the timing of sampling and holding this peak value may deviate.

The present invention was made in view of the second situation, and it is possible to generate sample and hold pulses so that video signals input from various videoscopes can always be sampled and held at optimal timing. An object of the present invention is to provide a sample and hold pulse generation circuit for an electronic endoscope device.

Means for Solving the Problem 2 In order to achieve the above-mentioned object, the present invention includes installing a solid-state image sensor at the tip of a scope section, outputting drive pulses from a processor to the solid-state image sensor via a cable, An electronic circuit that inputs the video signal read out from the solid-state image sensor to the sample-and-hold circuit of the processor via a cable, samples and holds the video signal in synchronization with a sample-and-hold pulse, and then performs predetermined signal processing. The endoscope apparatus is characterized in that it includes a sample-and-hold pulse generating circuit that removes modulation from the input video signal to generate a sample-and-hold pulse, and outputs this to the sample-and-hold circuit.

[Effect]

According to the present invention, a sample-and-hold pulse for sample-holding a video signal is generated from an input video signal. That is, by using a narrow-band high-gain amplifier or the like that is tuned to the successive cycles of the video signal, a sample-and-hold pulse is generated by removing modulation from the video signal read out from the solid-state image sensor, and this is used as a sample hold pulse in the processor. I am trying to output it to the hold circuit.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a sample and hold pulse generation circuit for an electronic endoscope apparatus according to the present invention will be described in detail below with reference to the accompanying drawings.

As shown in FIG. 2, the electronic endoscope device is composed of an electronic endoscope scope section 10 and a processor 20. The scope section 10 is replaceable with respect to the processor 20, and the endoscope It will be replaced with one more suitable for the purpose of the inspection.

FIG. 1 is a circuit diagram of the main part of the processor 20, which includes a sample and hold pulse generation circuit according to the present invention.

A solid-state image sensor (CCD image sensor) (not shown) is disposed at the tip of the scope section 10 (FIG. 2).
The charges accumulated in each pixel of the CCD image sensor are sequentially read out by driving pulses (two horizontal and vertical scanning pulses) applied from the driver, and are applied to the processor 20 as a CCD output signal. Here, the 20 CCD output signal is a signal synchronized with the frequency (for example, 7.15 MHz) of the horizontal scanning pulse modulated by the accumulated charge of each pixel, as shown in FIG.

Now, as shown in FIG. 1, the CCD output signal passes through a transformer 21 and is then branched into two paths.

The first path is provided with a narrow band high gain amplifier 22 synchronized to 7.1'5M7. This narrow band high gain amplifier 22 removes modulation from the input CCD output signal, thereby obtaining a 7.15 MHz signal. Note that since the CCD output signal is a negative signal, 7
．． The signal of 15M) tz is inverted and used as a sample and hold pulse (FIG. 4), as will be described later.

On the other hand, the second path is provided with an amplifier 23, a delay circuit 24, a clamp circuit 25, and a buffer amplifier 26. Amplifier 23 amplifies the CCD output signal to the level required for optimal sampling, and delay circuit 24 adds a delay equal to the first path delay. In addition, the clamp circuit 25
pedestally clamps the CCD output signal using a clamp pulse.

The CCD output signal through the second path is applied to the source of a field effect transistor (FET) 27. On the other hand, a sample and hold pulse is applied to the gate of the FET 27 from the first path.

This FET 27 becomes ○N during the sample period when the sample hold pulse is added, and becomes OFF during the hold period until the next sample hold pulse is applied. Then, the C CjD output signal that has passed through the +::FET 27 during the sample period is charged into the capacitor 28, and the terminal voltage of the capacitor 28 is read out during the hold period.

The CCD output signal sampled and held in this manner is passed through a buffer amplifier 29 to a low-pass filter 30.
, where undesired high frequency components are removed, and then amplified by amplifier 31 for subsequent processing.

〔Effect of the invention〕

As explained above, according to the sample-and-hold pulse generation circuit of the electronic endoscope device according to the present invention, the modulation component is removed from the CCD output signal to generate the sample-and-hold pulse. Sample and hold pulses can be generated at appropriate timing without being affected.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a main part of a processor including a sample-hold pulse generation circuit of an electronic endoscope device according to the present invention, and FIG.
The figure is a schematic diagram of the scope section and processor that make up the electronic endoscope device, and Figures 3 and 4 are respectively similar to Figure 1!
! FIG. 2 is a signal waveform diagram used for DESCRIPTION OF SYMBOLS 10... Scope part, 20... Processor, 22... Narrowband high gain amplifier, 24... Delay circuit, 26.29... Buffer amplifier, 27... Field effect transistor (FET) 28 ...
capacitor.

Claims (1)

[Claims] A solid-state image sensor is provided at the tip of the scope section, a drive pulse is output from a processor to the solid-state image sensor via a cable, and a video signal read out from the solid-state image sensor is sent via the cable. In an electronic endoscope apparatus that inputs the video signal to a sample hold circuit of the processor, samples and holds the video signal in synchronization with a sample hold pulse, and then performs predetermined signal processing, wherein modulation is removed from the input video signal. A sample and hold pulse generation circuit for an electronic endoscope apparatus, comprising a sample and hold pulse generation circuit that generates a sample and hold pulse and outputs it to the sample and hold circuit.