JPH04183078A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To obtain proportional relation between the quantity of light and an output, to enable unbroken reading and to eliminate afterimages by using a lateral electrostatic dielectric transistor as a photoelectric converting element and reading this transistor according to a capacity load type source follower circuit system. CONSTITUTION:Respective photoelectric converting elements 1-11, 1-12, 1-13...1-31, 1-32 and 1-33 are respectively MOS gate structure lateral electrostatic dielectric transistors (MOS SIT) constituting a photoelectric conversion part, respective source terminals are respectively connected to source lines 2-1-2-3 in common for each longitudinal line, and respective gates are respectively connected to gate lines 3-1-3-3 in common for each lateral line. Then, reading is executed according to the capacity load type source follower circuit system. Thus, the proportional relation is established between the quantity of light and the output, there is no afterimage, and unbroken reading is enabled.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an surrounding imaging device, and in particular, by using a lateral electrostatic induction transistor as an imaging element and using a capacitively loaded source follower circuit for reading, Output linearity is good! ! The present invention relates to a nondestructive readout type imaging device that has no image and has low fixed pattern noise.

[Prior art] Conventionally, a lateral static induction transistor with a MOS gate structure (
An image sensor constructed using a MOS-SIT (hereinafter referred to as MOS-SIT) as a photoelectric conversion element is published in Journal of the Television Society Vol. 1.41, No.

11, pp. 1047-1053 (1987). In this image sensor, the gate, source, and drain voltages at the time of reading are fixed, and the source current is used as an output and subjected to I-V conversion by an amplifier at a subsequent stage. In such an image sensor, by using MOS-3IT as a photoelectric conversion element, there is a feature that there is little afterimage and only non-destructive readout is possible.

In addition, it has been proposed to use a capacitively loaded source follower circuit system or a capacitively loaded emitter follower circuit system for reading, and to differentially amplify the output read out before the accumulated charge is added and at the reset point f&. There is. For example, I
EEE Trans, V.

1, ED-35, No, 5. pp, 646-652 (1
In May 1988), an example of a series of capacitively loaded source followers using junction field effect transistors (JPETs) as photoelectric conversion elements was presented, published in Mata magazine ``Eizo Information'', V o I, 21. No, 10. PP, 4
1-46 (May 1989) shows an example of a capacitively loaded emitter follower readout using a bipolar transistor as a photoelectric conversion element.

In this way, by using a capacitively loaded source follower or emitter follower circuit system for reading, the amount of charge accumulated in the gate or base is proportional to the voltage generated at the gate or base due to this charge. It has the advantage that there is a proportional relationship between the amount of light and the output of the source follower or emitter follower. Furthermore, storage N
Fixed pattern noise (hereinafter referred to as FPN) that occurs due to variations in threshold voltage VT in device characteristics can be eliminated by reading the charge twice before and after resetting, and differentially amplifying it in the amplifier at the subsequent stage. It has the advantage of being removable.

[Problem to be solved by the invention] However, as in the first conventional example mentioned above, MOS-
Even if SIT is used as a photoelectric conversion element, when the source outputs current and the subsequent amplifier performs I-V conversion, the amount of charge accumulated in the gate part due to photoelectric conversion is not proportional to the source current value. There was a disadvantage that a proportional relationship between the amount of light and the output could not be obtained. Additionally, since MOS-3IT is sensitive to slight variations in device characteristics, device size, impurity concentration, etc., there is also the problem of large FPN caused by variations in device characteristics, such as threshold voltage VT and mutual conductance Gm. there were.

In addition, in a method in which a capacitive load type source follower or emitter follower circuit system is used for reading and the output read out before and after resetting the stored charge is differentially amplified, if the charging conversion element is a JFET or a bipolar transistor, However, there was a problem in that the reset operation of the accumulated charge was difficult and an afterimage occurred. This is because the method of forward biasing the PN junction between the gate and source or between the base and emitter and recombining the PN junction at the time of reset causes the gate potential or base potential to change even if the applied forward bias voltage is constant. This is because the effective gate-source voltage or base-emitter voltage is different because the potential changes depending on the amount of light, and the gate or base potential after reset also remains dependent on the amount of light.

Furthermore, if the photoelectric conversion element is a bipolar transistor, the base and emitter are forward-biased shallowly during readout, but at this time some of the accumulated charge is lost due to recombination, so in a strict sense, it is not possible to perform non-destructive readout. Not satisfied,
Therefore, it has been inconvenient that it cannot be used in applications where reading operations, that is, non-destructive reading, are repeatedly performed.

In view of the above-mentioned problems in conventional devices, an object of the present invention is to provide a solid-state imaging system that has a proportional relationship between light amount and output, has no afterimages, enables non-destructive readout, and has minimal fixed pattern noise. The goal is to provide equipment.

Means for Solving Double Charge] In order to solve the above-mentioned problems, the present invention provides a photoelectric conversion element with a horizontal W type. It is characterized in that it uses an electric induction transistor and that readout is performed by a capacitive load type source follower circuit system.

Further, in the above system, reading may be performed before and after resetting the charges accumulated in the gate portion, and the video signal may be obtained based on the difference between the readout outputs.

Function] As described above, in the solid-state imaging device according to the present invention,
Since reading from the photoelectric conversion element is performed using a capacitively loaded source follower circuit system, a perfect proportional relationship between the amount of light and the output can be obtained. In addition, the source follower output is not affected by the value of mutual contactasis Gm in the device characteristics, so fixed pattern noise due to variations in Gm does not occur.Furthermore, the voltage applied between the gate and source at the time of reading is For example, a PN junction formed on the surface of a semiconductor such as silicon, formed by a P-type inversion layer and an N-type semiconductor layer, can be set within a range where a reverse bias state is achieved, so non-destructive readout is possible. It becomes possible.

In addition, a lateral electrostatic induction transistor (MO) is used as a photoelectric conversion element.
S-3IT), the gate and
By applying an appropriate voltage between the sources, the stored M charge is emptied, so that the reset operation is complete and there is no afterimage. Furthermore, by performing source follower readout before and after reset and differentially amplifying both outputs, FPN caused by variations in threshold voltage VT can be reduced.
is removed.

[Examples] Examples of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit configuration of a solid-state imaging device such as an image sensor according to an embodiment of the present invention. The figure shows a case where photoelectric conversion elements are arranged in three rows and three columns.

In FIG. 1, each photoelectric conversion element 1-11.1-12.
1-13. . . , 1-31.1-32.1-33 are MOS/SITs constituting a photoelectric conversion section, and each source terminal is commonly connected to a source line 2'-1,
2-2 and 2-3, respectively, and each gate is connected to a gate line 3-1.3-2.3-3 in common in one horizontal row. Load capacity (CTs) 4-1.4-
2.4-3 and load capacity (C1N) 5-1.5-2.
5-3 is a load capacitor for reading out the source follower, the load capacitor C1S outputs the output just before reset, that is, after performing open photoelectric conversion for a - constant accumulation time, and the load capacitor 01N outputs the output immediately after reset. It is for reading. Note that immediately after reset, the opening during accumulation is considered to be small and can be ignored.

The vertical running circuit 8 (VSR) 6 generates gate pulses φ61 to "G3" for each photoelectric conversion element.

Further, the horizontal scanning circuit (HSR) 7 has the load capacitance CT
Switching transistor 1 for sequentially transferring charges stored in S and 01N to horizontal readout lines 8 and 9
8-1.19-1.18-2.19-2.18-3.1
This is a circuit for generating gate pulses φH1 to φH3 of 9-3. Capacity (CH3) 10 and Capacity (CHN)
11 is the parasitic capacitance of each horizontal readout line 8.9.

In addition, the gate pulse (φ) 12 and the gate pulse (φTON) 13 are each MOS-3
Switching transistors 20-1.20-2.20-3 connected to IT and load capacitances C13 and C1Nth, respectively
and the pulses applied to the gates of 21-1.21-2.21-3. In addition, the gate pulse (φR8, n1
4 is a reset transistor 22-1.22-2.22-3 for the vertical source line 2-1.2-2.2-3.
is the pulse applied to the gate of , and the gate pulse (φ
R3H)15 is a pulse applied to the gate of the reset transistor 23-1.23-2 of the horizontal succession line 8.9. In addition, output terminals (VO8 and voN) 1
6 and 17 output successive signals before and after resetting the SIT, respectively, which are differentially amplified by an amplifier (not shown) in the subsequent stage to obtain a final video signal.

FIG. 2 is a waveform diagram showing the timing of each pulse that drives the solid-state imaging device in FIG.
The operation of the device shown in the figure will be explained. Note that the photoelectric conversion elements 1-21.1-22.1-2 in the second row in the apparatus shown in FIG.
The operation will be explained by focusing on 3.

Gate pulses φ61 to φ6 applied to each photoelectric conversion element
3 corresponds to each operation of storage, readout, and reset.
It has a voltage value of level (VGl''G2.VO3).

When this level is VGl, for example, when it is -T1, the photoelectric conversion element is in an off state, and an accumulation operation is performed in which charges generated according to the amount of incident light are accumulated on the surface of the semiconductor substrate facing the gate part. .

At time t, = T2, gate pulse φ, φ:TGS
Since TG N and φR3V are at high level, each switching transistor 20-1.20-2.20-3.21
-1,21 2.21-3.22-122-2.22-
3 are all turned on, and each load capacitance CTs and CTN is discharged through each source line 2-1.2-2.2-3 and reset to the ground level. That is, CT3,
01N and source line reset operation is performed.

At time t=T3, the gate pulse φRSV is at a low level and each source line 2-1.2-2.2-3 becomes floating. Furthermore, since the gate pulse φTGS is at a high level, each switching transistor 20-1, 20-
2.20-3 turns on, source line 2-1.2'
-2, 2-3 and load capacitance 4-1.4-2.4-3 are connected to each other. At the same time, the gate pulse φ62 or V output from the vertical scanning circuit 6 for the photoelectric conversion element.
Since the level is O2, the photoelectric conversion element 1-21.1-
22.1-23 is in the on state, and the source follower operation changes the output depending on the amount of light, that is, the accumulated N charge, or the load capacitance (
CTs) 4-1.4-2.4-3. That is, a read operation is performed.

The photoelectric conversion elements of other pixels are at the level of gate pulse φ67 and φG3 or vGl, so they are in the off state, and each continues the accumulation operation without affecting the output. In this case, the voltage CTS generated in the load capacitance CTS is expressed by the following equation.

Qoh I Cl + α + β x ...... (1) In this equation, VT is the photoelectric conversion element (MOS・5IT
), the pinch-off voltage QDh is the amount of charge generated by photoelectric conversion and accumulated in the gate portion, and is proportional to the amount of light. Further, C is the gate oxide film capacitance of the MOS-SOX IT, and α and β are constants determined by the substrate bias voltage dependence and source-train voltage dependence of the pinch-off voltage VT of the MOS-3IT, respectively. In addition, the level of VO2 is vG2≧
Set it to be V1.

In such a read operation, if the amount of accumulated charge Qph accumulated in the gate part is within a certain range, that is, less than the saturation charge amount Qsa, then the read operation will cause no change in the accumulated charge. Since there is no influence, non-destructive reading is possible.

As mentioned before, in MOS-3IT, the PN junction between the P-type inversion layer formed on the semiconductor substrate below the gate and the N-type semiconductor layer (channel part) is forward biased. This is because the read operation can be performed without any bias, that is, while the reverse bias state is maintained, so that the stored M charges are not recombined or injected into the P-type substrate. However, if the accumulated charge amount Qp1 exceeds the saturated charge amount Q3,1,
Since the excess amount disappears in the readout operation described above, when the amount of light corresponding to the saturated charge amount Qsat is exceeded, the output becomes saturated l-
It comes.

At time t=T, since the gate pulse φR3V is a high level, each source line 2-1.2-2゜2-3 is connected to the ground, and the gate pulse φG2 is VO2
photoelectric conversion element 1-21.1-22
．． The charges accumulated in 1-23 disappear due to recombination or injection into the semiconductor substrate, resulting in an empty state. That is, a reset operation is performed. Note that the level of VO3 is set to a relatively high value so that the charge stored in the gate portion of the photoelectric conversion element is emptied. In this way, MOS as a photoelectric conversion element
- In solid-state imaging devices using SIT, by setting the voltage between the gate and source above a certain value, a complete reset operation can be performed, and therefore the problem of afterimages does not occur. During the reset operation,
The other pixels are in the off state and continue the accumulation operation.

At time t=Ts, the gate pulse φRSV becomes low level, so each source line 2-1.2-2°2-3
is isolated from the ground and the gate pulse φTGN is at a high level, so the load capacitance (CTN) is 51.5 2.5
3, respectively. In addition, gate pulse φG2
or VO2 level, and the photoelectric conversion element 1-21.1-22.1-23 immediately after being reset turns on again, and the accumulated charge amount Q or the output of the almost zero state or h is applied to the capacitor CTN. It can be stored. That is, a dark output read operation is performed.

In this case as well, the other pixels that are not selected continue their accumulation operation in the off state and do not affect the output, so the voltage ■c18 generated in the capacitor CTN is
, ,=O, and is expressed by the following equation.

In this way, the load capacity (C18) 4-1, 4-
2.4-3 and other load capacities (C1N) U-1゜5-
2. The charge accumulated in -1i-3 is then outputted from the horizontal scanning circuit 7 as a pulse φ φ φH1' H
At the timing of 2' 13, the horizontal read lines 8 and 9 are sequentially read out.
are respectively transferred to the output V. , and VoN are obtained. Note that the gate pulse φR3H is applied to the horizontal readout line 8.
．． This is a gate pulse for switching transistors 23-1 and 23-2 for resetting the charge of 9.

In such an operation, CTS""TN" CT,c
=c If =c, ■ and V. , is expressed by the following H5HN Has formula.

phI CT ・ (□) ・・・・・・(3)C■＋C
H v −<VO2−v ding ) () N y ・ (□) ・・・・・・ (4
) C, 10CH Output ■ obtained in this way. S and V. N is an output V that is proportional to the amount of light, which is subjected to subtraction processing in a circuit such as a differential amplifier at the subsequent stage (not shown). , 1 is obtained.

That is, ”out =”as-■0N Qph I 0th = □(□璽□) Cl±α+β CT 1,000H O× (5) As shown in equation (w), the output V . S and V. By taking the difference in N, it is possible to obtain an output that is free from the influence of variations in the pinch-off voltage VT of the photoelectric conversion element. Furthermore, since source follower reading is used, the term of mutual conductance Gl does not appear in the output, and the influence of variations in Gi is also eliminated.

In this way, by performing capacitive load type source follower reading before and after reset, it is possible to obtain an output that is not affected by variations in pinch-off voltage VT or mutual contactance Gn, and therefore, fixed pattern noise can be minimized. Become.

Note that FIGS. 3 and 4 are a plan view and a cross-sectional view, respectively, showing an example of the structure of a MOS-3IT that can be used as a photoelectric conversion element of a solid-state imaging device as shown in FIG. MOS-3IT shown in these figures
is an N-type source region 33 formed on the top of an N-type semiconductor layer 32 such as an N-type epitaxial layer formed on a P-type semiconductor substrate 31, and an N-type drain region surrounding this N-type source region 33. Further, a gate electrode 36 made of polycrystalline silicon or the like is formed on the N-type semiconductor layer 32 between the N-type source region 33 and the N-type drain region 34 with an insulating film 35 interposed therebetween. . Further, a large number of such SITs are formed in a matrix on a semiconductor substrate, and the N-type source regions 33 of each SIT in a column are connected to each other by an aluminum wiring 37 for a source line. Also, the gates and poles 36 of the SITs in the same row are connected to each other by a gate line 38. Note that the semiconductor layers and regions in FIGS. 3 and 4 are of opposite conductivity type, that is, P type is changed to N type, N type is changed to P type,
It is also possible to do so.

[Effects of the Invention] As described above, according to the present invention, a lateral electrostatic induction transistor is used as a photoelectric conversion element, and this is read out using a capacitively loaded source follower circuit system, so that there is no proportional relationship between the amount of light and the output. This enables continuous non-destructive printing and eliminates afterimages. In addition, readout using the capacitive load type source follower method is performed before and after resetting/resetting the photoelectric conversion element, and both readout outputs are differentially amplified, eliminating the influence of variations in the photoelectric conversion element and minimizing fixed pattern noise. Become.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing the circuit configuration of a solid-state imaging device according to an embodiment of the present invention in the case where photoelectric conversion elements are arranged in three rows and three columns, and FIG. FIG. 3 is a waveform diagram showing the pulse timing and voltage relationship of each part of the solid-state imaging device shown in FIG.
The figure is a cross-sectional view of the photoelectric conversion element in FIG. 3 taken along line AA'. 1-11.1-12.1-13. ..., 1-31゜1
-32.1-33: Photoelectric conversion element, 2-1.2-2.2-3: Source line, 3-1.
3-2. 3-3 Nigate Line, 4-1.5-1.
..., 4-3.5-3: Load capacitance, 6: Vertical scanning circuit, 7. Horizontal scanning circuit, 8.9: Horizontal readout line. 10.11: Parasitic capacitance of horizontal readout line, 12.13
．． 14.15: Gate pulse, 16.17: Output terminal, 18-1.18-2.18-3. ..., 22-1゜2
2-2.22-3.23-1.23-2 Niswitching transistor, 31: P-type semiconductor substrate, 32: N-type semiconductor layer, 33:
N-type source region, 34: N-type drain region, 35: insulating film, 36: gate electrode, 37: source line, 38 negative gate line.

Claims (1)

[Scope of Claims] 1. A plurality of lateral static induction transistors arranged in a matrix and each accumulating charge in its gate portion according to incident light; a load capacitor coupled to the source circuit of the lateral static induction transistor selected by the selection gate means and charged by a signal corresponding to the amount of charge accumulated in the gate portion; , A solid-state imaging device is characterized in that it obtains a video signal based on the charge of the load capacitor. 2. A plurality of lateral electrostatic induction transistors arranged in a matrix and each accumulating charge in its gate portion according to incident light, and a selection gate means for selecting a desired one for reading out of the plurality of lateral induction transistors. and first and second transistors coupled to the source circuit of the lateral static induction transistor selected by the selection gate means and charged according to the potential of the source circuit before and after resetting the charge accumulated in the gate section, respectively. A solid-state imaging device, comprising: a second load capacitor; and obtaining a video signal based on a difference between signals corresponding to charges of the first and second load capacitors. 3. The lateral static induction transistor includes a low concentration semiconductor layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type, and a high concentration second conductivity type semiconductor layer formed near the surface of this semiconductor layer. 2. A semiconductor device comprising: a source region and a drain region of a second conductivity type; and a gate electrode formed on the semiconductor layer of the second conductivity type between the source region and the drain region with an insulating film interposed therebetween. Or the solid-state imaging device according to 2.