JPH04182988A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To allow the effective relief of defective bits without increasing access time with reduced electric power consumption by dividing memory cell arrays to plural blocks and adding a spare memory block of the same capacity as the capacity of these blocks. CONSTITUTION:Reading out/writing circuits 5a to 5h corresponding to the normal memory blocks and a reading out/writing circuit 5R corresponding to the spare memory block 1R are made of the same constitution. In addition, a Y system decoder-driver 3 is formed to such a shape which handles the changeover signal from a defect block changeover signal generating circuit 4 as the signal equal to an address signal and generates the selection signal for the memory blocks. Then, the critical path to determine the access time of the normal memory blocks 1a to 1h and the spare memory block 1R are exactly the same. The increase in the access time by the adoption of the redundancy constitution is obviated in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory technology and a technology that is particularly effective when applied to a so-called redundant configuration in a semiconductor memory.
For example, the present invention relates to a technique effective for use in a multi-bit parallel output type static RAM.

[Prior Art] In a semiconductor memory, if even one bit of a memory cell in a memory cell array is defective, the entire device becomes defective. Therefore, as the memory capacity increases, that is, the number of memory cells increases, the chip area increases, and the yield of semiconductor memories due to bit defects in the memory cells is significantly reduced.

Therefore, a redundant configuration is implemented in which a spare memory column is provided in advance separately from the regular memory cell array, and a memory column containing a defective memory cell (hereinafter referred to as a defective bit) is replaced with the spare memory column.

However, the conventional general redundant configuration has the drawback of slowing down the operating speed, that is, the access time.

However, due to the demand for higher speed systems using semiconductor memories, there is a demand for an increase in the operating speed of semiconductor memories as well as an increase in storage capacity.

In order to meet such demands, for example,
A redundant configuration technique has also been proposed that allows defective bits to be repaired without reducing operating speed, such as the invention described in No. 198. That is, in the prior invention, the memory cell array 10 is divided into eight blocks 1 as shown in FIG.
In addition to dividing into blocks 0a to 10h, a spare memory block 101 is added separately, and multiplexers lla and llb are provided as selection circuits on the decoder side. 2 decoder 18, the multiplexer l
1a and llb are switched and the entire block is replaced with the spare memory block 10i.

[Problems to be Solved by the Invention] Although the above-mentioned conventional technology can repair defective bits without significantly reducing the operating speed, there are problems as described below.

First, one column is selected from the divided blocks loa to 10h by the Y decoder 14,
Since multiplexers lla and llb select one block for a read or write operation, a delay due to passage through multiplexer lla or llb is inevitably added.

Second, there is a problem in that power consumption is high because all of the divided blocks operate.

Furthermore, since there is no consideration given to parallel read and write operations in units of multiple bits, in order to enable operations in units of multiple bits, the number of multiplexers must be multiplied by the number of bits, increasing the chip size. There is also the problem of letting it happen.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory redundancy configuration technique that consumes less power and can effectively repair defective bits without increasing access time.

Another object of the present invention is to perform parallel reading in units of multiple bits;
An object of the present invention is to provide a redundant configuration technique that does not significantly increase the chip size even when configuring a writable semiconductor memory.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In other words, the memory cell array is divided into multiple blocks, a spare memory block with the same capacity as this block is added, multiple bits handled simultaneously can be read or written from the same block, and any defective bits in any block are If there is a defective block, the decoder is configured to switch the entire block as a spare memory block and drive only the sense amplifier corresponding to the selected block, and the defective block switching signal generating means is equipped with an externally programmable element. It is designed to provide a.

[Operation] According to the above-mentioned means, since multiple bits handled simultaneously are read or written from the same block, it is possible to activate only the selected block and prevent current from flowing to non-selected blocks. , this can significantly reduce power consumption. In addition, the defective block switching signal can be determined before the address signal is input to the decoder, and the switching signal is directly input to the decoder, eliminating the need for a selection circuit such as a multiplexer, increasing access time. Not at all.

Furthermore, since all of the multiple bits that are input and output in parallel are read or written from one block, the configuration of the decoder that generates the signal to switch a block with defective bits to a spare block is simplified, and the configuration of the multiplexer is simplified. Since such a selection circuit is not required, an increase in chip size can be suppressed even when a memory that operates in units of multiple bits is configured.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to a static RAM.

In FIG. 1, reference numeral 1 denotes a memory cell array having a storage capacity of 64 bits. In this embodiment, the memory cell array 1 is divided into eight blocks la to 1h, each block 1a to 1h having a memory capacity of 64 bits. It is organized into 8 bits in 256 rows and 32 columns. And the above blocks 1a~
In addition to 1h, a spare memory block IR of the same size and having a configuration of 256 rows and 32 columns is provided adjacently.

Further, in FIG. 1, 2 is an X-system decoder/driver, which receives 8-bit X address signals xO to x7.
25 commonly arranged in each block la to lh and IR
Select any one of the six word lines.

3 is a Y-system decoder/driver, which receives the 3-bit Y address signal YO-Y2 and a signal from the defective block switching signal generation circuit 4, and selects any one block from the nine blocks 1a to IR. do.

The defective block switching signal generation circuit 4 includes a programmable element such as a fuse, and amplifies a signal generated according to the state of the element to a predetermined signal level and supplies it to the Y-system decoder/driver 3. , which prohibits selection of defective blocks and provides a signal to select spare memory block IR.

5a to 5R are read/write circuits each having a write amplifier for writing to each block 1a to IR and a sense amplifier for reading. This read/write circuit 5
A to 5R are composed of 32 write amplifiers and 32 sense amplifiers, and each block can independently perform 32-bit read or write operations. Further, one of these read or write circuits 5a to 5R is activated only when a selection signal from the Y-system decoder/driver 3 is input.

On the other hand, 6 is a data input/output circuit which supplies 32-bit input data D, -D l + to the write amplifier or outputs data read out from the memory cell array 1 by the sense amplifier.

Further, 7 is a read/write control signal W supplied from the outside.
This is an internal control circuit that forms control signals for the data input/output circuit 6 and read/write circuits 5a to 5R based on E and chip selection signal O8.

The above memory is configured such that only one read/write circuit 5a to 5R selected by the Y-system decoder/driver 3 and the corresponding blocks 1a to IR are activated, and the remaining eight blocks are supplied with a read current. The structure is such that no current or write current is allowed to flow. This significantly reduces power consumption compared to a method in which 32 bits are read from each block, selected by a multiplexer, and output.

Further, in the above embodiment, the read/write circuits 5a to 5h corresponding to the regular memory block and the read/write circuit 5R corresponding to the spare memory block IR have the same configuration, and the Y-system decoder/driver 3 is defective. Since the switching signal from the block switching signal generation circuit 4 is treated as a signal equivalent to an address signal and generates a memory block selection signal, access to the regular memory blocks 1a to 1h and the spare memory block IR is facilitated. The critbus, which determines the time, will be exactly the same. Therefore, there is no increase in access time due to the adoption of the redundant configuration.

FIG. 2 shows an example of the configuration of the Y-system decoder/driver 3 and the defective block switching signal generation circuit 4.

Of these, the Y system decoder/driver 3 receives external Y
Address buffer 31a receives address signals YO to ¥2 and generates complementary address signals.

31b, 31c and 3-man powered NOR gates 32a to 32h
a decoder section 32 consisting of a decoder section 32, and two-man power NOR gates 33a to 33h and 331 whose input signals are the decoded signal thereof and a complementary switching signal from the defective block switching generation circuit 4.
A redundant switching unit 33 consisting of ~33p and a NOR gate 33
Regular memory blocks 18 to 1 receive outputs from a to 33h.
level converters/drivers 34a to 34h that form selection signals Ya to Yh, and the NOR gates 33a to 3
3h, and a level converter/driver 34R that receives the output and forms a selection signal YR for the spare memory block IR. ing.

On the other hand, the defective block switching signal generation circuit 4 includes programmable level generation means 41a to 41h, and buffer amplifiers 42a to 42h that receive these signals and generate complementary switching signals co, co to C7, C7. ing.

FIG. 3 shows a level generating means 41 and a buffer amplifier 42.
A specific example of the configuration is shown.

That is, the level generating means 41 has the power supply voltage terminal Vcc,
Resistor R1, fuse F, and resistor R2 are connected in series between Vee and F, and when fuse F is not cut, a signal of "1" level (Vcc) is generated, and a large current is caused to flow by applying a probe to terminal P. It is configured to generate a "0" level (Vee) signal when the fuse F is cut.

The buffer amplifier 42 is constituted by a differential amplifier consisting of a differential amplification stage DA having transistors Ql and Q2 and emitter followers EFl and EF2. Upon receiving the signal, complementary signals Ci and Ci are generated. These complementary signals Ci, Ci
The level of is set in accordance with the signal level of the NOR gates 33a to 33p in the Y-system decoder/driver 3.

Of these complementary signals Ci and Ci, the inverted signal C1 is the NOR gate 33a to 33h for normal memory block selection.
The non-inverted signal C1 is input to NOR gates 331 to 33p for selecting spare memory blocks.

When defect relief is not performed, that is, when the fuse is not cut, the output of the level generation circuit 41 is at the "1" level, so the five inverted signals of the buffer amplifier 42 are at the rQJ level, and the non-inverted signal C is at the "1" level. It is. Therefore, the NOR gate 33a for normal memory block selection
A signal of r□ level is input to 33h, and the outputs of NOR gates 33a to 33h follow the inputs from Y-system decoder/driver OR gates 32a to 32h. That is,
If the output of any one of the OR gates 32a to 32h is "O", the output of the corresponding NOR gate 33a to 33h is "0".
1", and one block corresponding to the NOR gate 33 with the output "1" is selected. On the other hand, at this time, the NOR gates 331 to 33p for selecting spare memory blocks have
Since a "1" level signal is input, the output of the OR gate 34 is
It is fixed at the "0" level regardless of the input from 32h. That is, spare memory block lR is not selected.

On the other hand, when performing defect relief, the fuse of the level generation circuit 41 corresponding to the defective block is cut.
The output becomes "0" level. Therefore, the inverted signal σ of the buffer amplifier 42 is "1", and the non-inverted signal C is "0".
It becomes a novel. In other words, the normal memory block selection NO.
Since a "1" level signal is input to the gate corresponding to the defective block among the R gates 33a to 33R, the normal memory block is is not selected. At the same time, since an "O" level signal is input to the redundant selection NOR gates 33i or 33i to 33p that are paired with the defective regular memory block selection NOR gates 33a to 33h, the A spare memory block selection signal is formed according to inputs from R gates 32a to 32h.

FIG. 4 shows a more specific example of the normal memory block selection side circuit of the Y-system decoder/driver 3.

In other words, the Y-system address signal YO− supplied from the outside
The input buffers 31a to 31C receiving Y2 are composed of ECL gates, and the emitter follower transistors Qll to Q16 forming the output stage thereof are multi-emitter transistors. Ql 3. Ql 5
Each emitter terminal of transistors Q12. is connected to a common constant current source CCl-CC4. Q14. Each emitter of Q16 is connected to common constant current sources CC5 to CC8 to form a wired logic. Then, the output signal of each wired logic is supplied to one input terminal of two-man power NOR gates 33a to 33h each consisting of an ECL gate, and decoded signals a, τ to h, and π are formed. The other input terminals of the NOR gates 33a to 33h receive the switching signal Go-C from the defective block switching signal generation circuit 4.
7 is input. Figure 4 shows the two-man powered NOR gate 3.
Examples of configurations 3a to 33h are representatively shown for 33a.

FIG. 5 shows a specific example of a circuit on the selection side of the spare memory block in the Y decoder/driver 3.

In the figure, the circuit portion indicated by the broken line A is the fourth
Common parts with the circuit shown in the figure are duplicated as they are.

ECL gates 31a to 31 as at[nos buffers]
N receives the wired logic signal of the output from c
The OR gates 33i to 33p are constructed of ECL gates operated by two people, similarly to the gates 33a to 33h. The difference is that the other input terminal of each NOR gate 33i to 33p receives a true level switching signal CO instead of a false level switching signal Go-C7 from the defective block switching signal generation circuit 4.
The point where ~C7 is input and the NOR gate 33i~3
3p output limiter follower constant current source CC11, CC
The only difference is that l2 is shared and wired logic is configured. Complementary outputs are taken out from the respective NOR gates 33a to 33p by level converters/drivers 34a to 34h in the next stage.

The circuit type of 34R (see FIG. 6) is taken into consideration.

FIG. 6 shows the outputs a, a to h of the NOR gates 33a to 33h and the wired logic section 35.

A level converter/driver 34a that receives h, R, and R and converts it into a signal suitable for a sense amplifier or a write amplifier.
Specific examples of ~34h and 34R are shown.

That is, the level converters/drivers 34a to 34.
h, 34R are an MO3 differential amplification stage MDA that receives the complementary output signals a, τ to h, h, or R2π, and a two-stage inverter IVI that receives the true level signal a-h or R.
, iv2, and two transistors Q31 . It is composed of a totem pole type output stage TPO in which Q32 is connected in series. In this way, by configuring the Bi-CMO3 circuit, a large load can be driven with less power consumption.

FIG. 7 shows a specific circuit example of the X-system decoder/driver 2.

The X-system decoder/driver 2 of this embodiment has almost the same configuration as the Y-system decoder/driver 3 shown in FIG. That is, the X-system address signals X0-X7 supplied from the outside are sent to the input buffer 21 consisting of ECL gates.
a to 21h, is decoded through the OR gate 22 consisting of wired logic, and is processed into 256 4-person ECLs.
Complementary selection signals WO, WO-W255 . W255 is formed.

The six pairs of complementary selection signals wi, wi are supplied to a level converter/driver having the same configuration as the circuit shown in FIG. A word line drive signal is formed that selects the word line.

FIG. 8 shows an example of the structure of the memory cell array 1.

In the memory cell array 1 of this embodiment, 256 word lines WLO to WL255 and 32 pairs of complementary bit lines BL and BL per block are arranged so as to be orthogonal to each other, and a memory cell MC is arranged at each intersection. ing. Each memory cell MC is connected to a corresponding word line WL and a pair of bit lines BL, BL, and a drive signal supplied from the X-system decoder/driver 2 is supplied to the word line WL.

One end of the bit lines BL, BL (upper end in the figure) is connected to the power supply voltage terminal Vcc via variable load MOS Qvl, Qv2.
It is connected to the. In addition, the variable load MO8Qvl,
Write control MO8Qwl, 0w2 are connected in parallel with Qv2, and are controlled to be in the on state in the write mode by the write enable signal W.

Further, complementary bit lines BL, , πT are provided with a pair of level shift transistors Q51 . Q52 is connected, and this transistor Q5
1. The emitter terminal of Q52 receives the Y system selection signal Ya-Yh.
, column switch MO3, which is turned on and off by YR.
It is connected to the power supply voltage \tee via Qyl and Qy2. Then, the transistor Q51. A pair of differential transistors Q53.Q52 whose emitters are commonly connected to each other is connected to the emitter terminal of Q52. The base terminal of Q54 is connected to the differential transistor Q53. A constant current MO3Qcl is connected to the common emitter terminal of Q54. At the time of reading, the transfer MO3 (Fig. 1.1 (A),
Load MO3Qvl is connected to the bit line connected via Qtl or Qt2 in (B).

Due to the read current flowing from the ii source terminal Vcc through Qwl (or Qv2, 0w2), the voltage difference between the bit line pair generated in the load MO8 is transferred to the differential transistor 53.
Amplify with Q54. In addition, the differential transistor Q53
．． The collector terminal of Q54 is the common bit line CBL, C
Clamping transistors Qrl and Qr2 via BL
A sense amplifier SA of collector dot type is configured. The collector terminals of the clamping transistors Qrl and Qr2 are connected to a resistor Rc.
l, 1 via Rc2! It is connected to the source voltage VCC, and the collector voltages of Qrl and Qr2 are connected to the output buffer DOB.
A read data signal Dn is formed.

the sense amplifier SA and output buffer D;

B is provided in the same number (32) as the number of bits to be simultaneously read out, that is, the memory columns of each block, and is connected to the common bit lines CBL and C to which the sense amplifier SA is connected.
BL includes differential transistors Q53 . The collector of Q54 is connected. Then, the transistors Q51 . Q52 and Q53. Q5
The voltage difference between the bit line pair detected by 4 is amplified by the sense amplifier, and is supplied to the output buffer DOB and output to the outside.

Further, the complementary bit lines BL, BL are provided with write column switches MO3Qs1. A write amplifier WA is connected via Qs2. The write column switches MO3Qsl and Qs2 are controlled on and off by a signal obtained by ANDing the selection signals Ya-Yh and YR output from the Y-system decoder driver 3 and the write enable signal WE. It has become. Further, the write amplifier WA forms write data signals d and c (based on the data input signal D1 supplied via the data input buffer DIB, the write enable signal W lower, and the chip select signal −lower. The written data signals d and a are sent to the power RAM switch MOS Qsl and Qs2.
bit line BL via.

BL is supplied to create a potential difference, and writing is performed to the memory cell to which the word line drive signal of the selection level is being applied at that time.

FIG. 9 shows an example of the configuration of the data output buffer DOB.

Although not particularly limited, read data from the sense amplifier SA is supplied to the output buffer DOB as a differential signal, and the first stage of the data output buffer DOB is
An emitter follower EF consisting of bipolar transistors Qol and Qo2 that receive the signal at their base terminals and a constant current source CC31° CC32 connected to their emitter terminals.
3. 31° EF32 and a transistor Qo whose base terminal receives their outputs. Qo4 and common constant current source CC3
3 and a differential amplifier stage DAMI and transistor Q
It is composed of a Hatake transistor Qo5 whose base terminal receives the collector voltage of o4 and whose emitter terminal is connected to the data output terminal OUT.

FIG. 10 shows an example of the configuration of the data input buffer DIB and write amplifier WA.

Although not particularly limited, the data manual buffer DIB consists of a differential amplification stage, and a differential type signal is formed. One of them is a three-man OR gate G2 consisting of an ECL circuit.
1, and a write enable signal WE and a chip select signal C8 are input to other input terminals of the gate Gll. Also, data manual buffer D
The other differential output of IB is sent to a three-man OR gate G12 having the same configuration as the gate G11, and receives the control signal WE.

It is input together with C8. As a result, when the control signals WE and C3 are both at low level, the input data Di
Write data d and a' corresponding to the data are formed, and level-converted by level converters LVCI and LVC2 to column switch MO3Qsl.

It is supplied to the bit lines BL and 'UL via Qs2 (see FIG. 8).

FIGS. 11(A) and 11(B) show the structure of the above memory cell.

Among these, the memory cell in FIG. 11(A) consists of two CMOS inverters INV whose input and output terminals are cross-coupled with each other.
It is composed of flip-flops MO3Qtl and MO3Qt2 connected between the input/output terminals of these inverters and the bit lines BL and BL. The above transmission gate MO3Qtl, Qt2
The gate terminal of is connected to the word line WL.

On the other hand, the memory cell in FIG. 11(B) connects the P-channel MO3Qpl, Qp2 that constitutes the inverters INVI, INV2 of the memory cell in FIG. 11(A) to the load resistances Rpl, Rp2.
It has been replaced with .

However, the configuration of the memory cell is not limited to these, and may be a bipolar memory cell.

FIG. 12 shows another embodiment of the defective block switching signal generation circuit 4. In FIG.

In this embodiment, instead of providing eight level generating means 41a to 41h corresponding to the number of memory blocks (eight), the number of level generating means is three, and the subsequent stage is a Wiode logic and a two-man NOR. A decoder 43 composed of gates 43a to 43h is provided to form eight types of complementary signals co, co to C7, and C7, which are the sources of block switching signals.

FIG. 13 shows a second embodiment of a static RAM to which the present invention is applied.

In this embodiment, two spare memory blocks having the same storage capacity as the regular block are provided, and two read/write circuits are also provided corresponding to the two spare memory blocks IRI and IR2. Furthermore, the positions of the two spare memory blocks IRI and IR2 are not at the ends of the memory cell array 1 but at the center.

Furthermore, the Y-system decoder/driver 3 and the defective block switching signal generation circuit 4 are also slightly different from those of the embodiment shown in FIG.

That is, as shown in FIG. 14, two sets of defective block switching signal generation circuits 4a and 4b each consisting of eight level generation circuits 41a to 41h and buffer amplifiers 42a to 42h are used.
are provided, and their output signals are supplied to the redundancy switching section 33 together with the decoded signal from the decoder section 32. The redundancy switching section 33 includes a two-man NOR circuit that generates a signal for selecting two spare memory blocks.
Two sets of gates 331 to 33p are provided, and
8-man powered OR gate 35 and level converter/driver 3
Two 4Rs are also provided.

According to this embodiment, it is possible to perform relief even when two of the eight regular memory blocks contain defective bits.

In the above embodiment, the Y-system decoder/driver 3 generates a block selection signal for selecting one of the nine blocks, but the block can be further divided into a plurality of blocks for selection. Such a selection signal may be generated from the Y-system decoder/driver 3. In this way, for example, if one block has 32 pairs of bit lines, by selecting 16 or 8 of them, you can perform parallel reading and writing in 8-bit or 16-bit units. Become.

In FIG. 15, the memory cell array 1 is divided into four blocks I.
An example is shown in which the memory is divided into A, IB, IC, and ID, one spare memory block IR is provided, and the number of memory columns in each block is twice the number of parallel bits read/written simultaneously. has been done.

Further, FIG. 16 shows an example of the configuration of the Y-system decoder/driver 3 in that case.

Since the memory cell array 1 is divided into four parts, the defective block switching signal generating circuit 4 is half the size of that of the embodiment shown in FIG.

In this example, column switches MO3Qyl, Qy
If the read/write circuits 58 to 5h are configured to be provided on the bit lines BL and BL instead of the position as shown in FIG.
Of these, the number of sense amplifiers SA can be reduced to half that of the embodiment shown in FIG.

As explained above, in the above embodiment, the memory cell array is divided into multiple blocks, a spare memory block with the same capacity as this block is added, and multiple bits handled simultaneously can be read or written from the same block. If there is a defective bit in any block, the entire block is switched to a spare memory block, the decoder is configured to drive only the sense amplifier corresponding to the selected block, and an element that can be programmed from the outside is configured. Since the defective block switching signal generating means is provided, it is possible to activate only the selected block and prevent current from flowing to non-selected blocks, thereby significantly reducing power consumption. In addition, the defective block switching signal can be determined before the address signal is input to the decoder, and the switching signal is directly input to the decoder, eliminating the need for a selection circuit such as a multiplexer, increasing access time. Not at all.

Furthermore, since all of the multiple bits that are input and output in parallel are read or written from one block, the configuration of the decoder that generates the signal to switch a block with defective bits to a spare block is simplified, and the configuration of the multiplexer is simplified. Since such a selection circuit is not required, there is an effect that an increase in chip size can be suppressed even when a memory that operates in units of multiple bits is configured.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, a fuse that is cut by passing a current is used as a programmable element in the level generating means, but there are also fuses that are cut by using a dirty laser, and fuses that are cut by using a dirty laser.
A method of using an M element, a method of lowering the resistance of a high-resistance polysilicon conductor by laser annealing, etc. may be used.

The above explanation will mainly focus on the static RAM, which is the field of application that was the background of the invention made by the present inventor.
Although the present invention has been described with reference to the case where it is applied to the above, the present invention is not limited thereto, and can be applied to dynamic RAM, ROM, and other raw conductor storage devices in general.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, in a semiconductor memory device, defective bits can be effectively repaired with low power consumption and without increasing access time, and the chip size can also be reduced when constructing a semiconductor memory that can read and write in parallel in units of multiple bits. It is possible to realize a redundant circuit without significantly increasing the amount of data.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a first embodiment in which the present invention is applied to a static RAM, Fig. 2 is a logic circuit diagram showing a configuration example of a Y-system decoder/driver, and Fig. 3 is a defective block switching A circuit diagram showing an example of the configuration of a signal generation circuit. Figure 4 is a circuit diagram showing a specific example of the regular block selection side of the Y-system decoder/driver. Figure 5 is a specific example of the spare memory block selection side of the Y-system decoder/driver. Figure 6 is a circuit diagram showing a specific example of a level converter/driver, Figure 7 is a circuit diagram showing an example of the configuration of an X-system decoder/driver, and Figure 8 is a circuit diagram of a memory cell array and sense amplifier. A circuit diagram showing an example of the configuration of the main parts, FIG. 9 is a circuit diagram showing an example of the configuration of the data output buffer, FIG. 10 is a circuit diagram showing an example of the configuration of the data manual buffer and write amplifier, FIG. 11 (A), (B) is a circuit diagram showing a configuration example of each memory cell, FIG. 12 is a logic circuit diagram showing another configuration example of a defective block switching signal generation circuit, and FIG. 13 is a static RA 'M to which the present invention is applied. 14 is a logic circuit diagram showing a configuration example of the Y-system decoder/driver, and FIG. 15 is a block diagram showing the second embodiment of the static RAM to which the present invention is applied.
FIG. 16 is a logic circuit diagram showing a configuration example of the Y-system decoder/driver, and FIG. 17 is a block diagram showing an example of a conventional semiconductor memory device having a redundant configuration. 1...Memory cell array, 1a to 1h...Regular block, IRI, IR2, IR3...Spare memory block, 2...X system decoder/driver, 3.
... Y system decoder driver, 4... Defective block switching signal generation circuit, 5... Read/write circuit, 6
...Data input/output circuit, 7...Internal control circuit. Figure 3 Figure 4 Figure 5 Figure 7 Figure 8 A Figure 9 EF31EF32 DAM Figure 10 A Figure 11 (B) Figure 12

Claims (1)

[Claims] 1. Divided into a plurality of blocks having the same storage capacity,
and a memory cell array including a spare memory block having the same storage capacity as each block, and an externally programmable element, and any one of the plurality of blocks.
a defective block switching signal generation circuit that generates a switching signal for replacing the block with a spare memory block when the block has a defective bit; an X-system decoder that selects a word line of the memory cell array; Select any block among them, select multiple bit lines at the same time, and select a specified block among the multiple blocks in response to a switching signal from the defective block switching signal generation circuit.When an address is input to that block. A semiconductor memory device comprising: a Y-system decoder for forming a selection signal for the spare memory block; and a sense amplifier and a write amplifier for reading from and writing to a selected memory cell. 2. The semiconductor memory device according to claim 1, wherein the word line is arranged in a straight line so as to be common to all the divided blocks and the spare memory block. 3. The device according to claim 1 or 2, wherein the number of bit lines selected simultaneously by the Y-system decoder is configured to match the number of bit lines provided in one block. Semiconductor storage device.