JPH04182735A - Information processor - Google Patents

Abstract

PURPOSE:To prevent the interruption of an instruction reading at the time of a block passing by providing a connection pointer at each block in a buffer storage device for instruction word and having its function to invalidate the temporarily read instruction. CONSTITUTION:A connection pointer 121 is provided at each block I to IV in a buffer storage device for instruction word 102 for predicting successor block. At the time of the block passing, as the block number for the passing destination is read from this pointer and is set to an instruction fetch address counter 101, a temporary reading can be made. When the temporary reading is different from an actual one, a coincidence detector 123 invalidates the temporary reading instruction word. Thus, the utilization factor of the information processor can be improved without an interruption of the instruction reading even at the time of the block passing.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an information processing device, and in particular to an instruction word buffer storage device consisting of a large number of blocks, and a method for pre-reading instruction words from the instruction word buffer storage device. an instruction fetch address counter that generates the address of
block crossing detection means for detecting that the last instruction word of the block is being read from the output of the instruction fetch address counter; and when it is detected that the last instruction word of the block is being read; The present invention relates to a pipelined information processing apparatus having a subsequent block detection means for detecting a subsequent block which is a block to be read subsequent to the block in an instruction word buffer storage device.

[Conventional technology]

Conventionally, this type of information processing device, as shown in FIG.
The instruction word buffer storage device 502 and the instruction word buffer storage device [
It has an instruction fetch address counter 501 that generates an address for pre-reading an instruction word from 502, and the read instruction word is fetched (F).
, decode(0).

It passes through address calculation (^), operand fetch (0), and execution (E) stages 503-507.

Each stage 503 to 507 has a busy flag of 5
08 to 512 correspond to each other, indicating that a valid instruction word exists in the corresponding stage.

As shown in FIG. 6, the main memory @600 has multiple (n+1
) blocks. The instruction word buffer storage device 502 is divided into a plurality of blocks (four in this case), and one of the blocks of the main storage device 600 is stored therein. The main memory for each block of the instruction word am memory 502! There are directories 5181-5184 indicating addresses in 600. The indranshicon fetch address counter 501 is incremented each time one instruction word is read out, and when the value indicates the address of the last instruction in the block (hereinafter referred to as block crossing), the block crossing detector 513 Detected when the block is crossed. The logical address register 514 contains the address in the main memory device 600 of the block currently being read, and is incremented from 1 to 1 when a block is detected, and the block number of the subsequent block is detected by the block detector 515 from this value. Ru. The block detector 515 includes directories 5181 to 5 as shown in FIG.
184, comparators 5191 to 5194, and encoder 52
The block number 521 is output by encoding the comparison result between the logical address register 514 and the directories 5181 to 5184.

Next, the operation of the conventional example will be explained with reference to FIG.

When the branch instruction branches to the last address OF of the block ■ in FIG.
is incremented.

Based on this value, the block number of the subsequent block is detected by the block detector 515, and the block number register 51
Set to 6. After the block is crossed and until the block number is detected, reading after the instruction is stopped, and after the detection, the value of the block number register 516 is set in the instruction fetch address counter 501 and reading is resumed.

[Problem to be solved by the invention]

The above-mentioned conventional information processing device has the drawback that the re-reading of instruction words across blocks is interrupted, and the efficiency of instruction reading is reduced, especially in routines that repeatedly cycle across two blocks. There is.

An object of the present invention is to provide an information processing device in which instruction reading is not interrupted when a block is exceeded.

[Means to solve the problem]

The information processing device of the present invention has a connection pointer for predicting a subsequent block for each block in the tlAE storage device for instruction words, and a connection pointer for predicting a subsequent block, and a pointer for detecting a subsequent block after the last instruction of the block is successively issued. Temporary reading flag means for temporarily reading an instruction word from the block predicted by the connection pointer and indicating in which stage on the pipeline the instruction word exists until the subsequent block is detected. a mismatch detecting means for detecting a mismatch between the block predicted by the connection pointer and the subsequent block; and an invalidating step for invalidating the provisionally read instruction word when the mismatch detecting means detects a mismatch. have the means.

[Effect]

Each block of the instruction word buffer storage device is provided with a connection pointer for predicting the subsequent block, and when a block is exceeded, the destination block number is read from there and set in the instruction fetch address counter. It is temporarily possible to read it. Further, when the temporary reading is different from the actual one, the temporarily read instruction word is invalidated.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an information processing device showing an embodiment of the present invention, FIG. 2 is a block diagram showing a mechanism for predicting subsequent blocks, and FIGS. 3 and 4 show the operation of this embodiment. It is a flowchart.

The instruction word buffer storage device 102 has four blocks 1, I
l, I[[, TV, each of which has main memory 2
Input one of the blocks O to N of 00.

Corresponding to each block of the instruction word buffer storage bag @102,
Connection pointers 1211 to 1211 indicating predicted subsequent blocks
There are 1214. The instruction fetch address counter 101 is connected to the instruction word buffer storage device 102.
generates a read address. Block crossing detection 611
7 (block crossing detection means) is an instruction
It is detected from the value of the flip address counter 101 that the last instruction word of the block in the instruction word buffer storage device 102 is being read. Logical address register 118
indicates the logical address in the logical address space of the block currently being read, and is incremented by the block crossing signal 126 from the block crossing detector 117, indicating the logical address of the subsequent block. The block detector 119 (subsequent block detection means) detects the instruction I? corresponding to the logical address indicated by the logical address register 118. The block number of the block in the L word buffer storage device 1i102 is detected. The block number register 120 takes in the block number detected by the block detector 119.

Prediction of subsequent blocks is made using connection pointers 1211 to 121.
4 by loading the subsequent block number 127 selected by the selector 128 into the instruction fetch address counter 101. The subsequent block number register 122 takes in the subsequent block number, which is compared with the block number register 120 by the mismatch detector 123 (mismatch detection means) to determine whether the prediction is successful or not.
A failure is detected.

F, D, A, O, and E stages 103 to 107 rotate the instruction word read from the instruction word buffer storage device 102, and perform instruction fetch, decoding, address calculation, and
Operand, fetch, and execute. Each stage 103
Busy flags 108 to 112 are provided corresponding to stages 108 to 107, which indicate that the instruction words in that stage are valid. Also, F-0 stages 103 to 106
Temporary read flags 113 to 116 (temporary read flag means) 7 are respectively provided for the data, and a temporary read signal 125 indicating that temporary reading is in progress is carried around.

An instruction word at a stage where the temporary read flag is 1 is an instruction word that has been temporarily read.

Next, a case in which the prediction is successful will be described with reference to FIG. When the instruction fetch address counter 101 indicates the last address value "OF" of block I, the block crossing detector 117 detects a block crossing and outputs a block crossing signal 126.

At this time, the logical address register 118 is incremented to create the logical address of the subsequent block. From this address, the block number II 3 II of the subsequent block is detected by the block detector 119 and taken into the block number register 120. Up to this point, three clocks of time are required. Now, regarding the prediction of the subsequent block,
Instruction fetch address counter 1
The value "3" of the connection pointer 1211 corresponding to block (2) is read from the connection pointer 121 from the value "OF" of 01, and is loaded into the instruction fetch address counter 101 with the quimming of 1.

Further, a case where prediction fails will be explained with reference to FIG. 4. In this case, the subsequent block is predicted to be Pa2'',
This is a case where provisional reading is started from there. During temporary reading,
The temporary read signal 125 is rotated among the temporary read flags 113 to 116. When the subsequent block r+3 TI is detected at timing 3, the failure of prediction is detected by the innumerable construction insect 123, the pipe invalidation flag 124 (invalidation means) is set, and the temporary read flag is set. Invalidate the stage that is 1. Invalidation is done by resetting the busy flag.

Also, if the prediction fails, the correct subsequent block number II
31+ is the instruction fetch address
The counter 101 is loaded and reading resumes from the correct block. Furthermore, “3” is added to the corresponding connection pointer.
" is input, and "3" is predicted the next time the block is crossed.

〔Effect of the invention〕

As explained above, the present invention provides a connection pointer in each block of the instruction word buffer storage device and has a function to invalidate temporarily read instructions, so that instructions can be read even when blocks are exceeded. This has the effect of increasing the utilization efficiency of the information processing device without interruption.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an information processing device showing an embodiment of the present invention, FIG. 2 is a block diagram explaining connection pointers 1211-1214, and FIG. 3.4 shows the operation of the information processing device of FIG. 5 is a block diagram showing the conventional example, FIG. 6 is a block diagram explaining block number detection, and FIG. 7 is a time chart showing the operation of the conventional example shown in FIG. 101.501...Instruction fetch
Address counter, 102.502... instruction word buffer storage device, 103.
503...F stage, 104.504...D stage, 105.505...A stage, 106.506...O stage, 107.507...E stage, 108.508...F Doji Flag, 109.509
...D busy flag, 110.510...△busy flag, 111.511...O busy flag, 112
．． 512...E busy flag, 113...F temporary read flag, 114...D temporary read flag, 115...A temporary read flag, 116...O temporary read' flag, 117.513... Block crossing detector, 118.5
14...Logical address register, 119.515...
・Block detector, 120.516...Block number register, 1211-1214...Connection pointer, 1
22...Subsequent block number register, 123...Inconsistency detector, 124...Vibe invalidation flag, 125...Temporary read signal, 126.517...Block crossing signal, 127...
Subsequent block number, 128...Selector, 129...Read instruction, 200.600...Main storage device, 5181-5184...Directory, 5191-5
194...Comparator, 520...Encoder, 512...Block number. Patent applicant: Kofu Nippon°Tunki Co., Ltd. Agent
Patent attorney T Uchihara

Claims (1)

[Claims] 1. An instruction word buffer storage device consisting of a large number of blocks;
an instruction fetch address counter that generates an address for pre-reading an instruction word from the buffer storage device;
block crossing detection means for detecting that the last instruction word of the block is being read from the output of the address counter; In a pipelined information processing device having a subsequent block detection means for detecting a subsequent block that is a block to be read subsequent to the block in the storage device, for each block in the instruction word buffer storage device, A connection pointer predicts a subsequent block, and an instruction word is tentatively read from the block predicted by the connection pointer between the time the last instruction of the block is read and the subsequent block is detected. provisional read flag means for indicating in which stage on the pipeline the block is present; mismatch detection means for detecting mismatch between the block predicted by the connection pointer at the stage when the subsequent block is detected and the subsequent block; An information processing apparatus comprising: invalidation means for invalidating the provisionally read instruction word when a mismatch is detected by the mismatch detection means.