JPH0418271B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device that once charges an input signal current to a capacitor and then reads out the charged voltage later to measure the signal current.

An X-ray CT (Computerized Tomography) apparatus is configured to irradiate an object to be measured with X-rays, detect the transmitted X-rays with a number of ionization chambers, and obtain projection data regarding the object based on the signals.
In this case, the device uses a current measuring device that measures the output current of each multi-channel ionization chamber. Conventional current measuring devices convert the ionizing current corresponding to the intensity of transmitted X-rays obtained from an X-ray ionization chamber into a current/voltage for each channel, and convert this into a current/voltage using an analog-to-digital converter (hereinafter referred to as an AD converter). It's going digital. In this case, leakage current may flow into the capacitor used for current/voltage conversion, and the amplifier that amplifies the charge voltage of this capacitor has a non-negligible offset, so high precision measurement is required. In order to achieve these expectations, it is necessary to correct these error elements. Although the offset of an amplifier can be corrected in an analog manner using an auto-zero method, conventionally there has been no suitable means for correcting the error element where leakage current from the circuit flows into the capacitor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a means for eliminating the influence of leakage current flowing into a capacitor in a device that measures a signal current as a charge voltage of a capacitor.

FIG. 1 is a configuration diagram of main parts showing an embodiment of a current measuring device according to the present invention. In the same figure, I ₁ to I _o
represents a signal current, and in terms of an X-ray CT device, it is an ionization current that corresponds to the intensity of transmitted X-rays. C ₁ -C _o are capacitors that convert each signal current I ₁ -I _o into voltage. S ₁ -S _o represent sampling switches, which select the voltages of the respective capacitors C ₁ -C _o and transmit them to the next stage. Note that this sampling switch may be replaced by a multiplexer instead of the plurality of switches shown in the figure. Sr represents a reset switch and has the function of discharging the charges of the capacitors C ₁ to _Co. U represents an amplifier which has a high input impedance and receives the voltages of the capacitors C ₁ to _Co , and also converts these voltages into appropriate magnitudes and transmits them to the next stage. 11 is an A/D converter that converts an analog signal into a digital signal; 12 is a memory that stores the output of the A/D converter 11; 13
is an arithmetic unit that appropriately calculates two digital signals, 1
4 is a switching circuit that appropriately switches and transmits the signal from the A/D converter 11 to the memory 12 and the arithmetic unit 13;
15 represents a timing control circuit, which includes sampling switches S ₁ to S _o , reset switches Sr, A.
It controls the timing of the D converter 11, memory 12, switching circuit 14, and arithmetic unit 13.

Capacitors C ₁ to _{C o} are connected to each input channel terminal 1
~n and circuit ground. Each input channel terminal 1 to n is connected to an amplifier U via a sampling switch S ₁ to _{S o} and to circuit ground via a contact of a reset switch Sr. The output of amplifier U is introduced into A/D converter 11 . The output of the A/D converter 11 is introduced into the memory 12 via the switching circuit 14 or into the arithmetic unit 13. The timing control circuit is the first
The timing of each part is controlled as shown in the figure. Note that i ₁ to i o added in parallel to each capacitor C ₁ to _{C o} represent leakage currents.

The operation of the apparatus shown in FIG. 1 configured as above will be explained with reference to FIG. 2. FIG. 2 is a diagram showing the timings of the sampling switches S ₁ -S _o , the reset switch Sr, and the signal currents I ₁ -I _o . In FIG. 2, (a) to (nu) represent periods, and on the left side of each waveform, the switch element name and signal current of the operation corresponding to that waveform are shown. It is assumed that the switch is on during the "high" level period of the waveform indicating the operation of each switch, and is off during the "low" level period. The operation will be explained below for each period (A) to (J).

During the period (a), the reset switch Sr and each sampling switch S ₁ -S _o are turned on, and the charges in the capacitors C ₁ -C _o are discharged.

During the period (b), the switches S ₁ -S _o and Sr are turned off, and the signal currents I ₁ -I _o of each channel are charged to the capacitors C ₁ -C _o . In addition, the leakage current i ₁ ~ i _o which is an error factor
flows into each capacitor C ₁ -C _o as shown in FIG. Of course, the direction in which the leakage currents i ₁ to _io flow is not limited to that shown in FIG. 1, and charges may flow out from the capacitors C ₁ to _Co.

Period (c) As shown in FIG. 2, only the sampling switch _S1 is turned on after a time _T1 after the capacitors _C1 to _Co are discharged by the reset switch Sr. Therefore, the charge voltage of the capacitor C ₁ is amplified by the amplifier U, converted into a digital signal e ₁ by the A/D converter 11, and stored in the memory 12. At this time, the output voltage E ₁ of the amplifier is expressed by equation (1).

E ₁ = {1/C ₁ ∫ ^T1 ₀ (I ₁ + i ₁ ) + Vos}・G (1) Here, Vos is the offset voltage of amplifier U, G
represents the amplification degree in amplifier U. That is,
During the period (c), the voltage E1 consisting of the signal current _I1 , the leakage current _i1 flowing into the capacitor _C1 over the period _T1 , and the offset voltage _Vos of the amplifier U is measured. A signal e ₁ obtained by converting the voltage E ₁ into a digital signal is stored in the memory 12 .

Periods (d) and (e) During these periods, each signal current I ₂ to _{I o} input from the second channel to the n-th channel is measured in the same manner as in (c) above. Regarding the n-th channel, only the sampling switch _S0 is turned on after a time _T0 after capacitors _C1 to _C0 are discharged by the reset switch Sr. Therefore, the charge voltage of capacitor C _o is amplified by amplifier U,
The signal is converted into a digital signal e _o by the A/D converter 11 and stored in the memory 12 . At this time, the output voltage E _o of the amplifier is expressed by equation (2).

E _o = {1/C _o ∫ ^Tn ₀ (I _o + i _o ) + Vos}・G (2) Period of (f) Similar to (a) above, the electric charge stored in the capacitors C ₁ to C _o Discharged and reset.

During the period (g), the signal currents I ₁ to I _o are not generated, and the period (g) is set to the same time T ₁ as the period (b).
It is desirable that the periods (b) and (g) are the same, but the purpose of the present invention can be achieved if they are substantially the same.

During the period from (h) to (j), error elements based on the leakage currents i ₁ to _{i o} from the first channel to the n-th channel and the offset voltage Vos of the amplifier U are measured. If we explain it in terms of the nth channel, the time elapsed after the capacitor C _o discharges is
Over a period of T _o , the charge voltage at which the leakage current i _o flows into the capacitor C _o is measured. The output voltage E _o ' of the amplifier U at this time is expressed by equation (3).

E _o ′={1/C _o ∫ ^Tn ₀ i _o +Vos}・G (3) As explained above, the signal current I _o including error elements measured in the period (c) to (e) I _o is stored in memory 12 as digital signals e ₁ to _{e o} . On the other hand, in the periods (chi) to (nu), error elements are measured as shown in equation (3). This equation (3) voltage E _o ′ is A・D
The converter 11 converts it into a digital signal e _o '. Therefore, the two digital signals e ₁ and e ₁ ′, e ₂ and e ₂ ′, ... e _o and e _o ′, corresponding to each input channel are input to the computing unit 13.
are subtracted from each other. If this is represented by the n-th channel, a signal based on equation (4) can be obtained as the output data of the arithmetic unit 13.

Output data = 1/C _o ∫ ^Tn ₀ I _o・G (4) As is clear from equation (4), the output data is
The leakage currents i ₁ -io and the offset voltage Vos of the amplifier _U , which are error elements, are removed, and the signal currents I _{1 -Io} to be measured can be accurately obtained.

In Fig. 1, the signals e ₁ to e _o are stored in the memory 1.
2, and the error element signals e ₁ ′ to _{e o} ′ are sent directly to the arithmetic unit 1 by the switching circuit 14 without going through the memory 12.
Although the configuration is such that the error element signals e ₁ ' to e _o ' are also stored in the memory 12 and read out from there, it is clear that the present invention can be applied.

Further, in the above description, the case of multi-channel input has been explained as an example, but it is clear that the present invention can be applied even in the case of only one channel input.

As described above, according to the present invention, the leakage current i ₁ ~
The influence of _io and the offset voltage Vos of the amplifier is removed, and the signal currents I ₁ to _Io can be accurately measured, resulting in a great effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram of main parts showing one embodiment of a current measuring device according to the present invention, and FIG. 2 is a timing chart of each switch. I ₁ ~ _{I o} ... Signal current, C _{1 ~ Co} ... Capacitor,
i ₁ - i _o ... leakage current, S ₁ - S _o ... sampling switch, Sr ... reset switch, U ... amplifier, 11 ... A/D converter, 12 ... memory, 1
3... Arithmetic unit, 14... Switching circuit, 15... Timing control circuit.

Claims (1)

[Scope of Claims] 1. A device that once charges an input signal current to a capacitor and then reads out the charged voltage to measure the signal current, comprising: a reset switch that discharges the charge of the capacitor at a certain time; A sampling switch that extracts the charge voltage of the capacitor after a predetermined time (T1) from , and an A/D exchanger that converts the voltage based on the charge voltage extracted by this sampling switch into a digital signal, into which a signal current flows. Either a digital value (e1) based on the charge voltage of the capacitor taken out from the sampling switch in the state, or a digital value (e1') based on the charge voltage of the capacitor taken out from the sampling switch in the state where no signal current flows. On the other hand,
or a memory that stores both, and an arithmetic unit that subtracts the digital value (e1) obtained when the signal current flows and the digital value (e1') obtained when the signal current does not flow. A current measuring device equipped with , . 2. The input signal current is a multi-channel signal current, and the capacitor is a plurality of capacitors provided for each channel, and the reset switch resets the charge of each capacitor at a certain time. It is a reset switch that discharges all at once, and the sampling switch is provided for each channel, and a period (T1, T2,...Tn) determined for each channel from the above-mentioned time.
A sampling switch that later takes out the charge voltage of the capacitor of the channel, and the memory stores digital values (e1, e2, ...) based on the charge voltage of the capacitor taken out from the sampling switch in a state in which a signal current flows; Or digital values (e1', e2',
...), wherein the arithmetic unit stores the digital values (e1, e2, ...) obtained in a state where a signal current flows and a state where a signal current does not flow. The digital value (e1', e2', ...) obtained from the same channel is an arithmetic unit that subtracts the digital values (e1 and e1') obtained from the capacitors of the same channel. A current measuring device according to claim 1.