JPH04181765A - Module of integrated circuit - Google Patents

Abstract

PURPOSE: To improve the reliability of physical and electrical connection by connecting a plurality of layers provided with a vertical end edge inclined along a continuous part to a contact board provided with an inclined surface for receiving and supporting the layer of an integrated circuit arranged perpendicularly to the layers. CONSTITUTION: A plurality of layers 11 of the integrated circuit are provided; the respective layers 11 are provided with an upper surface 51, a lower surface 47, and the vertical end edge 45; and the inclined surface 15 is provided on a part of the vertical end edge 45. Also, the contact board 13 arranged perpendicularly to the layers 11 and connected to the vertical end edge 45 is provided and the contact board 13 is provided with first and second surface 17 and 43. The first surface 17 receives and supports the layer 11 and an inclined part 17 for being abutted to the inclined part 15 of the end edge 45 of the layer 11 and supporting it and a vertical part 43 for being abutted to the lower surface 47 of the layer 11 and supporting it are provided. Then, electric signals are transmitted by conductive pads 23 and 21 formed on the layers 11 of the integrated circuit and the inclined surface 17 of the contact board 13. Thus, the reliability of the physical and electrical connection is improved.

Description

BACKGROUND OF THE INVENTION This invention relates to integrated circuit modules, and more particularly to integrated circuit modules suitable for supporting arrays of infrared detector elements in a space environment.

Infrared detector modules are used for a variety of purposes including space surveillance. In view of the stringent environmental and performance demands of such systems, as well as the spatial limitations of launch and orbit, it is important to miniaturize the module and at the same time achieve high performance and high reliability of operation. There has been an increasing practical need to preserve it.

For example, to provide accurate resolution for infrared imaging, it may be necessary to spatialize the elements of an infrared detector to less than 4 mm. It is also desirable to provide some form of focal plane processing to limit the need to communicate raw data to a remote processor.

As a result, it not only solves the problem of dense connectivity, but also
There has been a growing need to provide improved modular structures that allow raw input signals to be processed on the focal plane.

Various structures have been proposed for integrated circuit modules. One such structure is disclosed in U.S. Patent No. 4.703.170 issued to Charles E. SchmiH and commonly assigned to the present assignee. One area of concern with such modules relates to the physical means for connecting the array of infrared detectors bonded to buffers, contact boards or interface devices to the module supporting the processing circuitry. A common technique for making such physical and electrical connections is to make an interface device on the surface of the detector that abuts against a conductive region formed on the surface of the vertical edge of the layer of the module. Including forming a diamond bump. The edge surfaces of the indium pump and module of the interface device are typically held in place by an insulating adhesive material. In such a structure, the individual layers are not supported by the structure of the detector interface device or by the shape or structure of the module's layers. Such a structure has several drawbacks. Not only is redundant alignment of the detector interface device and module required, but the entire detector interface device/module interface is encased in adhesive as a means of connecting the module to the detector interface device. It is necessary to put it away. Therefore, individual module layers cannot be selectively removed from the module. Manufacturing of such modules typically proceeds by first forming a rigid multilayer module and then connecting the module to the detector interface device.

As a practical matter, it is important to match the spatial dimensions of the detector elements to be the same as those of the interface device or contact board and to easily create electrical contact between the layers of the stack and the contact board. Difficulties exist in spatially aligning layers. Furthermore, the extreme thinness of the module layers and the intensive processing requirements result in a predictable number of defects that are often not discernible until the module layers are connected to the detector interface device. However, since the layers of the module are permanently connected, defects occurring with any particular layer typically result in the entire module being scrapped.

Therefore, it is possible to make the physical and electrical connections more reliable and less redundant, and to select individual layers even after the module has been formed and connected to the detector interface device. There is a need to develop an alternating arrangement for connecting layers of modules to detector interfaces that facilitates modular replacement.

SUMMARY OF THE INVENTION Integrated circuit modules and techniques for their formation are disclosed. The module includes a plurality of layers of integrated circuits having sloped vertical edges along the portion thereof. The layers are connected to a contact board having a sloped first surface disposed perpendicular to the layers and also configured to receive and support the layers of the integrated circuit.

Each layer of the integrated circuit may have sloped portions at its ends to facilitate connection to a pair of contact boards disposed on one end of the layer of the integrated circuit. Transmission of electrical signals is facilitated by conductive pads formed on the layers of the integrated circuit and on the sloped surfaces of the contact board.

In the presently preferred embodiment, the edges of the layers of the integrated circuit are sloped only along that portion, and the remaining portions are perpendicular to the first surface of the layer.

The contact board also incorporates non-slope sections extending between sloped sections. The non-slope portion facilitates reliable structural and electrical connections between the integrated circuit layers and the contact board despite size variations in the integrated circuit layers and the contact board.

In the presently preferred embodiment, the sloped portions are formed by isotropically etching the surface of the single crystal silicon integrated circuit layer and contact board. The layers of the integrated circuit and the contact board are sloped during isotropic etching so that the sloped portions complement each other, thereby facilitating precise mating of the surfaces of the circuit layers and the surface of the contact board. It is formed to have a crystal lattice structure oriented in this way.

Adhesive layers or lands may be disposed between adjacent integrated circuit layers. Adhesive lands may also be placed between, for example, sloped surfaces that connect the layers of the integrated circuit to the contact board. The integrated circuit layers are secured to the contact board at both ends, and the integrated circuit layers do not need to be secured together with adhesive material. Thus, individual circuit layers can be removed from the module, ie from the connection to the contact board, without the need to disassemble the entire module. Alternatively, the layers may be connected to each other and/or by materials that can be easily liquefied, such as solder, which facilitates the selective removal of individual circuit layers without disassembling the entire module. Can be fixed to the board.

DETAILED DESCRIPTION OF THE CURRENTLY PREFERRED EMBODIMENTS The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of the presently preferred embodiments of this invention and is only one example of how the invention may be constructed or utilized. It is not intended as an indication of form. The function and sequence of steps for constituting the invention in the context of the illustrated embodiments will now be described. However, it is to be understood that the same or equivalent functions and sequences may be achieved by different embodiments that are intended to be encompassed within the scope of this invention.

FIG. 1 shows a layer 1 with sloped edges formed thereon.
1 is a partial cross-sectional view showing the connection of contact board 1.
3 has a sawtooth pattern formed in one of its surfaces. As shown in FIG. 1, the layers 11 are each formed with sloped edges 15, which edges are formed by isotropic etching of (100) single crystal silicon. Contact board 13 has edge 1
5 with a beveled edge 17 shaped to engage the beveled edge 15 of the layer.

As mentioned above, the layer is preferably extremely thin, ie about 3 to 4 mm. The formation of electrical contacts between the layers of the stack and the contact board is carried out in order to obtain the required periodic spacing of the layers in the stack by controlling the thickness of each layer, and also by forming contacts on the faces of the stack. A number of processes are performed redundantly to prepare the contact board and to align and bump bond the electrical contacts to the contact board. The present invention employs a stack of sloped edge layer surfaces and a sloped groove contact board. This involves much less redundant processing.

However, the problem of creating accurate alignment angles should be addressed by using isotropic etching on the edge portions of both the layer and the surface of the contact board. It is to be understood that the present invention is not intended to be limited to any particular method of forming precise interlocking angles on the interlocking surfaces. It is anticipated that other methods, which may be more or less effective, may be used in the broader aspects of the invention.

The isotropic etching technique used in the presently preferred embodiment effectively etches a single crystal material in a predictable direction with respect to the crystal lattice. In the presently preferred embodiment, layer 11 is formed on a single (100) oriented crystalline silicon material. Isotropic etching selectively etches silicon atoms until they reach the portion of the silicon crystal lattice defined by (111). In practice, isotropic etching results in slanted edges, the angle of which is determined by the silicon crystal lattice. In the presently preferred embodiment, a wafer of silicon is formed such that the (100) orientation of the silicon molecules is aligned in the direction shown in FIG. As a result, silicon layer 1
An isotropic etch of 1 produces the sloped surface 15 shown in FIG. In view of the particular crystal lattice structure of silicon molecules, the sloped surface 15 is formed to have sloped bevels as shown in FIG. This bevel can be repeated as long as the (100) crystal orientation of the silicon module remains as indicated.

When a (100) single crystal silicon material is used, the bevel angle will be 54 degrees instead of 45 degrees, so the angle of the slanted groove in the contact board must be shaped to match the bevel angle of the layer. Must be. As explained below, this means that isotropic etching compensates for the oblique angle of the layer.
This is done by forming the contact board to have a crystal lattice orientation that forms 36 degrees.

Figures 2a and 2b illustrate the formation of an interlock between the surface of the layer and the surface of the contact board in accordance with the presently preferred embodiment of the present invention. As shown in Figure 2a, the contact board 13 is formed including a plurality of conductive pads 21 formed on the sloped surface 17. As shown in Figure 2b, the layer 11 is formed on the contact board. It includes a conductive pad 23 in abutting electrical connection with pad 21. The conductive pad 23 of the layer is in electrical communication with a conductive pattern 25 formed on the first surface of layer 11. Conductive pads 23 transmit signals to integrated circuit structures 27 formed on the surface of layer 11 .

Although the figure shows layer 11 connected to a single contact board, it should be understood that layer 11 could be connected to a second contact board along opposite edges of the contact board. The second contact board may be assembled and formed in the same manner as contact board 13. As a result of the two contact board embodiment, layer 11 is supported at both ends by contact boards.

Referring again to FIG. 2b, further description regarding the preferred structure of contact board 13 will now be made.

As shown therein, the contact board 13 is also provided with a plurality of conductive pads 29 formed on the second surface of the contact board. Conductive pads 29 preferably form an array of areas on the lower surface of contact board 13, as shown more clearly in FIG. FIG. 5 illustrates the underside of contact board 13, with conductive pads 29
are arranged in rows interconnected by conductive strips 33. Depending on the processing application, it may be beneficial to interconnect several rows, i.e. alternating rows or all rows of conductive pads, thereby connecting the interconnected detector elements (not shown). ) can be processed in the most efficient and useful manner.

Referring again to FIG. 2b, pad 21 and conductive pad 29
Electrical communication between the contact board 13 and
This is done by a conductive via 31 extending through it. In the presently preferred embodiment, the conductive vias are formed by well known techniques such as vapor phase plating of through holes formed in contact board 13.

Figures 3a and 3b provide additional illustrations of the contact board 13 shown in Figures 2a and 2b. FIG. 3b also shows the formation of an insulating oxide layer 35 formed on the surface of contact board 13. FIG. The opposite side of layer 13 is also as shown in FIGS. 2b and 3b.
A layer 37 of oxide may be provided. Layer 11 is also a second
An insulating oxide layer 39 may be provided, as indicated by bD.

As shown in FIG. 3b, the upper surface of the contact board 13 includes an inclined surface 17, a horizontal portion 41, respectively.
and a plurality of grooves or channels 20 characterized by vertical portions 43 . The sloped surface 17 and the vertical surface 43 are shown in FIGS. 2a and 2b.
As can be seen, the corresponding surface of layer 11 is received and engaged. Horizontal portion 41 provides a basis for accommodating size changes without compromising the structural or electrical integrity of the connection between layer 11 and contact board 13. Layer 11 is likewise formed to have a sloped portion 15, a non-sloped portion 45 and a bottom portion 47.

Portions 41 and 45 need not be sized to be the same and may in fact vary in length or thickness without compromising the integrity of the connection between layer 11 and board 13.

6a, 6b, 7 and 8 illustrate the steps in forming contact board 13. FIG. As shown in FIG. 6a, the formation of contact board 13 begins by forming a grooved silicon wafer 30, as shown in FIGS. 6a and 6b. Groove 40 extends into top surface 42 of wafer 30 and extends into sidewall 43.
．． 44 and bottom 41 . As shown in FIG. 7, the wafer is formed such that the silicon crystal lattice has a (100) orientation in the vertical direction as shown or a (110) orientation in the horizontal direction. Ru. A layer of photoresist 49 covers the surface 42 of the wafer, excluding the vertical walls 44 of the grooves 4o, as shown in FIG.
, are formed along the vertical wall surface 43. An isotropic etchant is then applied to the wafer. This results in an essentially v-shaped etching from wall surface 44 defined by surfaces 17 and 18. This etching may continue until reaching and portioning surface 43, thereby allowing separation of portions of the wafer on surface 17. The resulting structure is as shown in FIG.

Also shown in FIG. 8, conductive vias 31 are now formed within the wafer. The silicon surfaces, including the walls of the via holes, are oxide coated. produced on metal films or their surfaces. Conductive pads 21 and 29 are then formed as shown in Figure 3b.

9, 10, 11, 12, 13a and 13b illustrate the formation of layer 11 of the integrated circuit. 9th
The figure comprehensively shows the edges of the layer 11 including the top sloped surface 5, the non-sloped surface 43, the bottom surface 47 and the top surface 51. As shown in FIG. 9, the layer is formed of a single crystalline silicon material with a crystal lattice orientation, and the (100) orientation of the lattice is formed as shown. FIG. 10 shows the first step in forming layer 11. FIG. As shown therein, a trench 50 is formed in a silicon wafer 52. As shown in FIG. In the presently preferred embodiment, the grooves 5o are formed by isotropic etching of the upper surface 51. However, it should be understood that other alternative methods may be used to form grooves 5o without departing from the broader aspects of this invention. As also shown in FIG. 10, the groove 50 is defined by sloping side walls 15 and 16. Isotropic etching can be carried out up to the point shown in FIG.
is extended by the formation of trench 54. trench 54
is defined by side walls 45,46 and bottom surface 48.

As shown in FIG. 12, the upper surface of wafer 52 is then provided with a layer 39 of oxide. Integrated circuit structure 2
7 is formed in the upper surface of wafer 52. Conductive pads 23 and conductive patterns 25 are formed to provide electrical communication between integrated circuit structure 27 and pads 23. Grooves 50 are repeated along the surface of the wafer 52 and the opposing sloped surfaces 16 (see, e.g., FIG. 11)
It should be understood that the pads may be provided with conductive pads in electrical communication with the integrated circuit structure 27 as well. In this manner a layer can be formed to be placed between pairs of contact boards 13.

As shown in FIG. 13a, wafer 52 is thinned to approximately a thickness compatible with forming trenches in lower surface 48, resulting in separation of multiple structures compatible with layer 11. FIG. 13b further shows layer 1 showing redundant conductive pads 23, each connected by a conductive pattern 25 to an integrated circuit structure 27 (shown within dashed lines).
1 is shown.

The contact pads on the layer and board are bonded and
It can be coated with a low melting point alloy such as solder or with pillar bumps of metal such as indium. This method can optionally be accomplished as part of wafer fabrication. Layer 1 can then be positioned to engage a portion of contact board 13 as shown in FIG.

Bonding with the alloy can then be achieved by heating. FIG. 15 shows multiple circuit layers 11 connected to a single contact board 13. FIG.

Layers 11 may be bonded and separated by a layer of insulating adhesive material disposed within channels 53 separating adjacent layers 11. Alternatively, small lands of insulating adhesive provide adhesion and separation between adjacent layers and facilitate removal of adhesive lands and selective removal of individual layers 11 while other layers 11 are attached to the contact board. 13 may be placed within the two-channel 53 to remain in contact with it. When two contact boards 13 are used, layer 11 can be sufficiently supported between the two contact boards 13 to avoid the need for an adhesive layer to provide structural integrity to the module. In such a case, removal of individual layers 11 can be carried out without the need to disturb adjacent layers 11. In such a structure, there may be no need for adhesive layers or lands between adjacent layers 11.

Thus, the module may be formed without gluing the layers 11 into a unitary structure prior to connecting the layers to the contact board 13.

Various other modifications and enhancements may be made within the scope of the present invention. As mentioned above, the exact angle of the sloped surface may vary depending on the particular material and the characteristic crystal structure of that material. In addition, mechanical or optical methods can
It can be used to form the sloped surfaces shown above. Such mechanical or optical methods may be particularly suitable if the contact board and layer dimensions allow for effective use of such techniques.

[Brief explanation of drawings]

FIG. 1 is a partial side view of an integrated circuit module showing complementary contact angles in which angled layers engage a contact board. FIG. 2a is a perspective view of a single integrated circuit layer connected to a grooved contact board. Figure 2b is a side view of the structure shown in Figure 2ae, further illustrating the conductive pads, conductive vias, and integrated circuit structure. Figure 3a is a perspective view of a grooved contact board showing conductive pads formed on the sloped surface. Figure 3b is a side view of the contact board shown in Figure 3a, further illustrating additional contact pads and conductive vias extending through the contact board. FIG. 4 is a bottom view of the contact board showing a plurality of conductive pads. FIG. 5 is a bottom view of an alternative contact board with interconnected rows of conductive pads. Figures 6a, 6b, 7 and 8 are diagrams illustrating the manufacture of a contact board. 9, 10, 11, 12, 13a and 13b illustrate the formation of layers of an integrated circuit. 14 and 15 are perspective views showing the assembly of contact boards and integrated circuit layers forming an integrated circuit module. In the figure, 11 is a layer, 13 is a contact board, and 15 is a layer.
and 17 is a beveled edge, 21 is a contact board pad, 23 is a conductive pad, 25 is a conductive pattern, 27 is an integrated circuit structure, 29 is a conductive pad, 31 is a conductive via;
35 is an oxide layer, 41 is a horizontal portion, 43 is a vertical portion, 4
7 is the bottom part, 50 is the groove, 51 is the top surface, 52 is the wafer, and 54 is the trench. Applicant Geraman Aerospace (2 idiots) 〉 □ Jitoζ

Claims (23)

[Claims] (1) An integrated circuit module comprising a plurality of integrated circuit layers, each of the layers having an upper and a lower surface and a pair of vertical edges, at least a first of the vertical edges. is sloped along at least a portion thereof and further includes a first contact board disposed perpendicularly to the layer of the integrated circuit and connected to a first vertical edge thereof;
a contact board having first and second surfaces, each of the first surfaces having a plurality of layer-receiving channels formed to receive and support a plurality of layers of integrated circuits, each of the channels a sloped portion formed to abut against and support the sloped portion of the first edge of the layer of circuitry; a vertical portion formed to support each of the integrated circuit layers, each of the integrated circuit layers having an integrated circuit structure formed on a top surface thereof, and each of the integrated circuit layers also having a first a first electrically conductive pad formed on the sloped portion of the edge, said first electrically conductive pad being in electrical connection with an integrated circuit structure formed on a respective layer; a contact board is further formed on each of the sloped portions, further comprising a second conductive pad for abutting electrical connection with the first conductive pad formed over the layer of the integrated circuit. have,
the first contact board further having a plurality of third conductive pads formed on a second surface thereof;
each of the conductive pads of the module is connected to a dedicated second conductive pad by a conductive via extending through the first contact board. (2) each of the layers of the circuit further includes a second vertical edge, the second vertical edge being sloped along the portion, and the sloped surface of the second vertical edge being above the second vertical edge; 2. The module of claim 1, further comprising a fourth conductive pad formed on a respective integrated circuit layer, the fourth conductive pad being in electrical communication with an integrated circuit structure formed on a respective integrated circuit layer. . (3) further comprising a second contact board disposed orthogonally to the layer of the integrated circuit and connected to a second vertical edge thereof, the second contact board having first and second surfaces; and wherein the first surface has a plurality of layers receiving channels, each channel configured to abut against and support an angled portion of a second edge of a layer of circuitry. 3. An integrated circuit module as claimed in claim 2, having an angled portion and a vertical portion formed to abut against and support a lower portion of a layer of circuitry. (4) said second contact board is formed on each of its sloped portions, a fifth contact board for abutting electrical connection to a fourth conductive pad formed on a layer of an integrated circuit; 4. The module of claim 3, further comprising a conductive pad. (5) the second contact board further includes a plurality of sixth conductive pads formed on the second surface thereof;
5. The module of claim 4, wherein each of the sixth conductive pads is connected to a dedicated fifth conductive pad by a conductive via extending through a second contact board. 6. The module of claim 1, wherein the third conductive pad is connectable to a planar array of infrared sensing modules. 7. The module of claim 1, wherein the integrated circuit layer is formed to be between 3 and 4 millimeters thick. 8. The module of claim 3, wherein individual integrated circuit layers are separately removable from the integrated circuit module. 9. The module of claim 1, further comprising an adhesive insulating land disposed between adjacent integrated circuit layers. 10. The module of claim 1, further comprising a plurality of adhesive insulating lands connecting the layer of circuitry to the first contact board. 11. The module of claim 3, further comprising an adhesive layer disposed between adjacent integrated circuit layers. (12) the sloped portion of the layer extends only along a portion of the first vertical edge of the layer, and the remaining portion of said first vertical edge connects the layer of circuitry and the first contact board; 2. The module of claim 1, which serves to facilitate abutting engagement of the circuit layers and the contact board despite changes in size during assembly. 13. The first surface of the first contact board further comprises a horizontal surface portion extending between an inclined portion of the board of circuitry and a vertical portion of the board of circuitry.
The module described in 2. 14. The module of claim 1, wherein the integrated circuit layer is formed to have a crystal lattice structure of the layer characterized by a (100) crystal orientation extending parallel to the top surface of the layer. (15) The first contact board is the second contact board of the circuit board.
2. A module according to claim 1, formed to have a crystal lattice structure characterized by an orientation of 100 crystals extending at right angles to the surface of the module. (16) A method for forming an integrated circuit module comprising a plurality of circuit layers bound together on at least one end by a contact board, the method comprising: a. at least one circuit layer in a first surface of the plurality of layers; isotropically etching two V-shaped grooves; b. forming a trench in each of the V-shaped grooves, the trench extending into the silicon substrate beyond the depth of the V-shaped grooves; c. forming an integrated circuit structure on a first surface of each of the layers; and d. forming a first sloped surface of the V-shaped groove of each of the layers.
forming conductive pads, said pads being in electrical communication with an integrated circuit structure; e. thinning each of the layers so that the thickness of each layer is substantially equal to the depth of the trench; f. separating portions of layers along trench sidewalls such that the first sloped surface and the first trench sidewall define a first edge portion of each layer; forming a plurality of trenches on a first surface of the contact board; g. isotropically etching the surface of the first vertical edges of the trenches of the contact board to form a plurality of layer receiving channels; each of the channels includes a repeating sawtooth pattern on a first surface of the circuit board, each sawtooth pattern including a vertical surface and a second sloped surface and a horizontal portion; h. forming a second conductive pad on each of the second sloped surfaces; i. a plurality of third conductive pads along the second surface of the contact board;
forming conductive pads of j, and forming conductive vias extending through the contact board connecting each of the second conductive pads and a third conductive pad;
and k, connecting the plurality of layers to the contact board such that each layer receiving channel receives and supports one of the layers in a direction substantially perpendicular to the second surface of the contact board, and in electrical communication. is performed between the third conductive pad and the integrated circuit structure. (17) isotropically etching the layer such that the crystal lattice structure of the layer extends parallel to the first surface of the layer;
17. The method of claim 16, comprising forming the layer as characterized by an orientation of 0 crystals. 18. The method of claim 17, wherein the V-shaped groove formed in each of the layers is formed to extend downwardly from the first surface of the layer at an angle of about 54 degrees. (19) The crystal lattice structure of the contact board extends perpendicularly to the second surface of the circuit board (100)
Claim 16 characterized by an orientation of the crystals of
The method described in. (20) isotropically etching the first vertical sidewalls of the trench further comprising applying a photoresist along the first surface of the contact board adjacent the first vertical edge surface; 17. The method of claim 16. (21) a second angled surface is formed to extend at an angle of about 36 degrees from the plane of the second surface of the wafer of the circuit board, the second angled surface extending longitudinally between adjacent grooves; Extends,
21. The method of claim 20, thereby separating portions of the first surface of the board of circuitry between the grooves. (22) a-e to form the second edge portion of each layer;
repeating the steps fj to form a second contact board; and repeating the steps f-j to form a second contact board; 17. The method of claim 16, further comprising repeating k steps to connect the layers. 23. The method of claim 16, further comprising applying at least one insulating adhesive land between the layers, the land serving to secure adjacent layers together.