JPH04181362A - Memory replacement type data processor - Google Patents

Abstract

PURPOSE:To eliminate the overhead of data transfer and to improve the throughput by connecting a memory to a rear processor after the processing of a front processor, and switching the connection of the memory. CONSTITUTION:Data after the processing of the front process is not transferred to the rear processor and the memory itself stored with the data processed by the front processor is switched and connected to the rear processor. Namely, a row data input processor P1 - an image output processor P5 are each connected to one of a 1st memories M1 - a 6th memory M6 and a switching control circuit 2 controls which process is connected to which memory. Consequently, there is neither a data transfer time nor a bus wait time and the throughput can be improved.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a memory exchange type data processing apparatus, and more particularly to a data processing apparatus in which memory exchange is performed instead of data transfer between a plurality of processors.

[Conventional technology]

Figure 2 shows the conventional image diagnostic equipment (CT, ~1R, etc.)
Give an example. This image diagnostic apparatus 51 operates as follows. A raw data input processor P1 sequentially stores raw data obtained by the observation device ts (scanner in the case of CT, magnet assembly in the case of MR) in the first memory M1. When the raw data for one image has been stored in the first memory M1, the raw data input processor P1 transfers the raw data to the bus arbitration circuit 5.
2, request data transfer. The bus arbitration circuit 52 permits the raw data input processor P1 to use the bus B when there is a transfer permission from the reconfigurable processor P2 and the bus B is vacant. The raw data processor P1 that has obtained this permission transfers the raw data stored in the first memory M1 to the second memory M2 via the bus B. The reconstruction processor P2 performs image reconstruction calculations on the raw data transferred to the second memory M2, and stores the reconstructed image data in the second memory M2. At this time,
The raw data input processor P1 stores the raw data of the next image in the first memory M1. When the image data is stored in the second memory M2, the reconstruction processor P2 transfers the image data from the second memory υM2 to the third memory M3 via the bus B in a manner similar to the above operation.
Transfer to. The compression processor P3 compresses the image data stored in the third memory M3, and stores the compressed data in the third memory M3. Then, in the same manner as the above operation, the compression processor P3 transfers the compressed data from the third memory M3 to the fourth memory M4 via the bus B. The processing processor P4 performs processing such as emphasis and smoothing on the compressed data stored in the fourth memory M4, and stores the processed data in the fourth memory M4. Then, in the same manner as above, the processed data is transferred to the fourth
Transfer from memory N14 to fifth memory M5. The image output processor P5 converts the processed data stored in the fifth memory M5 into an image and sends it to the display/storage device. The display/storage device displays and stores tomographic images of the human body. In the above conventional examples, data transfer is performed without using the common memory MC, or when data transfer is performed using the common memory MC, the transfer source processor transfers the data to be transferred from its own memory to the common memory. Transfer to memory MC. Then, the transfer destination processor takes out the data to be transferred from the common memory MC and moves it to its own memory. When using this common memory MC, there is an advantage that the operations of the transfer source processor and transfer destination processor can be made asynchronous.

[Invention or problem to be solved]

The conventional image diagnostic apparatus 51 described above has a problem in that data transfer is always required between the first-stage processing and the second-stage processing, and the data transfer time becomes an overhead. Also, if you try to transfer data from one memory to another and bus B is already in use, you will not be able to transfer data until bus B is finished, resulting in waiting time and overhead. There is a problem. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a memory exchange type data processing device that eliminates the overhead of data transfer by exchanging the memory itself instead of data transfer.

[Means to solve the problem]

The memory exchange type data processing device of the present invention includes a memory for storing data, a pre-processor for processing data, a post-processor for further processing data processed by the pre-processor, and a pre-processor for processing data. Before processing, the memory is connected to the previous processor so that the data processed by the previous processor can be stored, and after processing by the previous processor, the memory is connected to the latter processor so that the data can be retrieved by the latter processor. ,
A structural feature of the device is that it includes a memory exchange means for changing the connection of the memory. Note that in the above configuration, "first stage" and "second stage" refer to the time order in which data is processed, and do not mean the connection order. Therefore, the present invention is applicable even when the processors are connected in parallel. Also, each processor is a separate chip. It may be built into one chip.

[Operation] In the memory exchange type data processing device of the present invention, the data processed by the former processor is not transferred to the latter processor, but the memory itself storing the data processed by the former processor is connected to the latter processor. This eliminates data transfer time and bus waiting time.
Throughput can be improved.

【Example】

The present invention will now be explained in more detail with reference to embodiments shown in the drawings. Note that this invention is not limited to this. FIG. 1 shows an image diagnostic apparatus 1 according to an embodiment of the present invention. This image diagnostic apparatus 1 takes in raw data obtained by an observation device (scanner in CT, magnet assembly in MR, etc.) S by a raw data input cabro sezza P1, and performs image reconstruction calculations on the raw data by a reconstruction processor P2. a compression processor P3 compresses the image data, a processing processor performs image processing on the compressed data to generate desired image data,
This is a device that displays and saves an image in an image output processor P5 or a display/storage device based on the image data. The raw data input processor P1 to the image output processor P5 are connected to the first
It is connected to any one of the memory M1 to the sixth memory M6. The switching control circuit 2 controls which processor is connected to the memory. In FIG. 1, the opening at the intersection of the vertical line from each processor and the horizontal line from each memory represents a contactor, a circle in the middle of the day represents an oven of the contactor, and a mark represents a closed state of the contactor. Next, the operation will be explained. First, the switching control circuit 2 connects the raw data input processor P1 and the first memory M1. The raw data input processor P1 stores raw data taken in from the observation device S into first memories to 11. When the storage of one image worth of raw data in the first memory M1 is completed, the raw data input processor P1 notifies the switching control circuit 2 to that effect. The switching control circuit 2 changes the state of the cross switch XS to connect the raw data input filter processor P1 and the second memory M2, and connect the reconfiguration processor P2 and the first memory M1. Upon receiving this notification of connection completion, the raw data processor P1 takes in the raw data from the observation device S and stores it in the second memory M2. On the other hand, reconfiguration processor P2
performs reconstruction calculations on the raw data stored in the first memories to 11 to generate image data, and stores the generated image data in the first memory M1. When the raw data character processor P1 completes the processing of raw data characters for one image, the controller P1 switches the control circuit 2 to that effect.
Notify. Furthermore, when the reconstruction calculation for one image is completed, the reconstruction processor P notifies the switching control circuit 2 to that effect. Next, the switching control circuit 2 switches the state of the cross switch
The reconfiguration processor P2 and the second memory M2 are connected, and the compression processor P3 and the first memory M1 are connected. Upon receiving this notification of connection completion, the raw data input processor P1 transfers the raw data taken in from the observation device S to the third
The reconstruction processor P2 generates image data from the raw data stored in the second memory M2 and stores it in the second memory ~12, and the compression processor P3
generates compressed data from the image data stored in the first memory M1 and stores it in the first memory M1. Upon receiving notification of the completion of each operation from each processor, the switching control circuit 2 turns off the state of the cross switch xS.
Furthermore, the raw data input processor P1 and the fourth memory ~1
4, the reconfiguration processor P2 and the third memory M3
, the compression processor P3 and the second memory M2 are connected, and the processing processor P4 and the first memory M1 are connected. Upon receiving this notification of connection completion, the raw data input processor P1 stores the raw data in the fourth memory M4, and the reconstruction processor P2 generates image data from the raw data in the third memory M3 and stores it in the third memory. The compression processor I) 3 generates compressed data from the image data in the second memory M2 and stores it in the second memory M2, and the processing processor P
4 generates processed data from the compressed data in the first memory M1 and stores it in the first memory M1. Upon receiving notification of processing completion from each processor, the switching control circuit 2 switches the state of the cross switch xS, connects the raw data input processor P1 and the fifth memory M5, and connects the reconfiguration processor P2 and the fourth memory. , the compression processor P3 and the third memory M3 are connected, the processing processor P4 and the second memory M2 are connected, and the image output processor P5 and the first memory M1 are connected. The state shown in FIG. 1 shows this state. Upon receiving this notification of connection completion, the raw data processor P1 stores the raw data in the fifth memory M5, and the reconstruction processor P2 generates image data from the raw data in the fourth memory M4 and stores the raw data in the fourth memory M4. The compression processor P3 generates compressed data from the image data in the third memory M3 and stores it in the third memory M3, and the processing processor P4 generates processed data from the compressed data in the second memory M2. The image output processor P5 retrieves the processed data from the first memory M1, converts it into an image, and outputs it to a display/storage device. After that, the switching control circuit 2 sequentially switches to each processor P1.
-P5 and the memories M1 to M5, images are generated one after another and displayed/stored by the display/storage device. In the above embodiment, the processing of each processor is carried out synchronously, but by adding memory (for example, adding the sixth memory M6), it is also possible to make the operation of each processor asynchronous. be. Note that the cross switch XS and the switching control circuit 2 constitute memory exchange means. Since the connections between each processor and each memory can be switched independently of each other, one processor can read data from multiple memories, and one processor can also write data to multiple memories. The present invention is useful not only for image diagnostic apparatuses as described above but also for apparatuses that process a large amount of data, such as simulation apparatuses. It is also useful as an information exchange device between processors.

【Effect of the invention】

The memory exchange type data processing device of the present invention eliminates data transfer time and bus waiting time, thereby eliminating data transfer overhead and improving throughput.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a memory exchange type data processing device of the present invention, and FIG. 2 is a block diagram of an example of a conventional data processing device. (Explanation of symbols) 1...Memory exchange type data processing device 2...Switching control circuit S...Observation device D
...Display/storage device XS...Crossbar switches P1-P5...Processor M1-M6...Memory.

Claims (1)

[Scope of Claims] 1. A memory that stores data; a preprocessor that performs processing on the data; a postprocessor that further processes the data processed by the preprocessor; and a preprocessor that performs further processing on the data processed by the preprocessor; The memory is connected to the preceding processor so that the data processed by the preceding processor can be stored, and after processing by the preceding processor, the memory is connected to the subsequent processor so that the latter processor can retrieve the data. 1. A memory exchange type data processing device comprising memory exchange means for changing connections.