JPH04180265A - Solid-state image sensor - Google Patents

Abstract

PURPOSE:To reduce the chip size and the number of outer terminals of a chip by sharing shunt wirings which impress drive clock to the respective transfer electrodes of the image sensing part including a plurality of two-dimensionally arranged photosensing parts and vertical transfer parts and the accumulative parts consisting of vertical transfer parts. CONSTITUTION:A shunt wiring 4 to impress drive pulse on the respective transfer electrodes of vertical shift registers of an image-sensing part 1 and an accumulative part L are extended and shared by the image-sensing part 1 and the accumulative part 2. That is, the respective transfer electrodes of vertical shift registers of the image-sensing part 1 and the accumulative part 2 are impressed with drive pulse via shunt wirings 4 extending from the top end of the image- sensing part 1 to the bottom end of the accumulative part 2 in the vertical direction and via loop busline wirings 5. Therefore, even when the shunt wiring 4 is extended and shared by the image-sensing part 1 and the accumulative part 2, the whole of the image-sensing part 1 and the accumulative part 2 is supplied with drive pulse without propagation delay. This design reduces the chip size and the number of outer terminals of a chip.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to solid-state imaging devices, and particularly to FIT (Frame Interline T) which requires high-speed transfer.
transfer) type CCD solid-state imaging device.

<Summary of the Invention> The present invention provides a solid-state imaging device including an imaging section including a plurality of two-dimensionally arranged photosensitive sections and a vertical transfer section, and a storage section including a vertical transfer section. By sharing the shunt wiring for applying a drive clock to each transfer electrode in the imaging section and storage section, it is possible to reduce the chip size and the number of external terminals of the chip.

<Prior art> As is clear from FIG. 2, which shows the outline of its basic configuration, an FIT type CCD solid-state imaging device is arranged two-dimensionally in the vertical and horizontal directions (in the figure, directions ① and H) to adjust the amount of incident light. Multiple photosensitive parts (photosensors) that accumulate signal charges according to the
11 and a first vertical/foot register (vertical transfer section) 12 which is arranged in each vertical column and which vertically transfers signal charges read out from these photosensitive sections 11. It consists of a second vertical shift register 21 connected to the vertical shift register 12 in the section I for each column, and is provided with an accumulation section 2 that enables reduction of smear components by high-speed charge transfer. The entire surface of the storage section 2 is covered with a light-shielding layer made of aluminum and minilum layers.

In the vertical shift register 12 of the imaging section 1, a plurality of transfer electrodes (not shown) made of polysilicon are formed so as to be able to transfer signal charges in the vertical direction. Similarly, in the vertical shift register 21 of the storage section 2, a plurality of transfer electrodes (not shown) made of polysilicon are formed so as to be able to transfer signal charges in the vertical direction.

In the imaging section 1, signal charges of all pixels photoelectrically converted by the photosensitive section 11 are read out to a vertical shift register 12, and transferred by the register 12 to the storage section 2 at high speed. The signal charges transferred to the storage section 2 are transferred at high speed by a vertical shift register 21 to a horizontal shift register (horizontal transfer section) 3 in portions corresponding to one scanning line. The signal charges for one scanning line are sequentially transferred in the horizontal direction by the numbered horizontal shift register 3. At the final end of the horizontal shift register 3, there is an FDA (Floating Diffusio).
n A+++plifier), etc.
(not shown) is provided, and the signal charge obtained by photoelectric conversion in the imaging section 1 is derived as an image signal.

By the way, as a solid-state imaging device that can cope with the increasing number of pixels in television systems such as HD (high-definition) TV, there is an FIT type CCD solid-state imaging device with a 1-inch optical system and 2 million pixels.

In this 1-inch optical system FIT-type COD solid-state imaging device for HDTV, the load capacity of the vertical shift register (vertical CCD) is large due to the large chip area. vertical shift register 1
By separating the shunt wiring 13.22 for applying a driving pulse to each transfer electrode in 2.21 into the imaging section 1 and the storage section 2, the load capacitance for each shunt wiring 13.22 is halved and the driving pulse is This prevents propagation delays (see specification of Japanese Patent Application No. 2-42666 filed by the present applicant).
.

That is, four-phase drive pulses φV, to φv4 are applied to the transfer electrodes of the first vertical shift register 120 in the imaging unit 1 via the shunt wiring 13 extending in the vertical direction and the loop-shaped lot line wiring 14. It looks like this. The pass line wiring 14 is for commonly applying driving pulses φ9□ to φv4 to the plurality of shunt wirings 13, and has four wiring patterns 14. ~1
4. It consists of These wiring patterns 14. ~14
4, four-phase drive pulses φv are applied from external terminals (not shown) of the chip via bonding bands 151 to 154.
l to φv4 are applied.

On the other hand, the second vertical shift register 21 in the storage section 2
The transfer electrode includes a shunt wiring 22 extending horizontally.
and a four-phase drive pulse φ9. ~φv4 is applied.

The pass line wiring 23 is for commonly applying driving pulses φVl to φv4 to the plurality of shunt wirings 22, and has four wiring patterns 23+ to 234 corresponding to four phases.
It consists of These wiring patterns 23+ to 234 have bonding bands 24. ~244 via Ch.

A four-phase drive pulse φ9.
~φv4 is applied.

<Problem to be solved by the invention> In this way, the FIT type CC for HDTV with a 1-inch optical system
Since the D solid-state imaging device has a structure in which the junction wiring is separated between the imaging section 1 and the storage section 2, the wiring pattern of the pass line wiring 14.23 is applied to both the imaging section 1 and the storage section 2 at 141 to 144 degrees. It was necessary to form 23, to 234. For this purpose, the wiring pattern 14. ~144,23
1-234 and bonding pad 15. ~15. ,2
4, to 244, and an additional area is required to form the bonding pads 15. ~15,. 24.
~244 external terminals of the chip are required, so
This has been an obstacle to reducing the chip size and the number of terminals.

In particular, the drive pulse φ in the pass line wiring 14.23
Pass line wiring 1 to prevent propagation delay of vI~φv4
When 4.23 is looped, the wiring pattern 14.
~14. , 23. 234 is doubled, the wiring patterns 141 to I44 are
, 23. 234 will require approximately twice the area.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a solid-state imaging device in which the chip size can be reduced and the number of external terminals of the chip can be reduced as the size of the optical system is reduced.

<Means for Solving the Problems> In order to achieve the above object, a solid-state imaging device according to the present invention includes a plurality of photosensitive sections arranged two-dimensionally in vertical and horizontal directions and signals read from these photosensitive sections. The imaging section includes an imaging section including a first vertical transfer section that vertically transfers charges, and an accumulation section consisting of a second vertical transfer section continuous to the first vertical transfer section for each column. A configuration is adopted in which the shunt wiring for applying a drive clock to each transfer electrode of the storage section is shared by the imaging section and the storage section.

<Function> In the solid-state imaging device according to the present invention, the load capacity of the vertical shift register (vertical CCD) is reduced as the size of the optical system is reduced, so the shunt wiring is extended and shared between the imaging section and the storage section. However, the driving pulse can be supplied throughout the imaging section and storage section without causing any propagation delay.

By sharing the shunt wiring in the imaging section and the storage section, only one system of pass line wiring and bonding pads is required, so that the chip size can be reduced and the number of external terminals of the chip can be reduced.

<Example> Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 1 is a schematic plan view showing a shunt wiring structure of a solid-state imaging device according to the present invention. Note that the solid-state imaging device to which the present invention is applied is, for example, a FIT-type COD solid-state imaging device for HDTV with a 2/3-inch optical system. By reducing the size of the optical system from 1 inch to 2/3 inch,
The area of the imaging section 1 is reduced to 1/2, and the load capacity of the vertical shift register (vertical C0D) is also reduced to 1/2. The configuration is such that the shunt wiring 4 for applying a driving pulse to each transfer electrode of the shift register is extended and shared by the imaging section 1 and the storage section 2.

That is, each transfer electrode of the vertical shift register of the imaging section 1 and the storage section 2 has a shunt wiring 4 extending from the upper end of the imaging section 1 to the lower end of the storage section 2 in the vertical direction.
Four-phase driving pulses φv1 to φv4 are applied via the loop-shaped pass line wiring 5. The shunt wiring 4 is formed by micromachining the first aluminum layer, extends vertically on each vertical shift register, and is connected to each transfer electrode at multiple locations via contact holes. .

In this way, even if the shunt wiring 4 is shared by the imaging section 1 and the storage section 2, the load capacity of the vertical shift register will be reduced by half as the size of the optical system is reduced from 1 inch to 2/3 inch. Therefore, the driving pulses φvl to φ9. can be supplied to the entire imaging section 1 and storage section 2 without causing any propagation delay.

The pass line wiring 5 is formed into a rectangular loop shape whose longitudinal direction is the horizontal direction by processing the second aluminum layer forming the light shielding layer. The pass line wiring 5 is provided with a driving pulse φ9. -φv4, and consists of four wiring patterns 5I to 54 corresponding to four phases. These wiring patterns 51 to 54 have bonding pads 6 that are wire-bonded to external terminals of the chip.
, -64, four-phase drive pulses φv1 to φv4 are applied. These bonding pads 6° to 64 are made of a first layer of aluminum, and are patterned so that each wiring pattern 7, to 74 extends to the bottom of the corresponding wiring pattern 51 to 54 of the pass line wiring 5. The wiring patterns 51 to 54 are electrically connected to each other.

Since each of the wiring patterns 5I to 54 of the pass line wiring 5 has a horizontal direction as its longitudinal direction, it can be divided into 5 parts in the vertical direction by the center line 0 in the horizontal direction, and the wiring patterns 51 to 5
4, on the side farther from the imaging unit 1, the bonding pad 6, ~
A connection is made to the shunt wiring 4 on the side of the wiring patterns 5I to 54 that is closer to the imaging unit l. A large number of shunt wires 4 are formed for each register on the vertical shift registers of the imaging section 1 and the storage section 2.
is each wiring pattern 5. of the four pass line wirings 5. ~5
The phases among the four are connected to the corresponding wiring patterns.

Therefore, each shunt wiring 4 has a four-phase driving pulse φ9.
．． .about.φv1 having a corresponding phase are supplied to the transfer electrodes of the vertical shift registers via the shunt wiring 4, respectively. ~φv4 will be applied.

In the above embodiment, a four-phase drive method was used as an example of the CCD transfer drive method, but the present invention is not limited to this drive method (two-phase or other drive methods may be used).

<Effects of the Invention> As explained in detail above, in the solid-state imaging device according to the present invention, the shunt wiring for applying the drive pulse to the vertical transfer electrode is shared by the imaging section and the storage section, thereby achieving the following effects.
Since only one system of pass line wiring and bonding pads for supplying drive pulses to the shunt wiring is required, the chip size can be reduced and the number of external terminals of the chip can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view showing the shunt wiring structure of a solid-state imaging device according to the present invention, FIG. 2 is a schematic plan view showing the basic configuration of an FIT type CCD solid-state imaging device, and FIG. 3 is a conventional shunt wiring structure. FIG. 3 is a schematic plan view showing the structure. 1...Imaging section. 2...Storage section. 3...Horizontal shift register. 4.13.22...Shunt wiring. 5.14.23...Pass line wiring. 61-64.151-154,24. ~244...Ponding pad. 11...Photosensitive part. 12...First vertical shift register. 21...Second vertical shift register. Patent applicant Sony Corporation agent
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Claims (1)

[Scope of Claims] An imaging section including a plurality of photosensitive sections two-dimensionally arranged in vertical and horizontal directions and a first vertical transfer section that transfers signal charges read from these photosensitive sections in the vertical direction; The first vertical transfer section includes a storage section consisting of a second vertical transfer section continuous for each column, and a shunt wiring for applying a driving clock to each transfer electrode of the imaging section and the storage section. A solid-state imaging device characterized in that the imaging section and the storage section are shared.