JPH04180107A - Temperature compensating circuit and supply voltage generating circuit - Google Patents

Abstract

PURPOSE:To assure a normal operation as a whole even if the temperature exceeds a specification level range due to a local rise of temperature by detecting the temperature changes of plural function blocks as the changes of the transmission delayed values and changing the power voltage of each function block. CONSTITUTION:When the temperature rises with the actuation of a function block 110, the output current of a MOSTr of a delay means 101 reduces and the delayed time increases. Then the output of a reference signal generator means 104 changes and the output of an EXNOR 202 of a temperature detector means 103 also changes. A counter 203 generates a pulse for each N counting frequency of reference signals, and an OR circuit 210 generates a pulse where the delayed time width decided by a delay buffer 206 is added to the width of the pulse generated by the counter 20. An AND circuit 207 output a pulse having the delayed time width decided by the buffer 206. A Tr P1 is turned on and the voltage of a capacitor C1 rises when the output of the circuit 202 is set at an L level. Meanwhile a Tr P3 is turned on and a capacitor C2 is charged up to the same level of voltage as the capacitor C1 when the circuit 210 is set at an H level. At the junction between the C2 and the P3, the voltage dependent on the temperature change and proportional to the delayed time is generated and supplied to the block 110.

Description

[Detailed Description of the Invention] Industrial Fields of Application The present invention & Dai To deal with the case where a short-term local temperature rise occurs within the operating temperature range in a semiconductor integrated circuit that configures a plurality of functional blocks on one chip. Conventional technology for temperature compensation circuits to prevent malfunctions in the entire circuit and supply voltage generation circuits used in the circuits has also changed due to advancements in semiconductor integration technology. Even though it is widely practiced to integrate devices into one, there is no guarantee that the normal operation of these semiconductor integrated circuits will be affected by temperature changes.
It is common to detect only the ambient temperature or chip surface temperature of the chip, estimate the internal temperature of the chip from the measured value, and control the chip to stop operating if the temperature exceeds the specified temperature. Furthermore, in semiconductor integrated circuits, each functional block is designed with a temperature margin based on simulations from transistor characteristics within the specified temperature range. It is very difficult to monitor the temperature status of the circuit from the outside, and in the end, there was no other way than to measure it from outside the package and estimate the average temperature of each functional block.About the circuit voltage conversion circuit used for the supply voltage generation means!
Conventionally, the configuration shown in FIG. 6(a) is explained using FIG. 6. In FIG. 6(a), the power supply 6
02 is the source of the P type MOS transistor P1 and the N type M
O8) Connect the source of transistor N2 and connect the drain of N type M○S transistor Nl to the drain of Pi L
Ground the source of Nl & connect P-type MO to the drain of N2
Connect the source of S transistor P2 L Connect capacitor C2 to the drain of P2 L Connect the terminal of C2 not connected to P2 Ground the connection point of PL and Nl, and P2
and N2 are connected by a capacitor C1.The output of the oscillation means 601 is connected to PI, P2゜N1. To explain the operation of the above configuration, when the output of the oscillation means 601 is at a high level, the N-type MOS transistor is turned on and the P-type transistor is turned off.
A capacitor is connected as shown in FIG. 6(b), and the capacitor C1 is charged with the power supply voltage. Next, the oscillation means 6
When the output of 01 is low level, the N-type MOS transistor is turned off and the P-type transistor is turned on.The capacitors are connected as shown in Figure 6(c), and the capacitor C2 has twice the power supply voltage. 6(b), (
A voltage twice the power supply voltage may be generated at the ungrounded terminal of the capacitor C2, but by this principle, a voltage 200 million to 3 times the power supply voltage can be obtained. Problems to be Solved In the conventional semiconductor integrated circuit described above, the temperature distribution of the chip is uneven due to differences in the operating states of each functional block within the chip, and even if the temperature locally becomes high, the temperature detector cannot The temperature detected by the device is the ambient temperature outside the package.If the package has a large heat capacity or the thermal resistance between the chip and the package is large, accurate temperature detection may not be possible. Even if it is low, depending on the operating condition, some functional blocks may exceed the maximum operating temperature, and the reliability of normal operation as a whole is poor.Also, even if the temperature is within the specified temperature, the temperature between each functional block In addition, in the conventional voltage conversion circuit described above, the voltage to be converted is n of the power supply voltage. times (n is an integer), it is impossible to increase the voltage by an arbitrary value, and it is also impossible to decrease the voltage below the power supply voltage. A detector is not required, and when a local temperature rise occurs and only that block temporarily exceeds the specified temperature range, the
It is an object of the present invention to provide a temperature compensation circuit that can guarantee the normal operation of the whole. Means for Solving Problems The present invention (1) aims to provide a circuit, in a semiconductor integrated circuit having a plurality of functional blocks therein, a reference signal generating means for generating a reference signal, and a reference signal generating means for generating a reference signal; a delay means configured of a plurality of semiconductor active elements whose delay time changes depending on the temperature; and a delay means which takes the output of the delay means and the reference signal as input and outputs a pulse having a pulse width proportional to the delay time. a functional block having a temperature detection means consisting of a time detection means; a voltage conversion means that takes the output of the delay time detection means as an input and generates and holds a voltage depending on the pulse width; and an output of the voltage conversion means at a reference temperature. a reference voltage generating means that generates the same voltage as that of the reference voltage generating means, and comparing the output of the voltage converting means and the output of the reference voltage generating means, and determining whether the output voltage of the voltage converting means is the output of the reference voltage generating means or the output of the reference voltage generating means. a voltage comparing means outputting the higher of the two voltages, and inputting the output voltage of the voltage comparing means and the output voltage of the reference voltage generating means, and boosting the power supply voltage by the difference between them, and supplying the voltage to the functional block. The present invention (2) ζ also provides a temperature compensation circuit characterized by comprising a supply voltage generating means for supplying a boosted voltage.
．． V2. A first power supply that generates V3, a second power supply, an oscillation means that alternately outputs the first and second timings in a certain period, and switching according to the first and second timings of the oscillation means. multiple switching elements;
A fourth capacitor having terminals B at both ends of the capacitor is grounded; The B terminal of the first capacitor and the A terminal of the second capacitor are connected, the B terminal of the second capacitor and the A terminal of the fourth capacitor are connected, and the A terminal of the first capacitor and The A terminal of the third capacitor is grounded, and the second power supply and the third capacitor are connected to each other.
At the second timing, connect the first power source and the A terminal of the third capacitor; connect the third power source and the A terminal of the first capacitor; connect the third power source and the A terminal of the first capacitor; The B terminal of the first capacitor and the second capacitor
A supply voltage generation circuit characterized in that the A terminal of the capacitor is grounded, and the B terminal of the second capacitor and the B terminal of the third capacitor are connected. The temperature change of each of the multiple functional blocks configured on the chip is detected as a change in the amount of propagation delay, and the power supply voltage of each functional block is changed to compensate for the change, thereby detecting the change in delay time caused by the temperature change. It is possible to cancel this number.
There is no significant difference in the amount of signal delay between each functional block due to differences in temperature changes between each functional block, and there is no possibility of malfunctions such as mis-latching. Since temperature monitoring is performed every time, more accurate temperature monitoring is possible.In addition, since temperature detection is performed internally, there is no need for an external temperature sensor. voltage value v1,
V2. It is possible to obtain the voltage value of V1 + V2 - V3 from V3. Furthermore, there is no need to use a power supply with the opposite polarity! It is possible to obtain a power supply voltage lower by an arbitrary voltage. Embodiment (Embodiment 1) Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings. FIG. 1 shows Embodiment 1 of the present invention. Figure 2 is a detailed diagram of the temperature compensation circuit for one functional block in Figure 1. Figure 3 is a time chart of voltage changes at each point in Figure 2. Also in FIG. 1, delay means 101 and delay time detection means 1
02 constitutes the temperature detection means 103.
The output of the reference signal generation means 104 is inputted to the delay time detection means 102, and the output of the reference signal generation means 104 and the output of the delay means 101 are inputted to the delay time detection means 102, which generates a pulse having a pulse width proportional to the delay time. A voltage converting means 105 is provided which inputs the output of the temperature detecting means 103 of each of the functional blocks 110, 120, and 130 having the detecting means 103 therein. A supply voltage generating means 108 which receives the output of the voltage converting means 105 as an input, and a supply voltage generating means 108 which receives the output of the voltage comparing means 107 and the output of the reference voltage generating means 106 as inputs.
The outputs of multiple functional blocks 110, 120, 13 respectively
Next, in FIG. 2, the specific circuit of the temperature compensation circuit related to the functional block 110 of FIG. 1 will be described in detail. Delay means 101 connected in series
The output of the reference signal generating means 1.4 is input to the exclusive N0R202.The output of the delay means 101 and the output of the reference signal generating means 104 are input to the exclusive N0R202.Here, the exclusive N0R202 detects the delay time. This is means 102.

Next The configuration of the voltage conversion means 105 is as follows: P-type MOS transistors P1 and R2 are connected in series L The source of R2 is connected to the power supply L The capacitor CI is connected to the drain of PI L The terminal of C1 not connected to Pl is grounded. Mu
The source of a P-type MO5) transistor P3 and the drain of an N-type MO5h transistor Nl are connected to the connection point between Pl and CI. Connect the drain of R3 and capacitor C21. ,,C
Ground the terminal not connected to R3 of 2 -L Nl
The output of the counter 203, which receives the output of the reference signal generating means 104, is connected to the delay buffer 206.
, the inverter 204, and the inverted clock terminal of the D flip-flop with inverted reset 205. Counter 2
The output of the OR circuit 210 which inputs the output of 03 and the output of the delay buffer 206 is input to the gate of R2, the output of the inverter 204 is input to the gate of R3, and the output of the delay buffer 2o6 is the data of the D flip-flop 205. An AND circuit 207 whose inputs are the output of the 4D flip-flop 205 and the output of the delay buffer 206.
The output of the voltage converter 10 is inputted to the gate of N1 and the inverting reset terminal of the D flip-flop 205.
Input point it as 5 P-type MoS transistor P1
It is a gate of
Also, the output point number is the connection point between the P-type MOS transistor P3 and the capacitor c2.Then, the configuration of the reference voltage generation means 106 (↓ Even if the resistors R1 and R2 are connected in series between the power supply and ground), the output at this time is The point is the connection point between R1 and R2. Next, the configuration of the voltage comparison means 107 is as follows: Connect the connection point of R1 and R2 to the negative terminal of the comparator 208, and connect R3 and 02 to the positive terminal.
Enter the connection point. Connect the drain of P-type MOS transistor P4 and the drain of P-type MO5) transistor P5. Connect the source of R4 to the connection point of R3 and 02.
The source of R5 is connected to the connection point of R1 and R2. The inverted output of the comparator 208 is connected to the gate of R4 and the inverter 20.
9, input the output of the inverter 209 to the gate of R5 & input the connection point of R4 and R5 and the connection point of R1 and R2 to the supply voltage generation means 108, and input the output of the supply voltage generation means 10g to the function block 110. The operation of the above configuration will be explained with reference to FIG. 3. If the temperature of the functional block 110 rises due to the operating state, the output current of the MOS transistor in the delay means 101 will decrease and the delay time will increase. The output of the reference signal generating means 104 is changed as shown in FIG. 3(a) (the output of the delay means 101 is delayed as shown in FIG. 3(b)). The output of NOR is the third
The pulse counter 203, which changes as shown in FIG. 3(c), is a counter that generates a pulse as shown in FIG. 3(e) when the reference signal is counted N times.
The output of the OR circuit 210 (the output of the AND circuit 207 is as shown in FIG. (When the pulse output from the counter 203 falls, the delay buffer 206
Therefore, when the output of the OR circuit 210 is at a low level, a pulse with a delay time width determined by
1 P-type MO5) transistor P2 is in the on state,
N-type MOS transistor N1 and P-type MOS transistor P3 are in the off state. Therefore, when the counter 203 counts the reference signal N times, when the output of the exclusive N0R202 is at low level, the P-type MO8h transistor PI is turned on. state, the capacitor CI is charged and Pl and C
The voltage at the connection point I increases as shown in FIG. 3(d).

When the OR circuit 210 outputs a high level, the P-type MOS
The transistor P2 is in the off state, and while the counter 203 is outputting a high level, the P-type MOS transistor P
If the capacitance of capacitors C1 and C2 is CI)C2, C2 will be charged to the same voltage (V) as C1, but if the counter 203 returns to low level after this, the P-type M
OS transistor P3 turns off, and capacitor C
2, even if the voltage V is held as shown in FIG. 3(h), when the AND circuit 207 outputs a high level, the N-type MOS transistor N1 is turned on and the capacitor CI is discharged, returning to the initial state. , every time the reference signal is counted N times, the voltage (V) at the connection point between C2 and P3 is generated and maintained in proportion to the delay time depending on the temperature change within the function block 110. Function block 1 by dividing the power supply voltage by RLR2
Comparator 208 +i does not generate the same voltage (VT) as the voltage appearing at the connection point of 02 and P3 when 10 is at the reference temperature.
When the voltage at the positive terminal is higher than the voltage at the negative terminal, the inverted output outputs a low level; otherwise, it outputs a high level. Therefore, when V>VT, the P-type MOS transistor P4 is turned on, and the P-type MO3) transistor P5
is turned off, and the voltage at the connection point of P4 and P5 is reversed to V. When V<VT, P-type MO8) transistor P4 is turned off, P-type MO3) transistor P5 is turned on, and P4 and P
The voltage at the connection point 5 is VT.

A supply voltage generating means 10 g LL which receives the voltages Vl and VT at the connection point of P4 and P5 as inputs, converts the power supply voltage VO' in the functional block 110 to V 1- as shown in FIG.
Boost only VT and supply it to function block 11.04
When the temperature of the functional block 110 rises, Vl-VT becomes a positive value, the power supply voltage supplied to the functional block increases, the output current increases, and normal operation at the reference temperature is possible. In this way, according to the semiconductor integrated circuit of the present invention, it is possible to minimize malfunctions of functional blocks caused by local temperature changes between functional blocks.The present invention is limited to the above embodiments. Not a thing,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention. (Example 2) Next, FIG. Figure 5 is a circuit diagram showing the connection state of each capacitor in Figure 4. In Figure 4, the first power supply 401 is connected to the source of the P-type MOS transistor P4. and P4 drain +;L
t1 connected to the drain of the N-type MOS transistor N4,
The source of N4 is grounded, and the P-type MOS transistors P5 to P8 are connected in series, and the source of P5 (
Top t1 connected to the second power supply 402, drain of P8 (connected to capacitor C4, terminal not connected to P8 of C4 (connected to ground) 4 connection point of P4 and N4, connection point of P5 and P6 is coupled by capacitor C3, and connects the source of 4P type MO5h transistor P2 and the source of P type MOS transistor P3.
The drain of N2 is connected to the drain of N-type MOS transistor N2, and the source of N2 is grounded. Connect the drain of P3 and the drain of N-type MOS transistor N3,
Ground the source of N3 & connect the connection point of P3 and N3,
1 and the connection point of P8 are connected by a capacitor C2. Third
Connect the power supply 403 and the source of the P-type MOS transistor P1 L Connect the drain of PI and the drain of the N-type transistor N1 L Connect the source of Nl The connection point between Pi and N1 and the connection point between P2 and N2 capacitor C
3. The output of the oscillation means 404 is connected to the inverter 40.
5, and P-type MOS transistors P1, P4, P6, P
The output of the inverter 405 is input to the gate of the inverter 405 and the gate of the N-type MOS transistors N1 and N4.
The operation of the above configuration will be explained with reference to FIG. lz,
Oscillation means 40 that alternately outputs low level voltage
When the output of 4 is high level, switching element N1,
Since N4, P2, P3, P5, and P8 are in the on state and the others are in the off state, the capacitors C1 to C4, the first power source 401, the second power source 403, and the third power source 403 (see Figure 5a) When the output of the oscillation means 404 is at a low level, the switching elements N2, N3, P1,
Since P4, P6, and Pl are in the on state and the others are in the off state, the capacitors 01 to C4 and the first power supply 401,
Although the second power source 403 and the third power source 403 are connected as shown in FIG. 5(b), in FIG. 5(a), Ca Ji is charged with the output voltage V2 of the second power source 402, so C2 and 03 If the capacity of is C2 (C3), then 02ζ friend 1st
Even if it is charged to the voltage of the output voltage V1 + V2 of the power supply 401
At this time, even if C14L is charged with the output voltage v3 of the third power supply 403, when the phase shifts to Fig. 5(a), the capacitance of the capacitors C1, C2, and C4 becomes Cl=C2=2
*When C4 is charged, C4U is charged with a voltage of V 1 +V 2- V 3. Therefore, by turning the switching element on and off, the oscillation means causes a voltage of tL V 1 +V 2- V to the ungrounded terminal of capacitor C4.
3. The present invention is not limited to the above embodiments,
It is also possible to use elements other than MOS (MOS) transistors as switching elements (for example, bipolar transistors, phototransistors, etc.), and these are not excluded from the scope of the present invention. According to the present invention, a plurality of functional blocks exist in one chip, and a local temperature rise occurs in each functional block, changing the characteristics of the semiconductor active element and causing the functional block to malfunction. In such cases, it is possible to always keep the functional block operating normally by detecting changes in the delay time inside the L functional block and feeding it back to the power supply voltage.
Even if the temperature locally exceeds the specified temperature range, malfunctions will not occur. Malfunctions such as mislatches are eliminated, and higher reliability can be obtained.Sarabanmi The temperature change of the chip is detected internally and responded to.There is no need to install external temperature detection means, and the overall system Furthermore, according to the supply voltage generating means of the present invention, it is possible to supply a power supply voltage with higher accuracy than that in which the voltage value to be converted is continuous rather than discrete. Amo: Is it possible to subtract the voltage without using a power supply with negative voltage?
Furthermore, since addition and subtraction are performed simultaneously using simple oscillation means, it can be constructed with a small number of parts, and is superior in terms of cost and integration.

[Brief explanation of drawings]

FIG. 1 shows a schematic configuration of a temperature compensation circuit showing Embodiment 1 of the present invention. FIG. 2 shows details of a temperature compensation circuit for one functional block in FIG. 1. FIG. 4 is a time chart of voltage changes at points. FIG. 4 is a circuit diagram showing the configuration of the supply voltage generating means in FIG. 1, showing a second embodiment of the present invention. FIG. FIG. 6 is an explanatory diagram of the conventional supply voltage generation means. ...Voltage conversion performance 106...
・Reference voltage generation Sennari 107...Voltage comparison half-dead 10
8... Supply voltage generation means, 110, 120, 130
...Function block C1-C4...Capacitor,
P1-P8...P type MO3h Rungisu N1-N4
...N-type MOS transistors R1-R2... Name of the resisting agent Patent attorney Akira Okaji and two others Fig. 1 琶 龿 Ｇ Ｉ 日 9 ・C Fig. 5 Cα) Fig. 6 6θl ( b) (C-)

Claims (2)

[Claims] (1) A semiconductor integrated circuit having a plurality of functional blocks inside, comprising a reference signal generating means for generating a reference signal, and a plurality of semiconductor active elements to which the reference signal is input and whose delay time changes depending on temperature. a delay means;
a functional block having a temperature detection means including a delay time detection means which receives the output of the delay time and the reference signal as input and outputs a pulse having a pulse width proportional to the delay time; and the output of the delay time detection means as input. , a voltage converter that generates and holds a voltage that depends on the pulse width; a reference voltage generator that generates the same voltage as the voltage output by the voltage converter at a reference temperature; Comparing the output of the voltage generation means,
voltage comparison means for outputting either the output voltage of the voltage conversion means or the output voltage of the reference voltage generation means, whichever is higher; and voltage comparison means for outputting the output voltage of the voltage comparison means and the output voltage of the reference voltage generation means 1. A temperature compensation circuit, comprising: supply voltage generating means for increasing a power supply voltage by the difference between the input voltages and supplying the boosted voltage to the functional block. (2) A first power supply that generates voltages V1, V2, and V3;
A power supply, a third power supply, an oscillation means that alternately outputs first and second timings in a certain period, a plurality of switching elements that switch according to the first and second timings of the oscillation means, and a capacitor at both ends. It comprises first to third capacitors having terminals A and B, and a fourth capacitor whose terminal B is grounded among the terminals A and B at both ends of the capacitor, and at the first timing, the first capacitor B of the capacitor of
terminal and the A terminal of the second capacitor are connected, and the B terminal of the second capacitor and the A terminal of the fourth capacitor are connected.
the A terminal of the first capacitor and the A terminal of the third capacitor are grounded, the second power supply and the B terminal of the third capacitor are connected, and the second timing When the first power supply and the A terminal of the third capacitor are connected, the third power supply and the first
connect the A terminal of the capacitor, and ground the B terminal of the first capacitor and the A terminal of the second capacitor,
A supply voltage generation circuit characterized in that a B terminal of the second capacitor and a B terminal of the third capacitor are connected.