JPH04179259A - Solder plating apparatus for leads - Google Patents
Solder plating apparatus for leadsInfo
- Publication number
- JPH04179259A JPH04179259A JP30757790A JP30757790A JPH04179259A JP H04179259 A JPH04179259 A JP H04179259A JP 30757790 A JP30757790 A JP 30757790A JP 30757790 A JP30757790 A JP 30757790A JP H04179259 A JPH04179259 A JP H04179259A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- leads
- cathode
- rubber
- solder plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000007747 plating Methods 0.000 title claims abstract description 32
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 18
- 239000004020 conductor Substances 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims description 21
- 230000037431 insertion Effects 0.000 claims description 5
- 238000003780 insertion Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 3
- 239000007788 liquid Substances 0.000 abstract 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 4
- 238000003825 pressing Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005489 elastic deformation Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003756 stirring Methods 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
1産業上の利用分野」
この発明は、IC(半導体集積回路)等の半導体装置の
り−F’ (端T−)に゛I′田メノメツ施オリードの
’I’−HEノブキ装置に関する。[Detailed Description of the Invention] 1. Field of Industrial Application" This invention is directed to the 'I'-field of the 'I' field which is applied to the 'I' field (end T-) of a semiconductor device such as an IC (semiconductor integrated circuit). Regarding the HE knob device.
[従来の技術−1
従来より、第3図に示すようなりワットフラットパッケ
ージ(Q、 uadF laL P ackage)タ
イプの半導体装置をはじめとする各種半導体装Hにはa
’;板への単口]イ・1け作業の効率化を図るために、
予め各リードに半田層を形成している(例えば実開昭6
3−67261号公報参照)。[Conventional technology-1] Conventionally, various semiconductor devices H, including a watt flat package (Q) type semiconductor device as shown in FIG.
';Single entry to the board] A. In order to improve the efficiency of 1 entry work,
A solder layer is formed on each lead in advance (for example,
3-67261).
第4図は一ヒ記従来技術を収得し、電気メッキにより半
11コ層を形成する改良技術のリードの半田メッキ装置
の概略構成を示す正断面図である。この図において、2
はチタン材による陰極であり、略直方体状をなすと共に
、その−1一部は絶縁線によるカバー3によって覆われ
、そのF部(」半導体装置1の本体部1aに対応した形
状の凹部が形成されている。この凹部の周囲のチタン材
が本体部1aの4辺に配列した全てのり−F’lb、l
b の基部に当接するようにな−、)でいる。4は+
1) E E K U等の絶縁線による下受台であり、
その上部は中央部が除去されることにより、リード1.
b、 l b、・の各法部に当接する板状ff1s4
a、4a、 か形成されている。FIG. 4 is a front cross-sectional view showing a schematic structure of a lead solder plating apparatus which is an improved technology which acquires the prior art described above and forms half-eleven layers by electroplating. In this figure, 2
is a cathode made of titanium material, which has a substantially rectangular parallelepiped shape, part of which is covered with a cover 3 made of insulated wire, and a concave portion corresponding to the main body portion 1a of the semiconductor device 1 is formed in the F portion. All the titanium materials around this recess are arranged on the four sides of the main body 1a - F'lb, l
b so that it comes into contact with the base of b. 4 is +
1) It is a lower holder made of insulated wire such as E E K U,
By removing the central part of the upper part, lead 1.
Plate-shaped ff1s4 that comes into contact with each legal part of b, l b, ·
a, 4a, are formed.
また、下受台4はその断面積が下部へ向かう程小さくな
るように側部にテーパが形成されている。Further, the lower pedestal 4 is tapered at the side so that its cross-sectional area becomes smaller toward the bottom.
5は保持部材であり、下受台4のテーパ部と当接するす
り林状の凹部か形成されている。また、保持部材5の周
囲には陰極2と対向する位置に陽極6か設置Jられてい
る。Reference numeral 5 denotes a holding member, which is formed with a forest-like recessed portion that comes into contact with the tapered portion of the lower pedestal 4. Further, an anode 6 is installed around the holding member 5 at a position facing the cathode 2.
この半[1]メッキ装置による半田メッキは次のように
して行なわれる。リードフォーミングの完了した半導体
装置1は、下受台4に載せられ、その本体部1aの4辺
の各リード] b、 I b の基部が板状部4a、
4a、・によって下から支えられる。次いで、陰極2が
半導体装置1の」二に載せられ、陰極2の下面凹部の周
囲のチタン材と下受台4の板状部4 a、4 a、・に
よってリードI b、 l b、・が挾まれる。そ冒−
で、半導体装置1および陰極2の載置された1・゛受台
4が保持部材4のすり林状部に収納され、リードl b
、 I b、 と陽極6との間隔dがメッキ条件(電
流値、メッキ液温度、攪拌強さ、メッキ液成分、濃度等
)に応じて定まる、数mm〜数十mmのうちの適切な値
になるように、保持部材5が適度に挾みつけられる。こ
のようにして半導体装置1の装着が完了し、この半田メ
ッキ装置が半1]]メッキ液中に浸され、陰極2と陽極
6に電流が流される。Solder plating using this half [1] plating apparatus is performed as follows. The semiconductor device 1 on which lead forming has been completed is placed on the lower pedestal 4, and the bases of the leads on the four sides of the main body 1a]b, Ib are formed on the plate-like portion 4a,
It is supported from below by 4a,. Next, the cathode 2 is placed on the top of the semiconductor device 1, and the leads Ib, lb, . is caught. Sora-
Then, the pedestal 4 on which the semiconductor device 1 and the cathode 2 are mounted is housed in the slotted part of the holding member 4, and the lead l b
, Ib, and the anode 6 is determined depending on the plating conditions (current value, plating solution temperature, stirring strength, plating solution components, concentration, etc.), and is an appropriate value from several mm to several tens of mm. The holding member 5 is appropriately clamped so that In this way, the mounting of the semiconductor device 1 is completed, and the solder plating apparatus is immersed in half the plating solution, and a current is applied to the cathode 2 and the anode 6.
[発明が解決しようとするi題]
ところで、」二連した従来の半田メッキ装置において!
;11 、半導体装置1のり−F’ l b、 l b
、 に半田メッキを行った際に、各リードI b、
] b、 の間にハリの成長等が生じたり、また第5
図に示すように陰極2に半1−Bメッキ7か付着し、こ
れが各リードI b、 l b、 間をブリソノして
しまうという問題かあった。また、第5図に示すように
各り−1・1b、 I b、 の高さにバラツキにあ
るので、このバラツギによって一部のり一1’ I b
、 I b、 に給電が行なわれなかったり、また全
てのり−1・jb、 l b。[Problem to be solved by the invention] By the way, in the conventional two-way solder plating device!
;11, Semiconductor device 1 glue-F' l b, l b
, When solder plating is applied to each lead I b,
] b. Growth of firmness may occur during the 5th period.
As shown in the figure, there was a problem in that the semi-1-B plating 7 adhered to the cathode 2, and this caused a gap between the leads Ib and lb. In addition, as shown in Fig. 5, there are variations in the height of each glue -1.
, I b, is not supplied with power, or all nodes -1.jb, l b.
に給電が行わなれなかったりして、メッキ不良が生して
しまうという問題もあった。There was also the problem that power was not being supplied to the parts, resulting in plating defects.
この発明は上述した事情に鑑みてなされたもので、半導
体装置の各リードへのメッキのパリの成長等や、リード
間にブリシンが生じなく、さらにメッキ不良を起こすこ
とがないリードの半田メッキ装置を提供することを目的
としている。This invention has been made in view of the above-mentioned circumstances, and is a lead solder plating apparatus that prevents the growth of plating on each lead of a semiconductor device, prevents the formation of brittle between leads, and does not cause plating defects. is intended to provide.
「課題を解決するための手段−1
この発明は、半導体装置の周囲に配設された複数のリー
ドに当接する陰極と、前記各リードから離間配設された
陽極と、半田メッキ族とを具備し、前記半導体装置の各
リードに半田メッキを施すリードの半田メッキ装置にお
いて、前記陰極と前記各リードの基部との間に介挿され
前記各リードを加圧する方向に対して導電性を示す加圧
異方性導電材料からなる介挿部材を備えたことを特徴と
する。``Means for Solving the Problems-1 The present invention includes a cathode that comes into contact with a plurality of leads arranged around a semiconductor device, an anode that is spaced apart from each of the leads, and a solder plating group. In the lead solder plating apparatus that performs solder plating on each lead of the semiconductor device, a pressurizer is inserted between the cathode and the base of each lead and exhibits conductivity in the direction in which the leads are pressurized. It is characterized in that it includes an insertion member made of a pressure anisotropic conductive material.
1作用 −1
−1−記構成によれば、加圧異方性導電性材料からなる
介挿部材を陰極と半導体装置の各リードの基部との間に
介挿することにより、各リードの高さのバラツキが吸収
されるので、給電不良が生じることがない。すなわち、
加圧異方性導電材料からなる介装部材には、導通状態と
なる加圧力の下限値が存在し、各リードの高さに違いが
あっても、介装部材がその違いに応して変形するので、
全てのリードを上記下限加圧13以上の加圧力で抑圧す
るよう働くのである。介装部材の弾性変形に着目したも
のである。1 Effect -1 According to the configuration described in -1-, the height of each lead is increased by inserting the insertion member made of a pressurized anisotropic conductive material between the cathode and the base of each lead of the semiconductor device. Since variations in power are absorbed, power supply failures do not occur. That is,
An intervening member made of a pressurized anisotropic conductive material has a lower limit value of the applied pressure that becomes conductive, and even if the height of each lead differs, the intervening member will respond to the difference. Because it deforms,
It works so that all the leads are suppressed with a pressure equal to or higher than the lower limit pressure 13. This focuses on the elastic deformation of the intervening member.
「実施例」
以下、図面を参照してこの発明の実施例について説明す
る。"Embodiments" Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第1図はこの発明の一実施例によるリードの半田メッキ
装置の要部の概略構成を示す正断面図である。この図に
示すように、陰極2と半導体装置1のリードl b、
I b、・の基部との間に加圧異方性導電ゴム(加圧異
方性導電材料)10が介挿されている点が前述した第4
図に示す従来の装置と異なっている。なお、この加圧異
方性導電ゴム10以外の他の部分は共通している。この
加圧異方性導電ゴム10は加圧作用方向に対してのみ導
電性を示す性質を有するしのであり、これを陰極2と半
導体装置1のリードl b、 I b、・の基部との間
に介挿して陰極2によるリードlb、++〕、・を押え
る方向に圧力を加えることにより、この圧力方向に対し
て導電性を示す。この場合、第2図に示すように、加圧
異方性導電ゴノ・10の金属粒子バス12,12、 の
互いに接触する部分か導通状態になる。FIG. 1 is a front sectional view showing a schematic configuration of the main parts of a lead solder plating apparatus according to an embodiment of the present invention. As shown in this figure, the cathode 2 and the lead l b of the semiconductor device 1,
The point that the pressurized anisotropic conductive rubber (pressurized anisotropic conductive material) 10 is inserted between the base of the I b, .
This is different from the conventional device shown in the figure. Note that the other parts other than the pressurized anisotropic conductive rubber 10 are common. This pressurized anisotropic conductive rubber 10 has a property of exhibiting conductivity only in the direction of pressurization, and is used between the cathode 2 and the base of the leads l b, I b, · of the semiconductor device 1. By applying pressure in the direction of pressing the leads lb, ++], and by the cathode 2 inserted between them, conductivity is exhibited in this pressure direction. In this case, as shown in FIG. 2, the portions of the metal particle buses 12, 12 of the pressurized anisotropic conductive gonograph 10 that are in contact with each other become electrically conductive.
このような加圧異方性導電ゴム1oを陰極2と半導体装
置1のり−1”lb、lb、−の基部との間に介挿し、
これを介してリードlb、Ib、・に圧力を加えると、
第2図に示すように同ゴム10が押しつぶされ、その一
部分10a、IOa、 かり−F’ 1b、 l I
ll、 の各間に押し出される。この押し出された一
部分10a、lOa、 がり−1” 1 b、 I
b、ノ各間をシールするので、各り−F l l)、
l b、 の間にメッキ液か浸透しない。これにより
、各リード11、)、 l 1)、・の間にブリシンが
生ぜず、またパリの成長か生じない。また、加圧異方性
導電性ゴA I Oの陰極2とり−J:’ l bとに
上る加圧部のみが導電性を示すので、各り−F’ l
b、 l b、 の高さのバラツギを吸収でき、給電
不良か防止される。Such a pressurized anisotropic conductive rubber 1o is inserted between the cathode 2 and the base of the semiconductor device 1 glue -1"lb, lb, -,
When pressure is applied to leads lb, Ib, · through this,
As shown in FIG. 2, the rubber 10 is crushed, and a part of it 10a, IOa, Kari-F' 1b, l I
It is pushed out between ll and . This extruded portion 10a, 1Oa, 1" 1b, I
b, Since each space is sealed, each -F l l),
The plating solution does not penetrate between lb and . As a result, no blycine is generated between each lead 11, ), l1), and no growth of paris occurs. In addition, since only the pressurized part that rises to the cathode 2 of the pressurized anisotropic conductive go A IO -J:' l b exhibits conductivity, each -F' l
It is possible to absorb variations in the heights of b, l b, and prevent power supply failures.
「発明の効果」
以1−説明したようにこの発明のリードの半田メソ−ヤ
装置によれば、陰極と半導体装置の各り一1’の基部と
の間に加圧作用方向に対して導電性を示す加圧異方性導
電ゴムからなる介挿部材を設たので、介挿部側の加圧さ
れる陰極とリードとの間のみ導電性を示すので、半導体
装置の各リードの高さのバラツギか吸収され、給電不良
ら生じることがない。``Effects of the Invention'' As described in 1-1 above, according to the lead soldering device of the present invention, there is no electrical conductivity between the cathode and the base of each 1' of the semiconductor device in the direction of pressure action. Since we have provided an insert member made of pressurized anisotropic conductive rubber that exhibits conductivity, it exhibits conductivity only between the pressurized cathode on the insertion part side and the lead, so the height of each lead of the semiconductor device can be reduced. Variations in power are absorbed, and power supply failures do not occur.
また、この介挿部材を介して各り−1・を加圧すること
により同部材か各リード間に押し出され、各リード間を
シールする。これにより、各リードの間へのメッキ液の
浸透が起こらない。また、メッキ液の浸透が起こらない
ことから各リード間でパリの成長ら生じない。Further, by applying pressure to each member -1 through this insertion member, the member is pushed out between each lead, thereby sealing between each lead. This prevents the plating solution from penetrating between the leads. In addition, since the plating solution does not penetrate, there is no growth of paris between the leads.
第1図はこの発明の一実施例によるリードの半田メッキ
装置の要部の概略構成を示す正断面図、第2図は同要部
の一部拡大図、第3図はクワノドフラノトバッケーンタ
イプの半導体装置を示す斜視閲、第4図は従来のリード
の半[lメッキ装置の概略構成を示す正断面図、第5図
は同装置の一部拡大図である。
1114導体装置、
2 陰極、
l b、 + 11. ・ リード、4 ]パ
受台、
6 陽極、
10 介挿部材。FIG. 1 is a front sectional view showing a schematic configuration of the main parts of a lead solder plating apparatus according to an embodiment of the present invention, FIG. 2 is a partially enlarged view of the main parts, and FIG. FIG. 4 is a front sectional view showing the schematic structure of a conventional lead half plating device, and FIG. 5 is a partially enlarged view of the same device. 1114 conductor device, 2 cathode, l b, + 11.・Lead, 4] Pa holder, 6 Anode, 10 Insert member.
Claims (1)
る陰極と、 前記各リードから離間配設された陽極と、 半田メッキ液と、 を具備し、前記半導体装置の各リードに半田メッキを施
すリードの半田メッキ装置において、前記陰極と前記各
リードの基部との間に介挿され前記各リードを加圧する
方向に対して導電性を示す加圧異方性導電材料からなる
介挿部材を備えたことを特徴とするリードの半田メッキ
装置。[Scope of Claims] A cathode that comes into contact with a plurality of leads arranged around a semiconductor device, an anode that is spaced apart from each of the leads, and a solder plating solution, and each of the semiconductor devices In a lead solder plating apparatus that applies solder plating to the leads, the material is made of a pressure anisotropic conductive material that is interposed between the cathode and the base of each lead and exhibits conductivity in the direction in which each lead is pressed. A lead solder plating device characterized by comprising an insertion member.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2307577A JP2522110B2 (en) | 1990-11-14 | 1990-11-14 | Lead solder plating equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2307577A JP2522110B2 (en) | 1990-11-14 | 1990-11-14 | Lead solder plating equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04179259A true JPH04179259A (en) | 1992-06-25 |
JP2522110B2 JP2522110B2 (en) | 1996-08-07 |
Family
ID=17970754
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2307577A Expired - Fee Related JP2522110B2 (en) | 1990-11-14 | 1990-11-14 | Lead solder plating equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2522110B2 (en) |
-
1990
- 1990-11-14 JP JP2307577A patent/JP2522110B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2522110B2 (en) | 1996-08-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |