JPH04179248A - Production of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the occurrence of wafers without good products by using a reticle designed to expose multiple chip patterns with different pattern measurements in one exposure to form multiple chips and then applying the results of chip feature measurements for these chips to achieve the optimal pattern measurements. CONSTITUTION:When a reticle 1 is used to create the 3 chips 1A, 1B, and 1C with different pattern measurements, the gate has the greatest effect on FET device characteristics and requires the most precise line width control. By adjusting the gate line widths to be, for example, 0.90, 0.85, and 0.80mum, FET devices with dramatically different characteristics can be achieved. In this case, the reticle 1 for forming the gates should be designed with 4.50mum for a chip 11, 4.25mum for a chip 12, and 4.00mum for a chip 13 at X5 size. As a result. when this type of reticle is used for exposure, there is no need to change any other processes.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a method for setting optimal pattern dimensions in a trial production process.

The aim is to easily control pattern line width without changing manufacturing conditions other than the photo process, and to eliminate wafers that fail to produce good quality products.

The present invention is configured to include the steps of forming a plurality of chips using a reticle that exposes patterns of a plurality of chips having different pattern dimensions in one exposure, and determining an optimum pattern dimension from the results of measuring the characteristics of these chips.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for setting optimum pattern dimensions during a trial manufacturing process.

In recent years, as semiconductor devices have become highly integrated and miniaturized, control of manufacturing processes is required to be more accurate than physical and chemical limits.

The present invention can be used as a manufacturing method that meets this requirement.

[Conventional technology]

In the conventional manufacturing of semiconductor devices, very strict management has been carried out in order to perform control exceeding the above-mentioned limits.

As a result, product throughput decreases, negatively impacting the flow of manufacturing lines and development periods for advanced products.

It was happening.

Furthermore, in setting the design and manufacturing conditions, feedback is required to the process after going through the wafer process and checking in the test process, so there is a high possibility that a large amount of loss will occur during that time.

[Problem to be solved by the invention] Conventionally, the optimal dimensions for device pattern design have been determined by automatic computer design.

” 1), the optimum design value is insufficient, and delicate line width control of the device pattern, ion implantation dose, annealing conditions, etc. must be adopted. Control is performed to improve device characteristics.

Therefore, one object of the present invention is to make it possible to easily control the line width of a pattern in the process of prototyping a product in which a plurality of chips are exposed in one exposure, and to eliminate wafers that cannot be made into good quality.

[Failure to solve the problem]

The solution to problem 1 is to form multiple chips using a reticle that exposes multiple chip patterns with different pattern dimensions in a single exposure, and then determine the optimal pattern dimensions from the results of measuring the characteristics of these chips. This is achieved by a method for manufacturing a semiconductor device that includes steps.

[Effect]

In the present invention, since it is difficult to vary the manufacturing conditions in detail in the prototyping process of semiconductor devices, the pattern dimensions of each chip in the reticle are changed so that the device characteristics change even if manufactured under the same conditions. In this way, the process can obtain chips with different characteristics under exactly the same conditions.

The optimum pattern can be found by checking these chips.

In the present invention, since delicate line width control is performed by the reticle itself, there is little influence on processes other than exposure. Also, the reticle is normally x5. Since it is drawn at a magnification of x10, it is easy to control the line width on the reticle.

〔Example〕

FIG. 1 is a plan view of a reticle according to an embodiment of the present invention.

A case will be described in which the reticle 1 is composed of, for example, three chips IA, IB, and IC having different pattern dimensions.

For FETs, it has the greatest impact on device characteristics.

Gates require precise control of line width.

Set the line width of the gate to 2 e.g. 0.90.0.85.0.80
By changing the value to μm, FETs with significantly different characteristics (speed) can be obtained.

In this case, the reticle 1 for forming the game I is 4.50 μm for the chip 11 and 4.2 μm for the chip 12 when the size is
The line width of the chip 13 may be 4.00 μm.

As a result, it is only necessary to use the above-mentioned reticle during exposure, and there is no need to change any other processes.

Next, two specific examples showing the effects of the present invention will be described.

Select IM bit SRAM as the target.

This product has strict device characteristics, especially speed, and the target line width (standard) for the gate line width is 0.95±0.05 μm in production lots.

On the other hand, resist 1~film is 0.85±0.05μm
standards.

As a result, it is possible to obtain a version with a speed of 25 ns based on computer simulation data due to the design, but if the width exceeds 0.95 μm, the speed will be 25 ns.
The ns version cannot be changed (however, the 35ns version can be changed).

On the other hand, if the line width becomes thinner than 0.90 μm, no product can be obtained at all.

In other words, to obtain the desired 25 ns version, there was only a very narrow range of conditions, or it is not uncommon for more than 50 experimental lots to be run to obtain this condition, and these were reduced to 5 to 10 lots. If it can be reduced, it will greatly contribute to shortening the development cycle and lowering manufacturing costs.

Also, if you are not able to obtain a good product, is it a process problem or a design problem?
Did it take you a long time to figure out what the problem was?

According to the present invention, since a large number of conditions (characteristics) can be obtained in 10 tests, it is possible to obtain information in a short time with a small number of experimental lots, which greatly contributes to failure analysis technology.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to easily control the line width of a pattern in the prototyping process of a product that exposes multiple chips in one exposure, and it is possible to eliminate wafers that cannot be made into good quality. did it.

In other words, at the initial prototyping stage, samples with various characteristics can be obtained by simply running a small lot through the process.
It is now possible to check each sample to determine the optimum linewidth.

Moreover, the stability of the current process will remain unchanged in the future.

As the degree of integration increases, it may be expected that a slight deviation in the manufacturing conditions will result in a failure to produce a good product.In that case, unless the accuracy of processes other than the exposure process can be improved, application of the present invention may be unnecessary. It can be predicted that it is impossible to manufacture.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a reticle according to an embodiment of the present invention. In fig. 1 is the reticle.

Claims (1)

[Claims] It is characterized by having a step of forming a plurality of chips using a reticle that exposes patterns of a plurality of chips having different pattern dimensions in one exposure, and determining an optimum pattern dimension from the results of measuring the characteristics of these chips. A method for manufacturing a semiconductor device.