JPH04178633A - Formation of semiconductor circuit - Google Patents
Formation of semiconductor circuitInfo
- Publication number
- JPH04178633A JPH04178633A JP2306269A JP30626990A JPH04178633A JP H04178633 A JPH04178633 A JP H04178633A JP 2306269 A JP2306269 A JP 2306269A JP 30626990 A JP30626990 A JP 30626990A JP H04178633 A JPH04178633 A JP H04178633A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- film
- circuits
- circuit
- active matrix
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 84
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 20
- 238000010030 laminating Methods 0.000 claims 1
- 239000011159 matrix material Substances 0.000 abstract description 24
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 abstract description 16
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 16
- 239000011733 molybdenum Substances 0.000 abstract description 16
- 238000005498 polishing Methods 0.000 abstract description 11
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 abstract description 5
- 238000012546 transfer Methods 0.000 abstract description 4
- 239000000853 adhesive Substances 0.000 abstract description 3
- 230000001070 adhesive effect Effects 0.000 abstract description 3
- 229920002799 BoPET Polymers 0.000 abstract description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 239000004593 Epoxy Substances 0.000 abstract 1
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 43
- 239000011521 glass Substances 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 230000009975 flexible effect Effects 0.000 description 5
- 229920000139 polyethylene terephthalate Polymers 0.000 description 5
- 239000005020 polyethylene terephthalate Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- WUKWITHWXAAZEY-UHFFFAOYSA-L calcium difluoride Chemical compound [F-].[F-].[Ca+2] WUKWITHWXAAZEY-UHFFFAOYSA-L 0.000 description 4
- 229910001634 calcium fluoride Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 239000004983 Polymer Dispersed Liquid Crystal Substances 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052783 alkali metal Inorganic materials 0.000 description 1
- 150000001340 alkali metals Chemical class 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- -1 polyethylene terephthalate Polymers 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は半導体回路の形成方法に係り、特に、基板の材
質に制約のない半導体回路の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for forming a semiconductor circuit, and particularly to a method for forming a semiconductor circuit without restrictions on the material of a substrate.
[従来の技術1
液晶デイスプレィ(LCD)に代表される薄型で低消費
電力の平面型表示装置(デイスプレィ)の研究開発が盛
んである。これらのデイスプレィでは、配線が形成され
た基板、または高表示品質を得るために、能動素子(ア
モルファスS1薄膜トランジスタ(a−3i TFT
)や多結晶S1薄膜トランジスタ[poly −S i
T F 7N )を作り込んだアクティブマトリク
ス基板が必要であり、配線やアクティブマトリクスが形
成される基板材料にはガラスが用いられるのが一般的で
あった。[Prior Art 1] Research and development of flat display devices (displays), which are thin and have low power consumption, such as liquid crystal displays (LCDs), are actively being conducted. These displays use substrates with wiring or active elements (amorphous S1 thin film transistors (A-3I TFTs) to obtain high display quality.
) and polycrystalline S1 thin film transistors [poly-Si
An active matrix substrate incorporating T F 7N is required, and glass is generally used as the substrate material on which the wiring and active matrix are formed.
しかし、ガラスではその耐熱温度に制約があり、上記配
線や能動素子の製作に大きな制約を課していた。すなわ
ち、安価なガラスの耐熱温度は概して低く、また能動素
子に悪影響を与えるアルカリ金属の含有が避けられない
。このため、不純物含有が少なく、耐熱温度の高い安価
なガラス基板の開発が要請されているが、これらの要求
を満たすガラスの開発がままならない。一方、ガラス基
板を用いるとその剛性のためデイスプレィを未使用時に
小さく折り畳んでおくことができない問題があった。し
たがって、未使用時には小さく折り畳むことができるフ
レキシブル基板を用いたデイスプレィの出現が待望され
ている。However, glass has limitations in its heat resistance, which imposes significant restrictions on the production of the wiring and active elements. That is, the heat resistance temperature of inexpensive glass is generally low, and it is inevitable that it contains alkali metals that adversely affect active elements. For this reason, there is a demand for the development of inexpensive glass substrates that contain fewer impurities and have a high heat resistance, but there is still no progress in developing glasses that meet these demands. On the other hand, when a glass substrate is used, there is a problem that the display cannot be folded up into a small size when not in use due to its rigidity. Therefore, a display using a flexible substrate that can be folded into a small size when not in use is eagerly awaited.
基板の制約を取り除く技術としては、1989年のイン
ターナショナルエレクトヨシ デバイスミーディング(
Internationa、I ElectronDe
vice Meeting (IEDM))にデバイス
転載技術が報告されている(ケイ・スミヨシ(K、 S
umiyoshi、)他、[デバイス レイア トラン
スフアートポリ−シリコンティーエフティーアレイ フ
ォーハイ レゾル−ジョン リキッドクリスタルプロジ
ェクタ−(”DEVICE LAYERTRANSFE
RED POLY−5iTFT ARRAY FO
RHl(J RESOLUTION LTQIJI
DCRYSTAL PROJECTOR”)J 、アイ
イーデイ−エム(IEDM)89. p、165.19
89)。As a technology to remove board constraints, International Electric Yoshi Device Meading (1989)
Internationala, I ElectronDe
device reprinting technology has been reported in Vice Meeting (IEDM) (K. Sumiyoshi (K, S.
umiyoshi, ) et al., [DEVICE LAYERTANSFE
RED POLY-5iTFT ARRAY FO
RHl(J RESOLUTION LTQIJI
DCRYSTAL PROJECTOR”) J, IEDM 89.p, 165.19
89).
1発明が解決しようとする課題]
上記の技術は81基板上に酸化膜(SiC,膜)を介し
てアクティブマトリクスを製作したのち、別の基板と張
り合わせ、その後81基板を研磨工程で除去するもので
ある。研磨工程ではSlより8101の研磨速度が小さ
いため、S10.が現われたところで研磨を止めること
ができ、結果として81基板」−に形成したデバイスを
別の基板上に転載することができる。上記報告では同じ
工程を2回用い、まず別のSi基板に転載したのち、次
にガラス基板に転載している。これは、デバイスの天地
反転を防止するためで本質ではない。この方法では、ア
クティブマトリクスを製作する基板として耐熱温度の高
いS】基板を用いることができるため、マトリクス製作
における製作温度の制約が少なく、高温度で高性能のT
FTの作製を可能にする利点があるが、研磨を用いて転
載を行うため、剛性のないフレキシブル基板に転載しよ
うとするとSi基板が研磨により薄くなるにしたがって
基板が変形し、研磨が均一にできないという根本的問題
があった。さらに、コストの高い研磨装置を準備しなけ
ればならない問題があった。1. Problems to be Solved by the Invention] The above technology fabricates an active matrix on the 81 substrate via an oxide film (SiC, film), then attaches it to another substrate, and then removes the 81 substrate in a polishing process. It is. In the polishing process, since the polishing rate of 8101 is lower than that of Sl, S10. The polishing can be stopped when the 81-substrate appears, and as a result, the device formed on the 81-substrate can be transferred onto another substrate. In the above report, the same process was used twice, first transferring to another Si substrate and then transferring to a glass substrate. This is to prevent the device from turning over, but is not essential. In this method, a high-temperature S] substrate with high heat resistance can be used as the substrate for fabricating the active matrix, so there are fewer restrictions on the fabrication temperature in matrix fabrication.
It has the advantage of making it possible to fabricate FT, but since the transfer is performed using polishing, if you try to transfer it onto a flexible substrate that has no rigidity, the substrate will deform as the Si substrate becomes thinner due to polishing, making it impossible to polish uniformly. There was a fundamental problem. Furthermore, there is a problem in that an expensive polishing device must be prepared.
本発明の目的は、上記問題を解決し、基板に対する制約
のない回路の転載方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and provide a method for reprinting a circuit without restrictions on the substrate.
[課題を解決するための手段]
本発明は、基板上に形成した回路と基板との間に介在さ
せた膜をエツチングで除去する方法を用いる。この膜の
エツチング速度が大きく、製作した回路、デバイスや基
板に対してこの膜を選択的に除去できれば回路、デバイ
スの転載が可能である。[Means for Solving the Problems] The present invention uses a method of removing by etching a film interposed between a circuit formed on a substrate and the substrate. If this film has a high etching speed and can be selectively removed from manufactured circuits, devices, or substrates, the circuits and devices can be reprinted.
すなわち、本発明の半導体回路の形成方法は、第1の膜
、または第1の膜および少なくとも1層の第2の膜を介
して回路を形成した第1の基板を上記回路を形成した側
で第2の基板に張り合わせたのち、上記第1の膜をエツ
チングにより除去することにより」二記回路を上記第2
の基板上に転載することを特徴とする。That is, in the method for forming a semiconductor circuit of the present invention, a first substrate on which a circuit is formed via a first film, or a first film and at least one layer of a second film is placed on the side on which the circuit is formed. After attaching the first film to the second substrate, the first film is removed by etching to form the second circuit.
It is characterized by being transferred onto a board.
し作用]
本発明では、回路を形成する基板に耐熱温度が高い基板
や、回路に悪影響を与える物質を含まない基板を用いる
ことができ、基板の制約を少なくすることができる。ま
た、回路を転載するのに、従来技術のように研磨を行わ
なくて済むので、コストの高い研磨装置が不用であり、
かつ剛性のないフレキシブル基板に転載しようとする場
合も基板が変形する問題もない。Effect] In the present invention, it is possible to use a substrate with a high heat resistance or a substrate that does not contain substances that adversely affect the circuit as a substrate forming a circuit, and it is possible to reduce restrictions on the substrate. In addition, unlike conventional technology, polishing is not required when reprinting a circuit, so expensive polishing equipment is not required.
In addition, even when attempting to transfer onto a flexible substrate without rigidity, there is no problem of the substrate deforming.
[実施例]
実施例1
第1図(a)〜(f)は、本発明の半導体回路の形成方
法の第1の実施例の工程断面図である。[Example] Example 1 FIGS. 1(a) to 1(f) are process cross-sectional views of a first example of the method for forming a semiconductor circuit of the present invention.
本実施例では、例えば4インチ径の81の第1の基板上
に回路としてアクティブマトリクスを形成し、ポリエチ
レンテレフタレート(PUT)の第2の基板上に転載し
た例を示す。In this embodiment, an example is shown in which an active matrix is formed as a circuit on a first substrate 81 having a diameter of 4 inches, and is transferred onto a second substrate made of polyethylene terephthalate (PUT).
まず、第1図(a)に示すように、Siの第1の基板l
l上に第1の膜12としてモリブデン膜を約〕μm堆積
する。次いで、(b)に示すように、製作工程中にモリ
ブデン膜12が酸化性雰囲気に曝されないよう、第2の
膜13としてSi、O,膜を堆積したのち、通常のアク
ティブマトリクス製作法でa−3iを用いたTFT17
およびIT○(酸化インジウム錫)の画素電極18、A
1の配線を形成し、アクティブマトリクス14を製作す
る。次いで、(c)に示すように、例えばエポキシ系の
接着剤15をアクティブマトリクス14上に塗布し、(
d)に示すように第2の基板]6としてPETMを回路
上に張り合わせる。First, as shown in FIG. 1(a), a first substrate l of Si is prepared.
A molybdenum film is deposited as a first film 12 on the substrate 1 to a thickness of about 1 μm. Next, as shown in (b), in order to prevent the molybdenum film 12 from being exposed to an oxidizing atmosphere during the manufacturing process, Si, O, and other films are deposited as the second film 13, and then a film is deposited using a normal active matrix manufacturing method. -TFT17 using 3i
and IT○ (indium tin oxide) pixel electrode 18, A
1 wiring is formed, and the active matrix 14 is manufactured. Next, as shown in (c), for example, an epoxy adhesive 15 is applied onto the active matrix 14, and (
As shown in d), PETM is laminated on the circuit as a second substrate]6.
その後、過酸化水素水中に浸漬し、(e)に示すように
モリブデン膜12をエツチングする。このとき、エツチ
ング速度を向上させるためエツチング液は加熱した。こ
のようにしてエツチングを進行させてモリブデン膜12
を完全に除去し、最後に(f)に示すように第1の基板
11が完全に離れれば完成する。Thereafter, the molybdenum film 12 is etched by immersing it in hydrogen peroxide water as shown in (e). At this time, the etching solution was heated to improve the etching speed. In this way, the etching progresses and the molybdenum film 12 is etched.
is completely removed, and finally, the first substrate 11 is completely separated as shown in (f), and the process is completed.
ここでモリブデンを第1の膜12に用いたのは酸化性雰
囲気に弱く、過酸化水素水への浸漬により容易にエツチ
ング除去できること、過酸化水素水はSl、5103、
Al、ITO等アクティブマトリクス製作に用いた材料
を全くエツチングしないため、きわめて高い選択エツチ
ング性を有するためである。また、第2の膜13を設け
たのは、モリブデン膜12がアクティブマトリクス製作
時に酸化性雰囲気に直接曝されないようにするためであ
る。Here, molybdenum was used for the first film 12 because it is sensitive to oxidizing atmosphere and can be easily removed by etching by immersion in hydrogen peroxide solution.
This is because the materials used for producing the active matrix, such as Al and ITO, are not etched at all, and therefore have extremely high selective etching properties. Further, the reason why the second film 13 is provided is to prevent the molybdenum film 12 from being directly exposed to an oxidizing atmosphere during active matrix fabrication.
こののち、この基板(第2の基板16)と対向電極を形
成したPETからなる対向基板を高分子分散型液晶を挾
んで張り付け、デイスプレィを完成さセた。このデイス
プレィを表示させたところ、ガラス基板上に形成したの
と同等な表示特性か得られることを確認した、また、こ
のデイスプレィはフしキシプル性があり、適度な曲げに
は酎えられることが分かった。したがって、未使用時に
は小さく折り畳むことができるデイスブしイを実現する
ことができる。Thereafter, this substrate (second substrate 16) and a counter substrate made of PET on which a counter electrode was formed were attached with the polymer dispersed liquid crystal sandwiched therebetween, thereby completing the display. When this display was displayed, it was confirmed that display characteristics equivalent to those formed on a glass substrate were obtained.Also, this display has flexible properties and can be easily bent to a moderate degree. Do you get it. Therefore, it is possible to realize a display that can be folded into a small size when not in use.
実施例2
実施例1のモリブデン膜12の代わりにモリブデン膜形
成時に酸素を含有したガスでスパッタしたモリブデン膜
を用いた。このため、モリブデン膜は酸素を高濃度に含
んでいる。酸素を高濃度に含むモリブデン膜はモリブデ
ン膜より過酸化水素水でのエツチング速度が大きい。そ
の後の工程は実施例1と同様とした。この結果、第1図
(e)でのモリブデン膜の除去がきわめて高速度に行わ
れる効果があった。特性等は全く同じであった。Example 2 In place of the molybdenum film 12 of Example 1, a molybdenum film sputtered with an oxygen-containing gas during formation of the molybdenum film was used. Therefore, the molybdenum film contains oxygen at a high concentration. A molybdenum film containing a high concentration of oxygen has a higher etching rate with hydrogen peroxide than a molybdenum film. The subsequent steps were the same as in Example 1. As a result, the molybdenum film shown in FIG. 1(e) was removed at an extremely high speed. The characteristics etc. were exactly the same.
実施例3
実施例1の第1の膜12として、モリブデン膜の代わり
にCaF、(弗化カルシウム)膜を用いた。この材料は
単結晶Si基板上にエピタキシャル成長させることがで
き、さらにCaF、上に81をエピタキシャル成長させ
ることができる。Example 3 As the first film 12 of Example 1, a CaF (calcium fluoride) film was used instead of the molybdenum film. This material can be epitaxially grown on a single crystal Si substrate, and CaF 81 can also be epitaxially grown on top of it.
本実施例ではエピタキシャル成長させたS1膜をTPT
の活性層として用いてアクティブマトリクスを製作した
。第2の基板としてPET膜を張り合わせ、希釈弗酸で
CaF、を除去した。CaFtは希釈弗酸で容易にエツ
チングでき、実施例1および2と同様にアクティブマト
リクスを第2の基板に転載できた。本実施例では、第2
の膜13(SiC,膜〕は形成しなかった。その後の工
程は実施例1と同様にしてデイスプレィを製作した。In this example, the epitaxially grown S1 film was
An active matrix was fabricated using this as an active layer. A PET film was laminated as a second substrate, and CaF was removed with diluted hydrofluoric acid. CaFt could be easily etched with diluted hydrofluoric acid, and the active matrix could be transferred to the second substrate as in Examples 1 and 2. In this example, the second
The film 13 (SiC, film) was not formed.The subsequent steps were the same as in Example 1 to produce a display.
その結果、表示特性が得られることを確認した。As a result, it was confirmed that display characteristics could be obtained.
実施例4
第2図(a)は、本発明の第4の実施例を示す図、第2
図(b)は、第2図(a)の要部拡大断面図である。実
施例1で述べた手法で多数の81基板を第1の基板41
としてその上にアクティブマトリクスを製作し、これら
を第2図(a)に示すようにPETの第2の基板42上
に張り合わせた。その後、実施例1と同様にしてアクテ
ィブマトリクスを第2の基板」−42に転載した。その
後、第2図(b)に示すように、フォトプロセスにより
スルーホール43を開口し、その後金属膜を堆積し、フ
ォトプロセスを用いて各アクティブマトリクスを接続す
る金属配線44とした。この結果、個々のアクティブマ
トリクスを接続した大面積のアクティブマトリクスを完
成できた。Embodiment 4 FIG. 2(a) is a diagram showing a fourth embodiment of the present invention.
FIG. 2(b) is an enlarged sectional view of the main part of FIG. 2(a). Using the method described in Example 1, a large number of 81 substrates are connected to the first substrate 41.
An active matrix was fabricated thereon, and these were laminated onto a second PET substrate 42 as shown in FIG. 2(a). Thereafter, in the same manner as in Example 1, the active matrix was transferred onto a second substrate "42". Thereafter, as shown in FIG. 2(b), a through hole 43 was opened by a photo process, and then a metal film was deposited to form a metal wiring 44 connecting each active matrix using a photo process. As a result, we were able to complete a large-area active matrix in which individual active matrices were connected.
こののち、この基板(第2の基板42)と対向電極を形
成したPETからなる対向基板を高分子分散型液晶を挾
んで張り付け、デイスプレィを完成させた。このデイス
プレィを表示させたところ、表示特性が得られることを
確認した。Thereafter, this substrate (second substrate 42) and a counter substrate made of PET on which a counter electrode was formed were attached with the polymer dispersed liquid crystal sandwiched therebetween, thereby completing a display. When this display was used, it was confirmed that the display characteristics could be obtained.
スルーホール43と配線44の形成は低温で行えるため
、PET基板(42)のような耐熱温度の低い基板上で
も問題なく行うことができた。また、配線の形成はスク
リーン印刷でも可能であった。Since the through-holes 43 and wiring 44 could be formed at low temperatures, they could be formed without any problem even on a substrate with a low heat-resistant temperature, such as a PET substrate (42). Also, the wiring could be formed by screen printing.
このように、回路を分割して形成し、それらを大面積基
板上に転載することにより、容易に大面積基板上に大規
模な回路を形成できる。この場合、分割された回路は大
面積基板に張り合わせる前に個別の試験により選別でき
、良品のみを転載することができるので、大規模回路の
製造歩留まりを上げることかできる。In this way, by dividing and forming a circuit and transferring them onto a large-area substrate, a large-scale circuit can be easily formed on a large-area substrate. In this case, the divided circuits can be selected through individual tests before being pasted onto a large-area board, and only non-defective products can be transferred, thereby increasing the manufacturing yield of large-scale circuits.
実施例5
第3図は、本発明の第5の実施例を示す図である。実施
例1で述べたのと同様な手法で81基板を第1の基板5
1としてその上にシフトレジスタからなるアクティブマ
トリクスの駆動回路53をpoly−3i T F
Tで形成し、第3図に示すようにa−3i TFTを
用いたアクティブマトリクス54を形成したガラスの第
2の基板52に張り合わせた。次いで、実施例1と同様
に駆動回路を第2の基板52に転載した。その後、実施
例4と同様な手法で駆動回路53とアクティブマトリク
スを接続した。回路動作を試験したところ、駆動回路か
らの信号がアクティブマトリクス54に転送されている
ことを確認した。実施例1と同様にデイスプレィを完成
させ、表示動作が確認できた、実施例6
第4図は、本発明の第6の実施例を示す図である。実施
例1で述べたのと同様な手法で81基板を第1の基板と
してその上にpoly−5iで1〕チヤネル1”FT6
]を形成し、同じく他の81基板上にpチャネルTF
T62を形成した。これらを第4図に示すようにガラス
の第2の基板63に転載し、実施例4の方法で相補形M
、OS (CM、OS)回路を構成するように接続した
。この回路を試験したところ、CMO3動作することが
確認できた。Embodiment 5 FIG. 3 is a diagram showing a fifth embodiment of the present invention. The 81 substrate was made into the first substrate 5 using the same method as described in Example 1.
A poly-3i T F
As shown in FIG. 3, the active matrix 54 using A-3i TFTs was bonded to a second glass substrate 52 on which an active matrix 54 was formed. Next, the drive circuit was transferred to the second substrate 52 in the same manner as in Example 1. Thereafter, the drive circuit 53 and the active matrix were connected in the same manner as in Example 4. When the circuit operation was tested, it was confirmed that the signal from the drive circuit was transferred to the active matrix 54. Example 6 The display was completed in the same manner as Example 1, and the display operation was confirmed. FIG. 4 is a diagram showing a sixth example of the present invention. Using the same method as described in Example 1, the 81 substrate was used as the first substrate and poly-5i was applied on it to form 1] channel 1" FT6.
] and p-channel TF on another 81 substrate.
T62 was formed. These are transferred onto a second glass substrate 63 as shown in FIG.
, OS (CM, OS) were connected to form a circuit. When this circuit was tested, it was confirmed that it operated in CMO3 mode.
このように、一連の工程で製作すると工程が複雑となる
CMO3回路を、丁1チャネルとpチャネル部分に分割
して形成し、転載して回路を構成することにより、工程
が単純化できる。In this way, the process can be simplified by forming the CMO3 circuit, which would be complicated if manufactured in a series of steps, by dividing it into the 1-channel and p-channel parts, and then reprinting them to configure the circuit.
以上説明したように、上記各実施例では、回路を形成す
る基板に耐熱温度が高い基板や、回路に悪影響を与える
物質を含まない基板を用いることができ、基板の制約を
少なくすることができる。As explained above, in each of the above embodiments, it is possible to use a substrate that has a high heat resistance temperature and a substrate that does not contain substances that adversely affect the circuit as the substrate forming the circuit, and it is possible to reduce restrictions on the substrate. .
また、回路を転載するのに、従来技術のように研磨を行
わなくて済むので、コストの高い研磨装置が不用であり
、低コスト化を達成でき、かつ剛性のないフレキシブル
基板に転載しようとする場合も基板が変形する問題もな
い。In addition, unlike conventional technology, polishing is not required when reprinting a circuit, eliminating the need for expensive polishing equipment, reducing costs, and reprinting onto non-rigid flexible substrates. In this case, there is no problem of the board deforming.
本発明の主旨は、容易にエツチング除去できる第1の膜
を第1の基板上に形成し、その上に回路を形成したのち
、第2の基板と張り合わせたのち、第1の膜を除去する
ことにより、回路を第2の基板上に転載することである
。第2の膜は第1の膜が回路製作時に損傷を受けるのを
防止するものである。したがって、本発明の主旨を逸脱
しない限りにおいて種々の変更が可能なことは言うまで
もなく、上記実施例において、例えば回路としてa−3
i TFT、 poly−8i TFTやエピタキ
シャル成長させたS]膜を用いたアクティブマトリゲス
、駆動回路を示したが、データバッファ回路等の回路で
あってもよい。第2の膜についてはSjO,膜の他にS
lNx膜等を用いることができる。接着剤は用途によ
って選べばよく、何等の制限もないことは明らかである
。The gist of the present invention is to form a first film that can be easily removed by etching on a first substrate, form a circuit thereon, bond it to a second substrate, and then remove the first film. In other words, the circuit is transferred onto a second substrate. The second film protects the first film from being damaged during circuit fabrication. Therefore, it goes without saying that various changes can be made without departing from the gist of the present invention.
Although active matrices and drive circuits using i TFTs, poly-8i TFTs, and epitaxially grown S] films have been shown, circuits such as data buffer circuits may also be used. For the second film, SjO, S
An INx film or the like can be used. It is clear that the adhesive can be selected depending on the purpose and there are no restrictions.
[発明の効果]
以上に説明したように、本発明は高価な研磨装置を使用
することなく回路を転載できるので、低コスト化が達成
できる。また、回路を分割して形成し、それらを大面積
基板上に転載することにより、容易に大規模回路を形成
できる。このとき、分割された回路は個別の試験により
選別でき、良品のみを転載することができるので、大規
模回路の製造歩留まりを上げることができる。さらに、
一連の工程で製作すると工程が複雑となるCMO3回路
をnチャネルとpチャネル部分に分割して形成し、転載
して回路を構成することにより、工程が単純化できる。[Effects of the Invention] As explained above, according to the present invention, circuits can be transferred without using expensive polishing equipment, so that cost reduction can be achieved. Further, by forming the circuit in sections and transferring them onto a large-area substrate, a large-scale circuit can be easily formed. At this time, the divided circuits can be selected through individual tests and only non-defective products can be reprinted, making it possible to increase the manufacturing yield of large-scale circuits. moreover,
The process can be simplified by forming the CMO3 circuit, which would be complicated if manufactured in a series of steps, by dividing it into n-channel and p-channel parts, and then reprinting the circuit to configure the circuit.
【図面の簡単な説明】
第1図(a)〜(f)は、本発明の半導体回路の形成方
法の第1の実施例の工程断面図、第2図(a)は、本発
明の第4の実施例を示す図、第2図(b)は、第2図(
a)の要部拡大断面図、第3図は、本発明の第5の実施
例を示す図、第4図は、本発明の第6の実施例を示す図
である。
11.41.51.62・・・第1の基板12・・・第
1の膜
13・・第2の膜
14・・・アクティブマトリクス
15・・・接着剤
16.42.52.63・・・第2の基板61・・・n
チャネルT F ’I”
62・・・pチャネル1”FT
特許出願人 日本電信電話株式会社[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1(a) to 1(f) are process cross-sectional views of a first embodiment of the method for forming a semiconductor circuit of the present invention, and FIG. 2(b) is a diagram showing the embodiment of No. 4, FIG.
FIG. 3 is a diagram showing a fifth embodiment of the present invention, and FIG. 4 is a diagram showing a sixth embodiment of the present invention. 11.41.51.62...First substrate 12...First film 13...Second film 14...Active matrix 15...Adhesive 16.42.52.63...・Second substrate 61...n
Channel TF 'I" 62...p channel 1" FT Patent applicant Nippon Telegraph and Telephone Corporation
Claims (1)
第2の膜を介して回路を形成した第1の基板を上記回路
を形成した側で第2の基板に張り合わせたのち、上記第
1の膜をエッチングにより除去することにより上記回路
を上記第2の基板上に転載することを特徴とする半導体
回路の形成方法。1. After laminating the first substrate on which a circuit is formed via the first film or the first film and at least one layer of the second film to the second substrate on the side on which the circuit is formed, A method for forming a semiconductor circuit, comprising transferring the circuit onto the second substrate by removing the first film by etching.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30626990A JP2866730B2 (en) | 1990-11-14 | 1990-11-14 | Method of forming semiconductor circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30626990A JP2866730B2 (en) | 1990-11-14 | 1990-11-14 | Method of forming semiconductor circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04178633A true JPH04178633A (en) | 1992-06-25 |
JP2866730B2 JP2866730B2 (en) | 1999-03-08 |
Family
ID=17955052
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JP30626990A Expired - Fee Related JP2866730B2 (en) | 1990-11-14 | 1990-11-14 | Method of forming semiconductor circuit |
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---|---|
JP (1) | JP2866730B2 (en) |
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