JPH04175835A - Debugging system for operating system - Google Patents

Abstract

PURPOSE:To execute a debugging operation system as a user program by preparing an instruction execution detecting-time processing program and executing a program which rewrites SVC instruction into an instruction which hardware treats as an instruction exception so as to debug it. CONSTITUTION:A supervisor call(SVC) instruction rewriting processing part 1-3-1-3 searches the SVC instruction of the debugging program on a memory and rewrites it into the instruction which generates the instruction exception. The instruction exception detecting-time processing program 1-3-2-1 is executed through the instruction exception detecting-time processing program registration processing part 1-2-1 of the operating system 1-2 when hardware detects the instruction exception in an instruction exception detecting processing part 1-1-1 or in an instruction execution protection processing part 1-1-2 at the time of the action of the debugging program on the memory. Thus, the debugging operating system is executed as a user program.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a debugging method for an operating system in a computer system.

[Conventional technology]

In conventional operating system debugging methods, when a supervisor call (hereinafter referred to as SVC) instruction is executed, the SVC program of the real operating system runs or a hardware instruction that can only be executed by the operating system is issued. In order to run as a user program of the operating system, it is necessary to
SV of the operating system program to be debugged
It is necessary to rewrite C instructions and instructions that can only be executed by the operating system to other instructions and execute them. In addition, debugging of the operating system was carried out by changing the operating system on which the debugging operating system runs and creating an operating system specifically for the debugging operating system.

[Problem to be solved by the invention]

Among the conventional operating system debugging methods mentioned above, SVC of Tebugzuru operating system
In the method of rewriting instructions that cannot be executed by the operating system to other instructions, the instructions to be rewritten may not be included in the SVC instruction or instruction area that can only be executed by the operating system, and the system conditions may not be able to be executed by the actual operating system. This is different from when you move a program because of a problem (-), so you have to change the source program, so multiple program files exist at the same time, and you have to compile it many times. In addition, debugging the operating system that operates on the operating system side has the disadvantage that the system must be generated, and some parts of the operating system such as critical testing must be done. In addition, the instruction exception detection processor simply rewrites the SVC instruction to an instruction that becomes an instruction exception and executes the instruction that can only be executed by the operating system. When a program performs instruction proxy processing, the operating system monitors the multiplicity of instruction exceptions, which has the disadvantage that the operating system being debugged cannot be executed as a user program.

[Means to solve the problem]

The debugging method of the present invention includes hardware having an instruction exception detection processing function and an instruction execution protection processing function, a processing program registration processing function when an instruction exception is detected, a control transfer processing function when an instruction exception is detected, and a processing program when an instruction exception is detected. Interpreting control statements that specify a program to be debugged in a debugging method for an operating system in a computer system that has an operating system that has a return processing function, especially a function that allows a return from the processing program when an instruction exception is detected at any location. a memory load processing unit for a program to be debugged which selects a program file to be debugged and creates a program to be debugged in memory and an address information table in a memory work area;
An SVC jump destination address table creation unit that interprets control statements that correspond to V C numbers and SVC programs and creates an SVC number to address correspondence table while referring to the address information table, and a dehugging unit for memory 12. I7
The SVC instruction rewrite processing unit searches for SVC instructions in the program and rewrites them to instructions that generate instruction exceptions, and the hardware detects instruction exceptions using the instruction exception detection processing unit or instruction execution protection processing unit when the program to be debugged in memory runs. The instruction exception detection processing function 7gram is executed via the instruction exception detection processing program registration processing section of the operating system when detected.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the present invention, the hardware 1-1 includes an instruction exception detection processing unit 1-1-1 and instruction execution protection processing units 1-1 to 2, and the operating system 1-2 registers a processing program at the time of instruction exception detection. Processing unit] -2-1, a processing program transition processing unit 1-2-2 at the time of instruction exception detection, and a return processing unit 1-2-3 from the processing program at the time of instruction exception detection. becomes.

In particular, the return processing unit 1-2-3 from the instruction exception detection processing program of the operating system 1-2 needs to be able to return to any location other than the instruction exception occurrence point. The debug program 1-3 of the present invention is roughly divided into initialization processing sections]-3 to 1 and execution processing section 1-3-2.

The initial setting processing unit 1, -3-1 includes a memory load processing unit 1-3-]-1 that loads a program to be debugged, and an SM
C jump destination address table creation unit 1, -3-1-2 and S
It consists of an SVC instruction rewrite processing unit 1-3-1-3 that rewrites a VC instruction to an exception instruction, and an instruction exception detection processing program registration process]-3-1-4. Execution waiting processing unit 1-3-2
is refined in the instruction exception detection processing program 1-3-2-1.

FIG. 2 shows an explanatory diagram of the initial setting process.

Among the initial setting processing sections 1-3-1, the memory load processing section 1-3-1 for the block to be debugged. -1 is a console command or control statement 1 that specifies the program to debug on a file. -5-], select the program file 1--4 to be debugged, load the program l-1-1 to be debugged in the memory into the memory work area 2-1, and read the address information table 2-1-2. Memory work area 2
Create at -1. Next, the SMC jump destination address table creation unit 1-3-1-2 interprets the control statement 1-5-2 that corresponds between the SVC number on the console command or file and the SVC program, and creates an address information table l-1-
SVC number and address correspondence table 2 while referring to 2.
-1-3 is created in the memory work area 2-1.

Next, the SVC instruction rewrite processing unit 1-3-1-3
Explanatory diagram of the processing unit that rewrites an instruction to an exception instruction (Figure 3)
As shown in , the progera to debug on memory b, 2
- If the entire program of 1-1 is searched and an SVC instruction is detected, and the SVC instruction is registered in the SVC number and address correspondence table 2-1-3, the hardware 1-1 treats the SVC instruction as an instruction exception. Rewrite the command to handle it as follows. In Figure 3, (n n ri ) and (mmm) or SVC
In this example, 3-1 is registered in number and address correspondence tables 2 to 1-3 and is not registered (xxx>), and 3-1 before SVC instruction rewriting is rewritten as 3-2 after SVC instruction rewriting. Here, , XXX are instructions that the hardware handles as instruction exceptions.

Next, instruction exception detection processing program registration processing] 3-1-
4 registers the instruction exception detection processing program 1-3-2-1 on the operating system using the instruction exception detection processing program registration processing unit 1-2-1 of the operating system 1-2.

Next, after the SVC instruction is rewritten, control is transferred to the debugging program 2-1-1 on the memory 3-2, and the debugging program 2-11 on the memory is operated.

FIG. 4 is an explanatory diagram when the program 2-1-1 to be debugged on the memory operates. In this example, the program to be debugged in memory is both the program to be debugged (SMC caller) 4-1 and the program to be debugged (SVC program) 4-2, but both are not necessarily 3-2 after the SVC instruction has been rewritten. It is not necessary, and one of the programs may be a program after rewriting the SVC instructions prepared in advance by the debug program 1-3.

When the program to be debugged (SMC caller) 4-1 is started and the XXX (nnn) instruction in ■ is executed, XXX
(nnn) instruction is SVC instruction rewrite processing unit 1-3-1-3
Since it has been rewritten as an exception instruction, the hardware instruction exception detection processing unit 1-1-1 recognizes it as an instruction exception, and the operating system's instruction exception detection control transfer processing unit 1
- In 2-2, instruction exception detection processing program registration processing 1 -
In step 3-1-4, control is transferred to the instruction exception detection processing program registration processing program 1-3-2-1■ registered using the instruction exception detection processing program registration processing section 1-2-1.

As shown in the flowchart of the instruction exception detection processing program 1-3-2-1, if the instruction that caused the instruction exception is an SVC instruction, the instruction exception detection processing program 1-3-2-1 saves the registers with 5VC (
nnn) program to be debugged (SVC program)
Obtain the start address of 4-2, and use (■) to set the return destination of the return processing unit 1-2-3 from the instruction exception detection processing program of the operating system to the address obtained in (■). Program to debug (<SVC program) 4- Return to 2.

The program to be debugged (SVC program) 4-2 is
After the SVC-specific processing is performed, a return instruction is issued from the hardware SVC by specifying the address of the next instruction after the SvC instruction (2).

Since the hardware return instruction from SvC in (2) is an instruction that can only be issued by the operating system, the hardware instruction execution protection processing unit j~1-2 operates, an instruction exception occurs, and the instruction exception detection processing unit is activated again. Lokrum 11-
2 Control shifts to 1. Instruction exception detection processing program 1, -3-2-1 is an instruction exception or an instruction that has occurred.SV
Since this is a return instruction from C, the registers stored in ■ are restored in (7), and 2. In ■, the return destination specified for the SVC cleanup instruction (the next instruction of the SVC instruction in ■) is set as an instruction exception. By notifying the return processing unit 1-2-3 from the instruction exception detection processing program of the operating system as the return destination, control is transferred to the instruction next to the SvC instruction 0).

In addition, to exit the operating system to be debugged, press S.
Since it is a VC instruction, the program to be debugged to terminate (SVC program> 4-2) is debugged program 1-
If preparation is made on the third side, the termination process can also be realized.

〔Effect of the invention〕

As described above, the present invention includes an instruction exception detection processing section and an instruction execution protection processing section of hardware, an instruction exception detection processing program registration processing section of an operating system, a control transfer processing section upon instruction exception detection, and an instruction exception detection processing section. The program to be debugged and the operating system can be debugged by preparing an instruction exception detection processing program using the return processing unit from the detection processing program and executing the debugging program in which the SVC instruction has been rewritten to an instruction that the hardware handles as an instruction exception. It has the effect of debugging operating system programs without modifying the system. Moreover, if this debug program runs on an operating system that can run multiple programs at the same time as an operating system user, there is an effect that multiple programs of the operating system can be debugged at the same time.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the present invention, Fig. 2 is an explanatory diagram of initial setting processing, Fig. 3 is an explanatory diagram of a processing unit that rewrites an S V C instruction to an exception instruction, and Fig. 4 is an illustration of the actual configuration of the present invention. FIG. 5 is an explanatory diagram when the debug program operates, and FIG. 5 is a flowchart of the processing program when an instruction exception is detected. 1-1...Hardware,] ---1 to 1...Instruction exception detection processing unit, 1-1-2...Instruction execution protection processing unit, 1-=2...Operating system, 1 -2-
1...Instruction exception detection processing program registration processing unit, 1
-2-2...Control transition processing unit upon detection of instruction exception, 1-2
-3...Return processing unit from instruction exception detection processing program, 1-3...Debug program, 1-3-1...
- Initial setting processing section, 1-3-1-1... Memory load processing section, 1-3-1-2... SVC jump destination address table creation section, ], -] 3-1-3 -S VC instruction rewrite processing unit, 1-3-1-4...Instruction exception detection processing program registration process, 1-3-2...Execution processing unit,
1-3-2-1...Instruction exception detection processing program,
1-4...Program file to be debugged, 1-5.
... Input control statement, l-5-1... Control statement that specifies the program to be debugged, 1-5-2... Control statement that corresponds between the S■C number and the SVC program, 2-1 ...Memory work area, l-1-1...Program to be debugged on memory, 2-1-2...Address information table, 2-
1-3...SVC number and address correspondence table, 3-
1... Before SVC instruction rewriting, 3-2... After SVC instruction rewriting, 4-1... Program to be hugged (
SVC caller), 4-2...Program to be debugged (
SVC program).

Claims (1)

[Scope of claims] Hardware having an instruction exception detection processing function and an instruction execution protection processing function, a processing program registration processing function when an instruction exception is detected, a control transfer processing function when an instruction exception is detected, and a processing program when an instruction exception is detected. In a debugging method for an operating system in a computer system that has a return processing function, especially a function that allows a return from the processing program when an instruction exception is detected at any location, a control statement that specifies the program to be debugged is interpreted. A control statement that selects a program file to be debugged and creates a program to be debugged in memory and an address information table in a memory work area, a memory load processing section of the program to be debugged, and a control statement that corresponds between a supervisor call number and a supervisor call program. A supervisor call destination address table creation unit that interprets the address information table and creates a supervisor call number and address correspondence table while referring to the address information table, and an instruction that searches for a supervisor call instruction in the program to be debugged in memory and generates an instruction exception. The supervisor call instruction rewrite processing unit to be rewritten and the instruction exception detection processing program registration of the operating system when the hardware detects an instruction exception in the instruction exception detection processing unit or instruction execution protection processing unit when the program to be debugged in memory runs. A debugging method for an operating system having an instruction exception detection processing program executed via a processing unit.