JPH04175674A - Semiconductor logical integrated circuit - Google Patents

Abstract

PURPOSE:To enhance the rate of failure detection by providing a control circuit which operates an initial test firmware stored in a control memory, and installing in the circuit a means for actuating the initial test firmware only when an internal circuit to be tested is set at a test mode. CONSTITUTION:The micro instruction register 2 of a semiconductor logical integrated circuit holds micro instruction words via an input signal SIN. An address register 4 holds the final address of an initial test firmware stored in a control memory 1. An address array 5 holds the control information of the data block of the control memory 1. A comparator circuit 6 compares the content of the register 4 to that of the array 5. A control circuit 3 stores the predetermined micro instruction words of the initial test firmware into the memory 1 via the register 2 by setting an input signal TST at '1' and operates the initial test firmware.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor logic integrated circuits (hereinafter referred to as LSIs), and particularly to electrical testing of internal circuits of LSIs.

[Conventional technology]

In the manufacture of LSIs, the types of functions of internal circuits are diverse, and the number of internal circuits housed in LSIs is also increasing.

In addition, LSIs that a few years ago housed internal circuits on a scale of only a few gates are likely to be put into practical use in the near future with circuits on a scale of hundreds of thousands to millions of gates.

As the number of circuits housed in an LSI increases, the chip size of the LSI increases. Even if the chip size is increased, the number of input/output terminals of the LSI will not be significantly increased. Therefore, the number of internal circuits, that is, the number of logic stages, of a specific signal bus between an input terminal and an output terminal tends to increase.

Due to the above-mentioned circumstances, methods such as the scan path method and the built-in self-test method have been used for electrical testing of LSIs after manufacturing them.

Furthermore, as the chip size increases, the operating performance required of LSIs increases, and the operating frequency is increased.

However, as a means to test LSI, LSI
The LSI is tested by starting the LSI with a clock signal applied from the tester to the LSI based on the information set in the input signal of the tester, and comparing the output signal with an expected value.

[Problem to be solved by the invention]

In this conventional semiconductor logic integrated circuit, the equipment inspection laboratory that used to inspect devices equipped with a large number of LSIs is now reaching a scale comparable to the electrical testing of recent LSIs. With the increase in scale, L
Although the number of steps in a test pattern for testing an SI increases, it has been difficult to effectively activate the circuits housed in the LSI, that is, the internal logic circuits.

Note that the circuit configuration of the logic circuit (ALU, RAM.

ROM, flip-flop, etc.)', and when each circuit is operated assuming all the operations of each circuit, the failure detection rate is the rate at which a failure can be detected when a specific circuit fails using a test pattern. That's what it means.

In other words, in conventional testing, it is difficult to form effective test patterns that adequately correspond to the increase in LSI circuit scale, and even if a huge number of test patterns are formed, the failure detection rate does not increase. there were.

In addition, to test this conventional semiconductor logic integrated circuit,
The frequency of a clock signal applied from a tester to an LSI to check its operation is becoming far lower than the normal operating frequency of the LSI.

For example, if the operating frequency of the tester is several MHz, but the actual operating frequency of the LSI is far from 20 to 50 MHz, there is a problem that it is not possible to test the performance of the LSI when it actually operates.

[Means to solve the problem]

The semiconductor logic integrated circuit of the present invention includes a control memory consisting of a plurality of compartments capable of storing a plurality of microinstructions, a microinstruction register that holds microinstructions read from the control memory, and a microinstruction register that holds microinstructions read from the control memory. an address register that holds the final address of the control memory of the initial test firmware, an address array that holds management information for data blocks of the control memory and has a plurality of entries, and an address register that holds the final address of the control memory of the initial test firmware; It includes a comparison circuit for comparison, and a control circuit for controlling the LSJ to operate the initial test firmware.

Further, the LSI of the present invention includes a control memory capable of storing a plurality of microinstruction words, a microinstruction register holding the microinstruction words read from the control memory, and an initial test firmware stored in the control memory. an address register holding the final address of the control memory; and 7 holding address information of the control memory.
A address counter, a comparison circuit that compares the contents of the address counter and the address register, a control circuit that controls the LSI to operate the initial test firmware, and a clock signal that is based on the clock signal supplied to the LSI. Clock 1/n divided by 1/n
It is equipped with a frequency dividing circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention, and FIG. 2 is a test flowchart for explaining the test operation using the blocks of FIG. 1.

As shown in these figures, the LSI input signal TST is
”, the control circuit 3 starts controlling to store a predetermined initial test firmware microinstruction word in the microinstruction register 2 by the scanpath method via the scanpath input signal SIN.

Microinstruction register 2 receives scan path input signal SI
As soon as the microinstruction register 2 is filled with data from the microinstruction register 2, the control circuit 3 executes a series of controls for sequentially writing data from the microinstruction register 2 to the control memory 1.

The predetermined initial test firmware is stored in RAM control memory 1.
Then, the control circuit 3 sets the final address in the address register 4 holding the final address of the control memory 1 of the initial test firmware stored in the control memory 1.

Next, the control circuit 3 reads the microinstruction word stored in the control memory l in order to test the circuit under test 7, and the initial test firmware decoded by the instruction decoder in the control circuit 3 is applied to the circuit under test 7. It runs until some error is detected or it terminates normally.

A comparator circuit 6 that compares the contents of an address register 4 that holds the final address of the initial test firmware in the control memory 1 and an address array 5 that holds management information of data blocks of the control memory 1 and has a plurality of entries. The output signal END of the control circuit 3 is set to 1'' when the output is "1", that is, the information indicating that this is the final step of the initial test firmware matches the information that the initial test firmware has been normally completed.

Next, the tester that tests the LSI detects that the LSI output signal EHD is set to "L" and sets the LSI input signal TST to 0, that is, the conventional method. When a specific value (“0” or “1”) is set to the simulated LSI input signal to effectively activate the LSI logic circuit, a specific value is set to the output of a specific flip-flop or the output signal of the LSI. The value (“0”, “1” or intermediate level) is output (this is called the expected value). In other words, the electrical testing method uses both the method of setting data to the input signal of the LSI and the scan path method. It turns out.

FIG. 3 is a block diagram of a second embodiment of the present invention, and FIG. 4 is a flowchart for explaining the operation of a test using the second block.

In the first embodiment, the control memory 1 was constructed of a readable and writable format, that is, a RAM, but the present embodiment is characterized in that it is a read-only control memory 1a.

By pre-forming the initial test firmware described in the first embodiment in the control memory 1a constituted by this ROM, it becomes possible to perform the same electrical test as in the first embodiment.

In the first embodiment and the second embodiment, the control memory 1, la
Although described so as to operate only the initial test firmware, it is also possible to implement a system in which the microinstruction words of the initial test firmware are stored in a part of the control memory 1, which is originally built in as a necessary function of the LSI.

FIG. 5 is a block diagram showing a third embodiment of the present invention,
FIG. 6 is a flow chart for explaining a test using the block shown in FIG. 5, and FIG. 7 is a waveform diagram of the clock signal after frequency division of the clock shown in FIG.

First, a clock signal (C
LK), the control circuit 3 starts control to store a predetermined initial test firmware microinstruction word in the microinstruction register 2 by serial-to-parallel conversion via the input signal SLN.

As soon as the microinstruction register 2 is full with data from the input signal SIN, the microinstruction register 2 to R
The control circuit 3 performs a series of controls for writing into the AM control memory l.

When the predetermined initial test firmware is stored in the control memory 1, the control circuit 3 stores the final address in the address register 4 holding the final address of the control memory 1 of the initial test firmware stored in the control memory l. Set address.

Next, by setting the input signal TST of the LSI to "1", the control circuit 3 outputs a clock signal (CL) which is supplied to the LSI as shown in FIG. 7 in order to test the circuit under test 7.
Clock l/n whose frequency is divided by 1/n based on K)
The frequency dividing circuit 8 operates, and the clock signal after frequency division (CLKI
), a normal real-time based high-speed test is started.

The micro-instruction word stored in the control memory l is read out and the initial test firmware is decoded by the instruction decoder in the control circuit 3 until an error is detected in the circuit under test 7 or the initial test firmware is terminated normally. executed.

The output of the comparator circuit 6 that compares the contents of the address register 4 that holds the final address in the control memory 1 of the initial test firmware with the contents of the address counter 5 that holds the address information of the control memory 1 is l'', that is, the initial The output signal END of the control circuit 3 is set to "1" when the information indicating that this is the final step of the test firmware and the information that the initial test firmware has been successfully completed match.

Next, the tester that tests the LSI detects that the LSI output signal END is set to "1" and sets the LSI input signal TST to "0", that is, the conventional method. , a test method in which a specific value (°゛0” or °′1”) is set to the simulated LSI input signal to effectively activate the LSI logic circuit and a scan path method are used together. This will lead to a transition to electrical testing methods.

FIG. 8 is a block diagram of the fourth embodiment of the present invention, and since the control memory 1 in FIG. 5 of the third embodiment is a ROM control memory 1a, it is necessary to read the initial firmware in advance. A similar effect can be obtained.

〔Effect of the invention〕

As explained above, the present invention can be applied to the conventional LSI
In addition to the above test method, the initial test firmware built into the LSI is activated, so an effective test can be performed to test LSIs that can cope with the increase in the number of circuits that will be housed in LSIs in the future.

In addition, clock 1/
Since an electrical test method is adopted in which the n-frequency divider circuit is activated and the initial test firmware is activated, the LSI can be tested at a high speed close to the actual operating frequency required for the LSI.

[Brief explanation of the drawing]

1 and 2 are a block diagram and a test flowchart of a first embodiment of the present invention, FIGS. 3 and 4 are a block diagram and a test flowchart of a second embodiment of the present invention, and FIG. ~
FIG. 7 is a block diagram of a third embodiment of the present invention, and FIG.
A flowchart and a waveform diagram of a frequency-divided clock signal for explaining a test using blocks, and FIG. 8 is a block diagram of a fourth embodiment of the present invention. 1.1a... Control memory, 2... Micro instruction register, 3... Control circuit, 4...
... Address register, 5 ... Address array, 6 ... Comparison circuit, 7 ... Circuit under test, 8 ... Clock]/n frequency division circuit, l 5-
...-address counter. Agent Patent Attorney Oto Uchihara Figure 2 Figure 4 Figure 6

Claims (1)

[Scope of Claims] 1. A control memory consisting of a plurality of compartments capable of storing a plurality of micro-instructions, and a micro-instruction that holds a micro-instruction word read from the control memory or a micro-instruction word to be written into the control memory. an instruction register, an address register holding the final address of the control memory of the initial test firmware stored in the control memory, and an address array holding management information of the data blocks of the control memory and having a plurality of entries; , a comparison circuit for comparing the contents of the address array and the address register, and a control circuit for operating the initial test firmware, and the initial test firmware is activated only when the internal circuit under test is set to test mode. A semiconductor logic integrated circuit characterized by having a built-in means for activating. 2. The control device according to claim 1, further comprising means for storing the microinstruction word in the microinstruction register by a scan path method, and further writing the stored microinstruction word in the control memory in microinstruction register units. semiconductor logic integrated circuit. 3. The semiconductor logic integrated circuit according to claim 1 or 2, wherein the control memory has a readable and writable format. 4. The semiconductor logic integrated circuit according to claim 1, wherein initial test firmware is stored in advance in the control memory, and the control memory is in a read-only format. 5. A control memory capable of storing a plurality of microinstruction words;
A microinstruction register that holds a microinstruction word read from the control memory or written to the control memory, and an initial test firmware stored in the control memory and a final address of the control memory. an address register, an address counter holding address information of the control memory, a comparison circuit that compares the contents of the address counter and the address register, a control circuit for operating the initial test firmware, and an external The clock signal is 1/n based on the supplied clock signal.
means for activating the clock 1/n frequency dividing circuit and activating the initial test firmware only when the internal circuit under test is set to a test mode; A semiconductor logic integrated circuit characterized by having a built-in. 6. The semiconductor logic integrated circuit according to claim 5, further comprising means for storing a microinstruction word in the microinstruction register by serial-to-parallel conversion, and further writing the stored microinstruction word in the control memory in microinstruction register units. . 7. The semiconductor logic integrated circuit according to claim 5 or 6, wherein the control memory has a readable and writable format. 8. The semiconductor logic integrated circuit according to claim 5, wherein the control memory in which initial test firmware is stored in advance is of a read-only format.