JPH04175034A - Cell exchange - Google Patents

Abstract

PURPOSE:To attain cell exchange without much increasing the speed and to reduce a cell abort rate by storing an input cell at an incoming line speed, managing an address in a buffer memory by destination and reading and outputting the data at a speed twice an outgoing line speed. CONSTITUTION:When a cell is inputted, a header processing circuit 10i (i=1-n) checks whether or not the cell is a multiple address cell, reads outgoing line numbers 21, 22 of destination, writes destination information in the order of incoming line numbers 11, 12 and sends the cell to a buffer selection circuit 16. The cell is written in an incoming line speed adjustment buffer 21 and the circuit 16 decides a number of a buffer memory to be written therein. An incoming line spatial switch 13 connects the buffer 21 and the decided memory and stores the cell to the prescribed buffer. At first a buffer memory for writing a multiple address cell B whose destination is numbers 21, 22 is selected. When the buffer memory 1 is selected, a cell number to be in multiple address with the buffer 10 is added to the cell B and the result is stored as a cell B2 and addresses of the buffer 10 are arranged in a queue by destination addressed to the outgoing line numbers 21, 22.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a cell switching device that switches cells containing blocks of various multimedia information such as voice, data, and images at high speed.

(Prior art) Figure 1θ is, for example, IEICE journal B-IVo1
．． J72-B-I No, 11 pp, 1070-1
075.075 is a block diagram showing a conventional cell switching device shown in November 1987. In the figure, (11) to (
tn) are n (n≧2) incoming lines into which packets are input, and the packets have a fixed length and each has a header section containing encoded destination information. (2,)
~(2,) are m (m≧2) outgoing lines through which the packet is output according to the destination specified in its header. (3,) to (31) are buffers on the IL (n≧n) side where the input packets are temporarily stored, and (4) are buffers on the incoming lines (1+) to (t
This is an empty buffer selection switch that connects the buffer memories (L) to (31) to the empty buffer memories (L) to (31).

(5,) to (5e) are the buffer memories (3,) to (
31), and extracts and stores only the header part of the packet stored in the associated buffer memories (3,) to (31). (6I) to (6□) are each of these header storage circuits (5
It is an outgoing line selection circuit that is provided corresponding to I) to (5□) and makes significant only the output sent to the output line corresponding to the stored contents of the corresponding header storage circuit (5,) to (5i). .

(71) to (7n) are prepared corresponding to each of the outgoing lines (2,) to (2,), and each of the outgoing line selection circuits (61
) to (61) and encodes the output into the buffer numbers (3I) to (3L). (8I) to (8n) are provided corresponding to encoders (71) to (7n), and buffer numbers coded by each encoder (7,) to (7rl) are written in the order in which they are input. This is a first-in first-out (hereinafter referred to as FIFO) type FIFO memory that is read. (91) - (9
n) is prepared for each output line (2I) to (21), and is controlled by the buffer number output from the corresponding FIFO memory (8,) to (8n).
This is a buffer connection switch that outputs packets stored in ports 1) to (3,) to outgoing lines (21) to (2,) specified by their headers.

Also, (7,,l), (a,,+), (30)
, (31) is provided for broadcast cells, and (7
, ri is the encoder for broadcasting, (a,,t) is FI for broadcasting
FO memory (30) is a broadcast selection circuit (311) that specifies whether or not to broadcast for each outgoing line according to the broadcast destination in the header.
) to (31- are M switches for switching broadcast/individual according to the designation thereof.

Although packets are used here instead of cells as the unit of information to be transmitted, the multimedia information is divided into blocks and a header section containing destination information is added to them. Both cells and packets accomplish the same thing. However, generally the packet is 1
The difference is that the length of one block is treated as a variable length, whereas the length of a cell is treated as a fixed length specified by international standards.

Next, the operation will be explained. Here, Fig. 11 is a time chart showing the timing of the signals of each part. When the buffer memories (3K) and (3L) are empty, the signals from the incoming lines (11) and (1n) to the a line (2I) are It shows the flow of control when packets are received simultaneously. Also,
The packets handled here have a fixed length as mentioned above,
The header section shall include an outgoing line number encoded as destination information.

When a packet arrives at the incoming lines (11) to (1,1), the free buffer selection switch (4) selects the buffer memory (31).
) to (3e) is selected and connected to the incoming lines (11) to (1n) on which the packet arrived. Here, as shown in (a) and (0) in Figure 11,
A packet whose destination is the outgoing line number "1" of the same outgoing line (2I) in the header section is sent to the incoming line (II) and (In
), the free buffer selection switch (4) changes the incoming lines (1,) to (1n) to lower numbers, for example.
And free buffer memory (3,) ~ (3jL)
Also select the youngest number and connect them. Therefore, in this case, the free buffer selection switch (4) selects the incoming line (b).
is connected to the buffer memory (31), and the incoming line (In) is connected to the buffer memory (3A), so that packet A arriving at the incoming line (ll) is connected to the buffer memory (31), and packet B arriving at the incoming line (In) is connected to the buffer memory (31). Buffer memory (31
) respectively.

By switching the free buffer selection switch (4), the packet A is sent to the header storage circuit (5I) corresponding to the buffer memory (3,), and the packet B is sent to the header storage circuit (SjL) corresponding to the buffer memory (3L).
Also supplied. Here, header storage circuits (51) to (
5 Arashi), the receiver extracts only the header part of each packet it receives and stores its content, which is the outgoing line number. Therefore, the outgoing line number "1" of the outgoing line (2,) is stored in the header storage circuits (5I) and (5□), respectively. The contents of these header storage circuits (5□) to (51) are sent to the corresponding outgoing line selection circuits (6I) to (6□), and each outgoing line selection circuit (6I) to (alL) stores the corresponding header. Only the output sent to the output line corresponding to the output line number specified by the contents of the memory circuits (5,) to (51) is made significant, that is, "1", and the output sent to other output lines is meaningless. , that is, the buffer memory (
3,) to (31), and informs the free buffer selection switch (4) of this to prepare for reception of subsequent packets.

Also, when broadcast cells arrive, the broadcast cells are accepted in the order of arrival in the broadcast FIFO, and buffer memories (3,) to (3,
From 1), broadcast cells are output all at once to a plurality of outgoing lines specified by the header.

[Problem to be solved by the invention]

Since the conventional cell switching device is configured as described above, one buffer memory (3I) is used to avoid collision with other cells when reading cells from the buffer memories (3,) to (3L). ~(3L) can store only one cell, and the number of cells written is smaller than the buffer memory (3L).
I) If the number of cells exceeds (31), the cell will be discarded, and in order to reduce the cell discard rate, a large number of buffer memories (3,) to (3A) are prepared. Furthermore, as a result, an empty buffer selection switch is provided for connecting the buffer memories (3I) to (31) to the incoming lines (l,) to (1n) and the outgoing lines (2□) to (2,). (4) and buffer connection switch (9I) ~
There were problems such as the scale of (9n) becoming large. Furthermore, since broadcast cells create a broadcast queue and are output at a different timing from non-broadcast cells, the order of cells may be reversed between broadcast cells and non-broadcast cells. When broadcast cells are sent, there is a problem in that the outgoing line becomes vacant, resulting in a low utilization rate of the outgoing line.

This invention was made to solve the above-mentioned yA problem, and even if the number of buffer memories is reduced, cells are less likely to be discarded due to collision, and the buffer memory is connected to incoming and outgoing lines. The purpose of the present invention is to provide a cell switching device having a broadcasting function, which can reduce the scale of a switch that carries out a call, and which maintains the order of cells and does not reduce the utilization rate of outgoing lines.

(Means for solving the i! problem) The cell switching device according to the first invention receives a broadcast or non-broadcast cell composed of a data part and a header containing destination information of the data part. It is equipped with a plurality of incoming lines and a plurality of outgoing lines through which cells are output to designated destinations according to the destination information, and is provided for each incoming line to determine the destination information from the header of the input cell and whether the cell is broadcast or non-broadcast. A header processing circuit that detects whether a cell is a broadcast cell, adds a count value of 1 to a cell detected as a non-broadcast cell, adds the number of destinations as a count value to a broadcast cell, and adds it to each address by address specification. A plurality of buffer memories for writing and decrementing a count value by 1 when reading a cell, an input line space switch that connects these buffer memories and the header processing circuit, and a line space switch that connects the read cell to one or many lines according to destination information. A buffer memory in which the cell is written is selected by controlling an output line space switch that simultaneously outputs output to the output line of the line and the input line space switch, and the cell is written in the buffer memory at a speed higher than the input line speed. and managing buffer numbers in the buffer memory of the written cells for each destination of the cells, and based on this, read the cells from the buffer memory in a predetermined order at a speed equal to or higher than the output speed; and a buffer control circuit that controls the outgoing line space switch so that the cell is output to the outgoing line specified by the header section.

Further, the cell switching device according to the second invention has a plurality of incoming lines for inputting broadcast or non-broadcast cells each including a data part and a header including destination information of the data part, and a cell switching device according to the destination information. A header processing circuit is provided for each incoming line and detects destination information from the header of the input cell and whether the cell is a broadcast or non-broadcast cell. , a broadcast cell counter that manages the readout number of broadcast cells as a count value, a broadcast cell counter that writes non-broadcast cells and broadcast cells to each address by address specification, and empties the non-broadcast cell when one is read. a memory capable of reading a broadcast cell multiple times at different timings and emptying it when the value of the broadcast cell counter becomes 0; a buffer control device that manages an address in the memory where the cell is stored; The apparatus includes a device for connecting the memory and an incoming line, and a device for connecting the memory and an outgoing line.

Further, the cell switching device according to the third invention has a plurality of incoming lines for inputting broadcast or non-broadcast cells composed of a data part and a header including destination information of the data part, and a cell switching device that inputs the cells according to the destination information. A header processing circuit is provided for each incoming line and detects destination information from the header of the input cell and whether the cell is a broadcast or non-broadcast cell. , a broadcast cell counter that manages the readout number of broadcast cells as a count value, a broadcast cell counter that writes non-broadcast cells and broadcast cells to each address by address specification, and empties the non-broadcast cell when one is read. Broadcast cells are read out multiple times at different timings and can be emptied when the value of the broadcast cell counter becomes 0, and an input line space that connects the header processing circuit and a predetermined buffer memory. a switch, an outgoing space switch that simultaneously outputs read cells to one or multiple outgoing lines according to destination information, and a buffer memory in which the cells are stored by controlling the incoming space switch. and write the cell in the buffer memory at a speed higher than the input linear speed, manage the buffer number of the written cell in the buffer memory for each destination of the cell, and write the cell based on the buffer number in the buffer memory of the written cell. Buffer control for controlling the outgoing line space switch so that the cell is read from the buffer memory in a predetermined order at a speed equal to or higher than the outgoing line speed, and the cell is output to the outgoing line specified by its header part. It is equipped with a circuit.

Further, the cell switching device according to the fourth invention has a plurality of incoming lines for inputting broadcast or non-broadcast cells composed of a data part and a header including destination information of the data part, and a cell switching device according to the destination information. A header processing circuit is provided for each incoming line and detects destination information from the header of the input cell and whether the cell is a broadcast or non-broadcast cell. , a broadcast cell counter that manages the readout number of broadcast cells as a count value, a broadcast cell counter that writes non-broadcast cells and broadcast cells to each address by address specification, and empties the non-broadcast cell when one is read. Broadcast cells can be read out multiple times at different timings and emptied when the value of the broadcast cell counter reaches 0.There is a buffer memory that can store multiple cells, and one or many incoming lines can be read out at the same time. an incoming line multiplexer for multiplexing arriving cells and writing them into one buffer memory; and an outgoing line multiplexer for separating the multiplexed and read cells into one or multiple outgoing lines according to destination information and outputting them simultaneously. It is equipped with a line separator and a buffer control circuit that maintains the order of the cells by managing the addresses of the buffer memory storing the cells for each destination outgoing line of the cells.

(Operation) The cell switching device in the first invention detects the destination of cells input from the incoming line, and then adds the number of cells to be broadcast to the buffer memory selected by the incoming line space switch as a count value. Write and accumulate the accumulated cells at high speed, manage the buffer number on the buffer memory of the accumulated cells for each destination, access the buffer memory based on the address managed for each destination, and write the accumulated cells there. High-speed reading increases the chances of reading cells from the same buffer memory, reducing cell collisions during reading, and reading broadcast cells reduces the count that was added to cells when storing them in the buffer memory. Decrease the value by 1, and if the count value is 2 or more, leave the cell in the buffer and read the cell multiple times, and set the outgoing space switch to 1.
By making a point-to-many connection, multiple cells can be read out at the same time to achieve a broadcast function, but since the count value of the buffer memory is 1, reading out non-broadcast cells is achieved by emptying the buffer when one cell is read out. By connecting the buffer memory and a predetermined outgoing line using an outgoing line space switch, the number of discards due to cell collisions is reduced with a small number of buffer memories, and the scale of the switch connecting the buffer memory and the incoming line and outgoing line is reduced. To realize a cell switching device that is capable of

The cell switching device in the second invention detects the destination of a cell inputted from an incoming line, and then writes and accumulates it in the memory at high speed, and as for broadcast cells, the number of destinations to be broadcast is used as a count value. Write it in the information cell counter,
When reading a cell many times until the count value decreases by 1 each time it is read to one destination, or when reading multiple cells at the same time, read by connecting one header processing circuit and a large number of memories one-to-many. The broadcast function is realized by emptying the memory when the count value reaches O.

The cell switching device in the third invention detects the destination of a cell inputted from an incoming line, and then writes and accumulates the cell at high speed in a buffer memory selected by an incoming line space switch. writes the number of destinations to be broadcast to the broadcast cell counter as a count value, and each time it is read to one destination, the count value is decreased by 1 until the count value becomes 1. When reading the cell many times or reading multiple cells at the same time. The broadcast function is realized by making one-to-many connections and reading them using the outgoing space switch, and emptying the buffer when the count value becomes O.The broadcast cell counter is used for non-broadcast cells. No! Cells are read out once to empty the buffer, and a symbol indicating whether the stored cell is a broadcast cell or not is added to the buffer number of the accumulated cell in the buffer memory, and it is divided into destinations. By accessing the buffer memory based on the address managed for each destination and reading out the cells stored there at high speed, there are many chances to read cells from the same buffer memory and cell collisions at the time of reading are avoided. In addition, by outputting to the outgoing line connected to the buffer memory by the outgoing line space switch, there is less discard due to cell collision with a small number of buffer memories, and the switch that connects the buffer memory and the incoming line and outgoing line To realize a cell switching device that can reduce the scale of the cell switching device.

The cell switching device in the fourth invention detects the destination of cells input from the incoming line, and then multiplexes the cells into a buffer number selected by the buffer control circuit using the incoming line multiplexer and stores the multiplexed cells. For broadcast cells, the number of destinations to be broadcast is written as a count value in the broadcast cell counter, and each time it is read to one destination, the count value is decremented by 1, and the cell is read out many times until the count value becomes O. The broadcast function is realized by emptying the buffer when the count value becomes O. Non-broadcast cells do not use the broadcast cell counter, and each cell is read out once, emptying the buffer, and then being accumulated. A symbol indicating whether the stored cell is a broadcast cell or a non-broadcast cell is added to the buffer number of the stored cell and managed for each destination, and the buffer memory is accessed based on the address managed for each destination. By reading out the cells stored in the cell, a cell switching device capable of broadcasting is realized.

(Example) Hereinafter, the first invention will be explained with reference to the figures. In Figure 1, (11) to (In) are input cells consisting of a header part containing an outgoing line number as destination information and a data part. n
The input lines (2,) to (21) of the (n≧2) tree are m(
m>'2) This is the outgoing line.

(10) is a header processing circuit provided corresponding to each of the incoming lines (1), which detects the destination outgoing line (2) from the header part of the cell input from the corresponding incoming line (1).

(211) to (21n) are the input lines (II) to (1n)
An incoming line speed adjustment buffer is provided corresponding to each of the header processing circuits, and adjusts the speed by accumulating cells output from the header processing circuit and reading them out at high speed.

In addition, (11) respectively have buffer memory numbers #0.
#1. ... is assigned, the cells are stored at a specified address, and by specifying that address, the stored cells can be read out regardless of the order in which they are written (n≦p). buffer memory,
It differs from the conventional buffers (31) to (3) shown in FIG. 7 in that it has q buffers (23) that can store cells in one buffer memory (11). Further, the buffer (23) can write the number of destinations to which the cell is to be broadcast if the write cell is a broadcast cell, and the number 1 to which the cell is to be sent if it is not a broadcast cell. (12) is provided corresponding to each of the buffer memories (11),
For example, it is a storage control circuit that manages free addresses using a FIFO type memory and provides read addresses and write addresses to the associated buffer memory (11).

(13) is the input linear speed adjustment buffer (211) to (2
(14) is an incoming line space switch that selectively connects each buffer memory (11) to a predetermined outgoing line (2). ) to (22,) are selectively connected to the output line space switch.

(22+) to (22,) are the outgoing lines (2I) to (2,)
The buffer memory (111) to
(IL) is read out faster than the output line space switch (13
) is an outgoing line speed adjustment buffer that stores cells connected by the outgoing line and adjusts them to the outgoing line speed.

(15) controls the switching of the incoming space switch (13) to select the buffer memory (11) in which cells are stored, and also controls the switching of the outgoing space switch (14) to select the buffer memory (11) in which cells are stored. 11) is a buffer control circuit that outputs the cells accumulated in 11) to the outgoing line (2) designated by the header section in a predetermined order.

Also, in this buffer control circuit (15), (1
6) receives the destination outgoing line numbers (21) to (2-) of the cell detected at the time of cell arrival in the header processing circuit (10) associated with each incoming line (1), and stores the cell. (17) is a write buffer selection circuit that controls the switching of the line space switch (13) in order to select a buffer memory (11) and connect it to the corresponding header processing circuit (10). The output line number (2) sent from the write buffer selection circuit (16)
I) to (2,), the arrived cells are divided by destination, and the write address of the buffer on the buffer memory (11) where the cell is written is set to that buffer memory (1).
This is an address exchange circuit that obtains the address from the storage control circuit (12) corresponding to 1) and writes it to a queue for each destination, which will be described later.

Reference numeral (18) denotes a queue for each destination, which is composed of a FIFO type memory and is provided corresponding to each of the outgoing lines (2). This destination-specific queue (18) has a queue for each outgoing line (2) to which it is associated.
2) Buffer memory (
11) The above buffer address is transferred to the address exchange circuit (
17), cells are written in the order in which they arrive.

(19) determines the cell to be read from the buffer memory (11) by referring to this queue for each destination (18), and when the cell read number attached to the cell in the buffer is 2 or more, the cell to be read is The buffer address is stored in the storage control circuit (1
2), and if the number of read cells attached to the cells in the buffer is 1, the queue for each destination (18
) is sent as a read address to the storage control circuit (12) associated with the corresponding buffer memory (11), and in either case, the switching of the outgoing space switch (14) is controlled to This is a read buffer selection circuit that connects the buffer memory (11) with the outgoing line speed adjustment buffer associated with the corresponding outgoing line (2).

Next, the operation will be explained. Figure 2 ((), (0)
The operation up to writing a cell to the buffer, Figure 3 (a)
, (b) shows the operation of reading a cell from the buffer and outputting it to the output line. For simplicity, it is assumed that the number of people/output lines is 2, the number of buffer memories is 2.1, the number of buffers included in the memory is 2, and the processing speed is equal to the input/output line speed.

One or two cells enter the line (1
), the header processing circuit (10
) indicates whether the cell in question is a broadcast cell or not from its header, the destination outgoing line number (2+), and (
2t) as the destination information, and enter the incoming line number (t+).
, (12) Send the destination information of each cell in order to the write buffer selection circuit (1B). The cell is written to the incoming line rate adjustment buffer (21). Write buffer selection circuit (
16) determines the buffer memory number in which each cell is to be written in numerical order. However, if there is no free buffer in that memory, the next numbered buffer memory is selected. Broadcast cells have multiple destinations, but one cell is stored in one buffer. The incoming line space switch (13) connects the incoming line speed adjustment buffer y (21) in which the cell is written to the determined memory, and stores the cell in a predetermined buffer.

Figure 2 (a) shows a state in which cell A addressed to 0° is stored in buffer 00, and cell B arrives at incoming line (1,) and cell C arrives at (12). Figure 2 (0) shows this state. This is a state in which writing to two cells has been completed. First, the destination is (21)
and (22), the write buffer memory of broadcast cell B is selected. First, assume that buffer memory (1) is selected. Cell B is stored in the buffer (10) as cell B2 with the number of cells to be broadcast, and this buffer address (10
) to the outgoing line ('2I) and (22) in a destination-specific queue.0 Next, select the write memory of the cell C whose destination is the outgoing line (22). Since buffer memory 0 has free space, buffer memory 0 is selected. When the mounting buffer address O1 is determined, since the cell C is not a broadcast, the read number 1 is added to the cell and stored in the buffer as the cell CI, and the write buffer address 01 is sent to the outgoing line (2,) in a queue for each destination. Arrange.

Here, the cell write speed was set equal to the input and output lines, so cells A and B that arrived at the same time were stored in different buffer memories. However, if the write speed is increased by w (2≦W≦number of lines) times the input line, W in one memory in one time slot
For example, if there are no empty buffers in buffer memory 0 and two empty buffers in buffer memory (1), two cells can be stored in buffer memory (1) at twice the speed. However, one time slot is one processing time (time for one cell to arrive at the incoming line).

In FIG. 3, cell reading will be explained. FIG. 3(A) shows a state in which cells A1, B1, and C are stored in buffers 00°10, 01, and FIG. 3(B) shows one cell output from each outgoing line. Read a cell from the buffer address at the head of the queue for each destination in 1, (2
1) Since 00 is lined up at the head of the queue for each destination, cell A stored in buffer 00 is output to the outgoing line (2I), but cell A stored in buffer 00 is stored in the buffer and cell 2 represents the remaining number of cells to read, so reduce this number by 1, rewrite 2 to 1, leave the cell in the buffer, and read out 1 cell.The head of the queue destined for the outgoing line (22) Since IO are lined up, cell B stored in buffer IO is read out, but cell Bl is written in the buffer and the remaining number of reads for this cell is 1, so when cell B is read out, it is stored in buffer IO. 10 is open. The output cells are once written into the outgoing line speed adjustment buffer (22) and output to the outgoing line in accordance with the outgoing line speed. Here, since buffers 00 and 10 are in the same memory, both cells A and B could be output, but if the cells that you want to read at the same time are in the same memory, only one cell will be output, and the remaining cells will be in the buffer. Waits until the next read.

Here, the cell reading speed was set equal to the output line, but r
By multiplying by (2≦r≦number of outgoing lines), r cells can be read out from the same buffer memory in one time slot.

In the above embodiment, a single cell switching device is shown, but the cell switching device may be linked and sequentially connected in multiple stages for expansion.

In addition, as the destination information in the cell header section, we have shown that the outgoing line number is directly given corresponding to the outgoing line of the cell switching device, but some conversion processing such as giving a coded number to the destination information in the header section has been shown. You may do so.

In addition, in order to ensure that each buffer memory has almost the same performance as one large buffer memory shared by all incoming lines, we select the buffer memory with the least amount of reserved cells and write cells. The cell discard rate may be further reduced with respect to fluctuations in .

Alternatively, the header section and the data section may be structurally separated and transmitted using circuits with different speeds, and the header section and the data section may be respectively assigned to a plurality of signal lines arranged in parallel.

Furthermore, in the above embodiment, the incoming link speed is the same, but traffic can be concentrated by making the reading speed from the buffer memory faster than the incoming link speed, and vice versa. It is also possible to make it faster. Furthermore, when the cell switching devices are linked, the rate of cell discard between the cell switching devices can be further reduced by making the speed between stages higher than the incoming line speed.

Further, in the above embodiment, one address queue was provided for each outgoing line of the cell switching device, but a plurality of address queues are assigned to each outgoing line according to priority,
It is also possible to read cells with higher priority from the buffer memory first based on a code indicating priority added to the header of the cell other than the destination outgoing line.

Furthermore, if restrictions on operating speed are required, a serial/parallel conversion circuit or a parallel/serial conversion circuit may be provided at the front and rear stages of this cell switching device to process signals as parallel signals.

An embodiment of the second and third inventions will be described below with reference to the drawings. In the 344 diagram, (l,) to (1rl) are n (n≧2) incoming lines into which cells consisting of a header section including an outgoing line number as destination information and a data section are input, (21
) to (2,) are m (m≧2) outgoing lines through which cells are output according to the destination specified in the header.
(jo) is a header processing circuit that is provided corresponding to each of the incoming lines (1) and detects the destination outgoing line (2) from the header part of the cell input from the corresponding incoming line (1).

(21+) ~ (2in) is the input line (1+) ~ (in)
An incoming line speed adjustment buffer is provided corresponding to each of the header processing circuits, and adjusts the speed by accumulating cells output from the header processing circuit and reading them out at high speed.

In addition, (11) is the memory number #0, #1, respectively.・
... is assigned, p (n≦p) cells can be stored at a specified address, and by specifying that address, the stored cells can be read out regardless of the order in which they are written. A buffer memory (23) that stores cells in one buffer memory (11).
) in the conventional buffer (3,
) to (31). (12) is provided corresponding to each of the buffer memories (11), and manages free addresses using, for example, a FIFO type memory, and writes read addresses and write addresses to the associated buffer memories (11). This is a memory control circuit that provides

(13) is the input linear speed adjustment buffer (211) to (2
(14) is an incoming line space switch that selectively connects each buffer memory (11) to a predetermined outgoing line (2). ) to (22,) are selectively connected to the output line space switch.

(22+) to (22,) are the outgoing lines (21) to (2,)
The buffer memories (11+) to
(ttp) and is read out faster than the outgoing space switch (1
3) is an outgoing line speed adjustment buffer that stores connected cells and adjusts them to the outgoing line speed.

(15) controls the switching of the incoming space switch (13) to select the buffer memory (11) in which cells are stored, and controls the switching of the outgoing space switch (14) to select the buffer memory (11). ) is a buffer control circuit that outputs the cells stored in the buffer in a predetermined order to the output line (2) specified by the header.

Also, in this buffer control circuit (15), (1
6) receives the destination outgoing line number (2I) to (2,) of the cell detected when the cell arrives at the header processing circuit (lO) associated with each incoming line (1), and stores the cell. A write buffer selection circuit controls the switching of the line space switch (13) in order to select a buffer memory (11) to be processed and connect it to the corresponding header processing circuit (10). (17) is the outgoing line number (2,) sent from this buffer selection circuit (16).
(Referring to 2-, the arrived cells are divided by destination, and the write address of the buffer on the buffer memory (11) in which the cell has been written is sent from the storage control circuit (12) corresponding to the buffer memory (11). This is an address exchange circuit that obtains the address information and writes it to a queue for each destination, which will be described later.

Reference numeral (18) denotes a queue for each destination, which is constituted by a FIFO type memory and is provided corresponding to each of the outgoing lines (2). This destination-specific queue (18) has a queue for each outgoing line (2) to which it is associated.
Buffer memory (1) in which cells destined for 2) are stored
1) The buffer address above and the symbol indicating whether the cell is a broadcast cell or not are the addresses of the address exchange circuit (1).
7), cells are written in the order in which they arrive.
(24) is a queue for each destination at the broadcast cell counter (18)
is installed in parallel.

This has an area for writing the number of broadcast cells to be read for all buffers.Broadcast cells stored in one buffer are copied and output to multiple destinations, but when one is read, the broadcast cell By decrementing the value of the counter (24) by 1, it is possible to recognize that the broadcast cell has been output to all predetermined destinations and to know when to release the buffer.

(19) is the queue for each destination and the broadcast cell counter (2
Determine the cell to be read from the buffer memory (11) by referring to 4), and if the buffer address read from the destination queue (18) does not have a broadcast symbol, use this buffer address as the read address. , a storage control circuit (
12) and controls the switching of the outgoing line space switch (14) to connect the buffer memory (11) to the outgoing line speed adjustment buffer associated with the corresponding outgoing line (2). It is.

Next, the operation will be explained. Figure 5 ((), (b)
Operation up to writing cells into the buffer, Figure 6 (a)
, (b) shows the operation of reading a cell from the buffer and outputting it to the output line. For simplicity, it is assumed that the number of people/outgoing lines is 2, the number of buffer memories is 2.1, the number of buffers included in the buffer memory is 2, and the processing speed is equal to the input/output line speed.

One or two cells enter the line (1
), the header processing circuit (lO
) indicates from its header whether the cell in question is a broadcast cell or not, the destination address, line number (21),
(22) is read as the destination information, and the incoming line number (
t+), (12) sequentially sends the destination information of each cell to the write buffer selection circuit (16). The cell is placed in the input line speed adjustment buffer (21). The write buffer selection circuit (16) determines the buffer memory number to which each cell is written in numerical order. However, if there is no free buffer in that buffer memory, the next numbered buffer memory is selected. Broadcast cells have multiple destinations, but one cell is stored in one buffer. The input line space switch (13) connects the input line speed adjustment buffer (21) in which the cell is written to the determined buffer memory, and stores the cell in a predetermined buffer.

Figure 5 (a) shows a state in which when cell A is stored at 0° in buffer 00, cell B arrives at incoming line (l,) and cell C arrives at (12), and Figure 5 (b) shows this state. This is a state in which writing to two cells has been completed. First, the destination is (2,)
and (22), the write memory of broadcast cell B is selected. First, assume that memory (1) is selected. Cell B is stored in the buffer 10, and Ion with the broadcast cell symbol, for example m, added to this buffer address is added to the outgoing line (2+), (2
2) Queue by destination. 2, which is the number of times the cell has been read, is written to the location corresponding to the buffer 10 of the broadcast cell counter.0 Next, the write buffer memory of the cell C whose destination is the outgoing line (22) is selected. Since it is not possible to write two cells to the same buffer at the same timing, buffer memory O is selected. When the write buffer address O1 is determined, the cell is stored in the buffer, and oin, which has a non-broadcast symbol such as n added to the address, is set as the outgoing line (2
2) Queue by destination. Nothing is written to the broadcast cell counter.

Here, the cell write speed was set equal to the input and output lines, so cells A and B that arrived at the same time were stored in different memories. However, if the write speed is multiplied by the input line W (2≦W≦number of input lines), 1 time W cells can be written to one memory in a lot 0 For example, if there are no empty buffers in buffer memory 0 and two empty buffers in buffer memory 1, at double the speed, two cells will be stored in buffer memory 1. can. However, one time slot is one processing time (time for one cell to arrive at the incoming line).

In FIG. 6, cell reading will be explained. FIG. 6(A) shows a state in which cells A, B, and C are stored in buffers 00, 10, and 01, and FIG. 6(B) shows one cell output from each outgoing line. Read the cell from the buffer address at the head of the queue for each destination in Figure 6 (a). (21) Since 00m is lined up at the head of the queue for each destination, the outgoing line (2,) has a buffer address of 00m. Outputs the cell A° stored in , but since m is the symbol for broadcast, the number written in OO of the cell counter is decremented by 1, and 2
is rewritten to 1, and one cell is read out while leaving the cell in the buffer.

10n is lined up at the head of the queue destined for the outgoing line (2,), but since this is not a broadcast cell, when cell B stored in the buffer IO is read out, the buffer 10 is released. The output cells are once sent to the output speed adjustment buffer (2
2) and output to the outgoing line according to the outgoing line speed.

Here, buffer 00 and buffer 10 are in different memories, so both cell A and cell B could be output, but if the cells that you want to read at the same time are in the same memory, only one cell will be output, and the remaining cells will be stored in the buffer and then Wait until it is read.

Here, the reading speed of the cells is set to be the same based on the output line, but if it is multiplied by r (2≦r≦number of output lines), r cells can be read out from the same buffer memory in one time slot.

In the above embodiment, a single cell switching device is shown, but the cell switching device may be linked and sequentially connected in multiple stages for expansion.

In addition, as the destination information in the cell header section, we have shown that the outgoing line number is directly given corresponding to the outgoing line of the cell switching device, but some conversion processing such as giving a coded number to the destination information in the header section has been shown. You may also perform a row.

In addition, in order to ensure that each buffer memory has almost the same performance as one large buffer memory shared by all incoming lines, we select the buffer memory with the least amount of reserved cells and write cells. The cell discard rate may be further reduced with respect to fluctuations in .

Alternatively, the header section and the data section may be structurally separated and transmitted using circuits with different speeds, and the header section and the data section may be respectively assigned to a plurality of signal lines arranged in parallel.

Furthermore, in the above embodiment, the incoming link speed is the same, but traffic can be concentrated by making the reading speed from the buffer memory faster than the incoming link speed, and vice versa. It is also possible to make it faster. Furthermore, when the cell switching devices are linked together, by making the speed between the stages higher than the incoming line speed, the cell discard rate between the stages of the cell switching device can be further reduced.

Further, in the above embodiment, one address queue was provided for each outgoing line of the cell switching device, but a plurality of address queues are assigned to each outgoing line according to priority,
It is also possible to read cells with a high priority from the buffer memory first based on a code indicating priority added to the header of the cell other than the destination outgoing line.

Furthermore, if restrictions on operating speed are required, a serial/parallel conversion circuit or a parallel/serial conversion circuit may be provided at the front and rear stages of this cell switching device to process signals as parallel signals.

An embodiment of the fourth invention will be described below with reference to the drawings. In FIG. 7, (1+) to (1o) represent n (n≧2) incoming lines into which cells consisting of a header section including an outgoing line number as destination information and a data section are input, and (2I) to ( 2,) are m (m≧2) outgoing lines through which cells are output according to the destination specified in the header. (10) is a header processing circuit provided corresponding to each of the incoming lines (1), which detects the destination outgoing line (2) from the header part of the cell input from the corresponding incoming line (1).

(30) is an incoming line multiplexer that multiplexes cells arriving at one incoming line at n times the speed. In addition, (l!) is a buffer memory that stores the cells at a specified address and can read out the stored cells by specifying that address, regardless of the order in which they were written. The buffer memory (11) has nine buffers (23) that can store cells.

(12) is provided corresponding to this buffer memory (11), and manages free addresses using, for example, a FIFO type memory.
1) is a storage control circuit that provides a read address and a write address.

(32) is an outgoing line separator that separates the cells multiplexed and output from the buffer memory (11) into predetermined outgoing lines and outputs the separated cells.

(15) is a buffer control circuit which outputs the cells stored in the buffer memory (11) to the outgoing line (2) designated by the header section in a predetermined order.

Also, in this buffer control circuit (15), (1
7) refers to the outgoing line numbers (2,) to (2,) sent from the header processing circuit (lO), sorts the arrived cells by destination, and stores the cells in the buffer memory (11) in which the cells are written. ) is an address exchange circuit that obtains the write address of the buffer above from the storage control circuit (12) and writes it to a destination-specific queue to be described later.

Reference numeral (18) denotes a queue for each destination, which is constituted by a FIFO type memory and is provided corresponding to each of the outgoing lines (2). This destination-specific queue (18) has a queue for each outgoing line (2) to which it is associated.
Buffer memory (1) in which cells destined for 2) are stored
1) The buffer address above and the symbol indicating whether the cell is a broadcast cell or not are the addresses of the address exchange circuit (1).
7), cells are written in the order in which they arrive. (
24) is a broadcast cell counter and is provided in parallel with the destination-specific queue (18).

This has an area for writing the number of broadcast cells read for all buffers.Broadcast cells stored in one buffer are copied and output to multiple destinations, but when one is read, the broadcast cell counter ( By reducing the value of 24) by 1, it is possible to recognize that the broadcast cell has been output to all predetermined destinations and to know the timing to release the buffer.

Next, the operation will be explained. Figure 8 ((), (B) shows the operation up to writing the cell into the buffer, Figure 9 (A), (
D) shows the operation of reading cells from the buffer and outputting them to the output line.For simplicity, the number of people and output lines is assumed to be 2.1 and the number of buffers included in the buffer memory is 4.

One or two cells enter the line (1
), the header processing circuit (10
) indicates from its header whether the cell in question is a broadcast cell or not, and the destination outgoing line number (21), (
22) as the destination information, and enter the incoming line number (1+).
, (1*) sequentially sends the destination information of each cell to the address exchange circuit (17). Although one broadcast cell has multiple destinations, one cell is stored in one buffer. Memory control circuit (1
2) selects the write buffer 1 number.

Figure 8 (a) shows a state in which cell B and cell C arrive at incoming line (l,) and (ld) when cell A M is stored in buffer 00, and Figure 8 (0) shows these two cells. This is the state where writing of the cell has been completed.The destination is (2,) and (2
2) Store the broadcast cell B in the buffer 10, and add the broadcast cell symbol, for example m, to the buffer address.
m is placed in queues for destinations addressed to outgoing lines (21) and (22). Write 2, which is the number of times the cell has been read, in the area corresponding to buffer 10 of the broadcast cell counter 0 Next, write buffer 01 of cell C whose destination is the outgoing line (22)
, store a cell in the address, and enter a non-broadcast symbol, for example n
The Oln with the ``Oln'' attached is placed in a destination-specific queue for the outgoing line (22). Nothing is written to the broadcast cell counter.

In FIG. 9, cell reading will be explained. FIG. 9(A) shows a state in which cells A1, B1, and C are stored in buffers 00°10, 01, and FIG. 9(B) shows one cell output from each outgoing line. Read the cell from the buffer address at the head of the queue for each destination in Figure 9 (a).Since OOm is lined up at the head of the queue for each destination addressed to (2+), the outgoing line (2I) is read from the buffer address at the head of the queue for each destination. The stored cell A is output, but since m is a broadcast symbol, the number written in 00 of the cell counter is decremented by 1, 2 is rewritten as 1, and cell and cell are left in the buffer and 1 cell is output. Read out.

10n is lined up at the head of the queue destined for the outgoing line (22), but since this is not a broadcast cell, when cell B stored in buffer 1o is read out, buffer 10 is released.

In the above embodiment, a single cell switching device is shown, but the cell switching device may be linked and sequentially connected in multiple stages for expansion.

In addition, as the destination information in the cell header section, we have shown that the outgoing line number is directly given corresponding to the outgoing line of the cell switching device, but some conversion processing such as giving a coded number to the destination information in the header section has been shown. You may do so.

In addition, in order to ensure that each buffer memory has almost the same performance as one large buffer memory shared by all incoming lines, we select the buffer memory with the least amount of reserved cells and write cells. The cell discard rate may be further reduced with respect to fluctuations in .

In addition, although the selection of the buffer number in the buffer memory into which a cell is to be written was performed by managing the write address and read address in the memory control circuit (12), other methods may be used, such as creating an address chain. .

Alternatively, the header section and the data section may be structurally separated and transmitted using circuits with different speeds, and the header section and the data section may be respectively assigned to a plurality of signal lines arranged in parallel.

Furthermore, the cell discard rate between cell switching device stages can be further reduced.

Further, in the above embodiment, one address queue was provided for each outgoing line of the cell switching device, but a plurality of address queues are assigned to each outgoing line according to priority,
It is also possible to read cells with higher priority from the buffer memory first based on a code indicating priority added to the header of the cell other than the destination outgoing line.

Furthermore, if restrictions on operating speed are required, a serial/parallel conversion circuit or a parallel/serial conversion circuit may be provided at the front and rear stages of this cell switching device to process signals as parallel signals.

[Effect of the Invention] As described above, according to the first invention, after detecting the destination of a cell input from the incoming line, the incoming line speed w(
1≦W≦number of input lines), the addresses of the accumulated cells on the buffer memory are managed for each destination, the buffer memory is accessed based on the addresses managed for each destination, and the cells are accumulated there. r of the output speed of the cell
Since the configuration is configured to read data at a speed twice as fast as (1≦r≦number of outgoing lines) and output it to the outgoing line connected to the buffer memory using the outgoing line space switch, cells can be exchanged without increasing the speed too much. Furthermore, since the number of buffer memories can be reduced, it is possible to reduce the cell discard rate that occurs when the number of cells written exceeds the capacity of the buffer memory, without increasing the scale of the space switch. In addition, since the number of broadcast cells is always managed in the buffer that stores the cells, and non-broadcast cells are handled simultaneously, there is no need to increase the number of buffer memories or reduce the utilization rate of outgoing lines. This has the effect of providing a cell switching device that can implement a broadcast function.

Further, according to the second invention, after detecting the destination of a cell input from an incoming line, it is written and accumulated in the memory at high speed, and for broadcast cells, the number of destinations to be broadcast is used as a count value. When reading out multiple cells at the same time, the count value is decreased by 1 each time it is read to a destination, and when reading multiple cells at the same time, one header processing circuit and multiple memories are used. The broadcast function is realized by connecting one-to-many and reading the buffer, and emptying the buffer when the count value becomes 0.The broadcast cell counter is not used for non-broadcast cells, and one cell is Empty the memory by reading it out once, and add a symbol to the buffer number of the stored cell in the memory to indicate whether the stored cell is a broadcast cell or not, and manage it for each destination. In addition, because it handles cells that are not broadcast at the same time, it is possible to obtain a cell switching device that can realize a broadcast function without increasing the number of buffer memories or reducing the utilization rate of outgoing lines.

According to the third invention, after detecting the destination of the cell input from the incoming line, the cell is transferred to the buffer memory selected by the incoming line space switch at a speed of the incoming line speed w (1≦W≦number of incoming lines). The addresses of the accumulated cells on the buffer memory are managed for each destination, and the buffer memory is accessed based on the address managed for each destination, and the cells accumulated there are transferred to the output line speed r( Since the configuration is configured such that the data is read out at a speed of 1≦r≦number of outgoing lines) and output to the outgoing line connected to the buffer memory by the outgoing line space switch, cells can be exchanged without increasing the speed too much. Furthermore, since the number of buffer memories can be reduced, the cell discard rate that occurs when the number of cells written exceeds the capacity of the buffer memory can be reduced without increasing the scale of the space switch.

In addition, by constantly managing the number of broadcast cells by setting up a broadcast cell counter, the number of broadcast cells can be handled simultaneously with non-broadcast cells. Therefore, broadcast cells can be broadcast without increasing the number of buffer memories or reducing the utilization rate of outgoing lines This has the effect of providing a cell switching device that can realize the functions.

According to the fourth invention, after detecting the destination of the cells input from the incoming line, the incoming line multiplexer multiplexes the cells at the speed of the number of incoming lines and stores them in the buffer memory selected by the buffer control circuit. , managing the addresses of the accumulated cells on the buffer memory for each destination, and accessing the buffer memory based on the addresses managed for each destination;
The cells stored there are read out, multiplexed by an outgoing line Il device, and the cells output from the buffer memory are separated and outputted to each destination outgoing line, and the broadcast cells are the number of broadcast cells. By providing a broadcast cell counter and constantly managing cell exchange, it is possible to realize the broadcast function without increasing the number of buffers or reducing the utilization rate of outgoing lines since non-broadcast cells are handled at the same time. There is an effect that the device can obtain.

[Brief explanation of the drawing]

′! FIG. 81 is a block diagram showing a cell switching device according to an embodiment of the first invention, FIGS. 2(4) and (0) are diagrams showing an example of cell writing according to the first invention, and FIGS. 0
) is an example of the cell readout of the first invention, and FIG. 4 is an example of the second invention.
and a block diagram showing a cell switching device according to an embodiment of the third invention, FIG. 5 is a diagram showing an example of cell writing according to the second invention, and FIG. FIG. 7 is a block diagram showing a cell switching device according to an embodiment of the fourth invention, and FIG. 8 (4), (D) is an example of a readout diagram.
FIG. 9 (4) is an example of cell writing according to the fourth invention.
, (0) is an example diagram of cell readout of the fourth invention, the first
FIG. 0 is a block diagram showing a conventional cell switching device, and FIG. 11 is a time chart showing signal timing in each part thereof. (11) to (tn) are incoming lines, (2,) to (2- are outgoing lines,
(3,) ~ (3 nose) is a buff American sled, (61) ~ (6
L) is an outgoing line selection circuit, (10+) to (ton) are header processing circuits, (lil) to (11- are buffer memories,
(12+) to (12,) are storage control circuits, (13) is an incoming space switch, (14) is an outgoing space switch, (15)
) is a buffer control circuit, (16) is a write buffer selection circuit, (17) is an address exchange circuit, (181) to (
ta, ) is an address queue, (19) is a read buffer selection circuit, (211) to (21,,) are input line speed adjustment buffers, (221) to (22n) are output line speed adjustment buffers, (23+1) to (23□) is a buffer, (24
) is a broadcast cell counter, (30) is an incoming multiplexer, (31
) is the outgoing line separator. In each figure, the same reference numerals refer to the same or corresponding parts.Figure 2, Figure 3, Figure 9, Figure 11.

Claims (4)

[Claims] (1) Multiple incoming lines that input broadcast or non-broadcast cells consisting of a data section and a header containing destination information for the data section, and multiple outgoing lines that output cells to designated destinations according to the destination information. and a header processing circuit provided for each incoming line to detect destination information from the header of an input cell and whether the cell is a broadcast or non-broadcast cell, a plurality of buffer memories that add a count value of 1 to a cell, add the number of destinations as a count value to a broadcast cell, write it to each address by address specification, and subtract 1 from the count value when reading a cell;
an incoming line space switch that connects these buffer memories and the header processing circuit; an outgoing line space switch that simultaneously outputs read cells to one or multiple outgoing lines according to destination information; and the incoming line space switch. , selects a buffer memory in which the cell is to be written, causes the cell to be written into the buffer memory at a speed higher than the input linear speed, and sets the buffer number in the buffer memory of the written cell to the cell. Based on this, the cells are read from the buffer memory in a predetermined order at a speed higher than the outgoing line speed, and the cells are output to the outgoing line specified by the header part. A cell switching device comprising: a buffer control circuit for controlling the outgoing line space switch. (2) Multiple incoming lines that input broadcast or non-broadcast cells consisting of a data section and a header containing destination information for the data section, and multiple outgoing lines that output cells to designated destinations according to the destination information. and a header processing circuit provided for each incoming line to detect destination information from the header of the input cell and whether the cell is a broadcast or non-broadcast cell, and a count value for the number of read broadcast cells. In addition to writing non-broadcast cells and broadcast cells to each address by specifying addresses, non-broadcast cells are emptied after one read, and broadcast cells are read multiple times at different timings. a memory that can be emptied when the value of the broadcast cell counter becomes 0; a buffer control device that manages addresses in the memory where cells are stored; and a device that connects the memory and an incoming line. and a device for connecting the memory and an outgoing line. (3) Multiple incoming lines that input broadcast or non-broadcast cells consisting of a data section and a header containing destination information for the data section, and multiple outgoing lines that output cells to designated destinations according to the destination information. and a header processing circuit provided for each incoming line to detect destination information from the header of the input cell and whether the cell is a broadcast or non-broadcast cell, and a count value for the number of read broadcast cells. In addition to writing non-broadcast cells and broadcast cells to each address by specifying addresses, non-broadcast cells are emptied after one read, and broadcast cells are read multiple times at different timings. a plurality of buffer memories that can be emptied when the value of the broadcast cell counter becomes 0; an incoming space switch that connects the header processing circuit and a predetermined buffer memory; A buffer memory in which the cell is written is selected by controlling an outgoing line space switch that simultaneously outputs to one or multiple outgoing lines according to the information and the incoming line space switch, and at a speed higher than the input line speed. The cells are written in the buffer memory, and the buffer numbers of the written cells in the buffer memory are managed for each destination of the cells, and based on this, the cells are written in a predetermined order at a speed higher than the output speed. and a buffer control circuit that controls the outgoing line space switch so that the cell is read from the buffer memory and output to the outgoing line specified by its header. Device. (4) Multiple incoming lines that input broadcast or non-broadcast cells consisting of a data section and a header containing destination information for the data section, and multiple outgoing lines that output cells to specified destinations according to the destination information. and a header processing circuit provided for each incoming line to detect destination information from the header of the input cell and whether the cell is a broadcast or non-broadcast cell, and a count value for the number of read broadcast cells. In addition to writing non-broadcast cells and broadcast cells to each address by specifying addresses, non-broadcast cells are emptied after one read, and broadcast cells are read multiple times at different timings. A buffer memory that can be emptied when the value of the broadcast cell counter becomes 0 and can store a plurality of cells; An incoming line multiplexer for writing to the buffer memory, an outgoing line separator that separates multiplexed and read cells into one or multiple outgoing lines according to destination information and outputs them simultaneously, and an outgoing line separator for storing cells. 1. A cell switching device comprising: a buffer control circuit that maintains the order of cells by managing the addresses of the buffer memory for each cell destination outgoing line.