JPH0417476A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To prevent occurrence of lateral stripe noise and flicker in a picked-up pattern by controlling a charge storage time of a solid-state image pickup element to be an integral number of multiple of an intermittent period of a ray from an object. CONSTITUTION:A charge storage start pulse from a timing generating circuit 22 and timing of a readout pulse are controlled by a control circuit 21 and the charge storage time of a CCD 1 is made coincident with a lighting period of a display device. That is, the charge storage start pulse is delayed for a prescribed time with respect to the readout pulse to sweep out the undesired charge stored in the a CCD 1 from the readout pulse to the charge storage start pulse. Since the display device is lighted, e.g. once without fail for the charge storage time of the CCD 1, the occurrence of a period when the display device is lighted twice or not lighted at all is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Industrial Application Field The present invention relates to a solid-state imaging device that receives intermittent light beams from a subject and photographs the subject using a synchronization signal with a frequency different from the intermittent frequency of the light beams. Regarding.

B0 Summary of the Invention The present invention has a solid-state image pickup device whose charge accumulation time can be varied and a control means for controlling the charge accumulation time of the solid-state image pickup device, and uses an object such as a computer that emits or reflects intermittent light. When photographing a subject illuminated by light such as a display screen or a fluorescent lamp using a synchronization signal with a frequency different from the intermittent frequency, the control means controls the charge accumulation time of the solid-state image sensor from the subject. By controlling the intermittent period of the light beam to an integer multiple, it is possible to prevent horizontal stripe-like noise and so-called flicker that occur on the screen when captured images are displayed on a monitor receiver. .

C0 Conventional technology For example, fluorescent lamps, mercury lamps, etc. are driven by a commercial AC power source during boat fishing, and flash at a frequency twice the commercial frequency. When a subject is photographed with a video camera such as a solid-state imaging device under such a light source, so-called flicker occurs. As a method for solving this problem, there is known a reading method for a solid-state image pickup device disclosed in Japanese Patent Laid-Open No. 63-207286.

In this method, a solid-state image sensor C is composed of photoelectric conversion elements arranged in a matrix and a charge-coupled device for reading out the charges accumulated in these photoelectric conversion elements.
Flicker is prevented by using a CCD (hereinafter referred to as a CCD) and setting the charge accumulation time of one field of the CCD to an integral multiple of a half cycle of the commercial AC power supply.

Also, for example, when photographing the screen of a television receiver with a video camera, the television receiver is compatible with so-called NTSC,
If a television (hereinafter referred to as TV) system such as PAL is adopted, the light emitting cycle of the television receiver can be adjusted by synchronizing the video camera (external synchronization) using various synchronization signals of the television receiver. You can synchronize the video camera to avoid flickering, etc.
It is known that it is possible to photograph the screen of a television receiver.

D0 Problems to be Solved by the Invention By the way, for example, as shown in FIG. When displaying on 1i52, the frequency of the vertical synchronization signal of the display 50 (hereinafter referred to as synchronization frequency) is significantly different from the synchronization frequency of TV broadcasting, so horizontal stripe-like noise occurs on the screen of the monitor receiver 52, resulting in poor image quality. There was a problem with deterioration.

Specifically, the cycle for displaying one screen of the display 50, that is, the synchronization frequency, is f□, the field frequency of the video camera 51 and monitor image reception 1152 is fFll, and the charge accumulation time of the CCD of the video camera 51 is TCMG, for example, TCMG〉l/fosr
Then, as shown in the light emission output of the display 50 in FIG. 9A, there is a region where the display 50 emits light twice within one charge accumulation time rcHa of the CCD (the region shown with diagonal lines in FIG. 9A). occurs, and the video camera 5 in Figure 9B
As shown in the output No. 1, the level of the output video signal of the video camera 51 is doubled corresponding to the area where the light is emitted twice, and horizontal stripe-like noise is generated on the screen of the monitor receiver 52. Also, for example, TCM. If 〈1/fDsp,
An area where the display 50 does not emit light occurs within one charge accumulation time TCMG of the COD, and the level of the output video signal of the video camera 51 becomes almost zero corresponding to that area, and the level of the output video signal of the video camera 51 becomes almost zero, and the level of the output video signal of the monitor receiver 52 is Streaky noise occurs.

The above-mentioned problems arise because the method for reading out solid-state image sensors disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 63-207286 is intended to prevent flicker caused by commercial AC power at a specific frequency. I couldn't solve it though. Furthermore, in conventional video cameras that can change the so-called shutter speed, the shutter speed is, for example, 1/60.1/100.1/250.1150.
Since the shutter speed and the synchronization frequency fD of the display 50 are fixed at 0, etc. F did not match, and the above problem could not be solved.

The present invention was made in view of the above circumstances, and it is possible to photograph a subject illuminated by intermittent light rays from a subject, such as a display screen of a computer or the like, and a subject illuminated by intermittent light rays.
When photographing with, for example, an NTSC or PAL solid-state imaging device that uses a vertical synchronization signal with a frequency different from these synchronization frequencies, it prevents the occurrence of horizontal stripe-like noise and flicker on the photographic screen due to the difference in frequency. The purpose of the present invention is to provide a solid-state imaging device that can perform

81 Means for Solving the Problems In order to solve the above problems, the solid-state imaging device according to the present invention receives an intermittent light beam from a subject, and uses a synchronization signal of a frequency different from the intermittent frequency of the light beam to detect the intermittent light beam. A solid-state imaging device for photographing a subject, comprising a solid-state imaging device whose charge accumulation time is variable, and a control means for controlling the charge accumulation time of the solid-state imaging device, the control means controlling the charge accumulation time of the solid-state imaging device. It is characterized in that the charge accumulation time is controlled to be an integral multiple of the intermittent period of the light beam.

Further, it has a detection means for detecting the intermittent frequency of the light beam from the subject based on the imaging output from the solid-state imaging device,
Based on the detection information from the detection means by the control means,
It is characterized in that the charge accumulation time of the solid-state image sensor is controlled to be an integral multiple of the intermittent period of the light beam.

Further, the control means horizontally controls the charge accumulation period of the solid-state image sensor by controlling the charge sweep period for discarding unnecessary accumulated charges and the accumulated charge readout timing based on the detection information from the detection means. It is characterized by control with an accuracy of one period or less of the synchronization signal.

F1 action In the solid-state imaging device according to the present invention, the control means controls the charge accumulation time of the solid-state imaging element to an integral multiple of the intermittent period of the light beam from the subject, thereby producing a video signal free from flicker and horizontal stripe-like noise. Output.

G. Example Hereinafter, an example of a solid-state imaging device according to the present invention will be described with reference to the drawings.

In Figure 1, a solid-state image sensor (hereinafter referred to as a CCD) has a structure in which photoelectric conversion elements are arranged in a matrix and the charges accumulated in these charge conversion elements are read out using a charge coupled device.
) 1 is of the so-called frame transfer type, interline transfer type, or hybrid transfer type, and the charge storage time can be controlled from the outside.

The imaging signal from the CCD 1 is sent to a signal processing circuit 2, subjected to predetermined signal processing, and then taken out from a terminal 3 as a video signal compliant with, for example, the NTSC system or the PAL system.

On the other hand, the detection circuit 10 is composed of switches 11, 14, 20, an area setting circuit 12, an average value circuit 13, a field switching circuit 15, a hold circuit 16, 17, a comparator circuit 18, and an inverting amplifier 19. A luminance signal (hereinafter referred to as Y signal) from the detection circuit 10 is sent to the switch 11 of the detection circuit 10 and the area setting circuit 12. The switch 11
is, for example, an analog switch, which is switched by a control signal from the area setting circuit 12 that turns the switch on for a predetermined period of time, and sends the Y signal to the average value circuit 13 for a predetermined period of time.

The average value circuit 13 receives the Y supplied within the predetermined time.
The average value of the signal is determined, and the output (average value) of the average value circuit 13 is sent to the selection terminal of the switch 14. The switch 14 is switched by a signal obtained by dividing the frequency of the vertical synchronizing signal from the field switching circuit 15 by two, that is, a signal with a period twice the field period, and the average value from the average value circuit 13 is controlled by a signal whose frequency is twice the field period. The signal is alternately sent to the hold circuits 16 and 17 via the switch 14 every l field.

The hold circuits 16 and 17 alternately hold the average values from the average value circuit 13 for each field and send the held average values to the comparison circuit 18.

The comparison circuit 18 outputs a comparison result for the first time when the difference between the output of the hold circuit 16 and the output of the hold circuit 17 is equal to or greater than a predetermined threshold value, and when the difference is equal to or less than a predetermined threshold value, the output becomes zero. The comparison circuit 18 sends the comparison result to the inverting amplifier 19 and the selected terminal 20a of the switch 20, and the output of the inverting amplifier 19 is sent to the other selected terminal 20b of the switch 20. It will be done.

The switch 20 is switched and controlled by a signal having a period twice the field period from the field switching circuit 15, and inverts the comparison result from the comparison circuit 18 and the comparison result from the inverting amplifier 19. Values, ie, those with inverted polarities, are alternately selected, and the selected comparison results are sent to the control circuit 21. That is, if the average value held in the hold circuit 16 or 17 at a certain point in time is ■7, and the average value held at the previous time is ■7-1, then v7■*-1 is always obtained. The comparison result is sent to the control circuit 21 via the switch 20.

The control circuit 21 sends a control signal to the timing generation circuit 22 based on the comparison result from the detection circuit 10.

The timing generation circuit 22 forms charge accumulation start pulses and readout pulses (hereinafter referred to as readout pulses) for the CCDI based on the control signal from the control circuit 21, and drives these charge accumulation start pulses and readout pulses. It is sent to circuit 23.

The driver circuit 23 is similar to the timing generation circuit 22.
A shutter pulse for sweeping away unnecessary accumulated charges is formed based on the charge accumulation start pulse from the CCDI.
send to

Thus, in this embodiment, the CCD 1 is used as a solid-state imaging device with a variable charge accumulation time, the control circuit 21 is used as a control means for controlling the charge accumulation time of the CCD 1, and the switches 11 to A detection circuit IO composed of 20 is used as a detection means for detecting the intermittent frequency of the light beam from the subject based on the damage output from the CCD 1.

Here, FIG. 2 shows a screen of a display having the above-mentioned configuration and a field frequency lower than the synchronous frequency rose. rr
3 shows the light emitting output of the display when photographed with a solid-state imaging device using a 3D image sensor, the timing of the charge accumulation start pulse, and the readout pulse.

By the way, as mentioned above, for example, the charge accumulation time factor CMG of the CCD l is the time for the display to emit light once (hereinafter referred to as display light emitting period) 1/f++s
If it is longer than p (TCMG>1/fosr), a region where the display emits light twice occurs within the charge accumulation time TCMG, and conversely, if the charge accumulation time TCNG of CCD 1 is shorter than the display emission period 1/f□ ( TCIIG
<1/fosp), a region occurs where the display does not emit light even once within the charge accumulation time TCMG, and horizontal stripe-like noise occurs on both sides of the image.

Therefore, in the present invention, the charge accumulation time TCHG of the CCD 1 of the solid-state imaging device is made to match an integral multiple of the light emission period of the display, thereby preventing the generation of horizontal stripe-like noise.

That is, as shown in FIG. 2, for example, the control circuit 21 controls the timing of the charge accumulation start pulse and the readout pulse from the timing generation circuit 22, and the charge accumulation time TCIIG of the CCD 1 is adjusted to the display light emission period 1/f.
Match nsr. Specifically, the charge accumulation start pulse is 1/hp 1/fosr with respect to the readout pulse.
The delay is made so that unnecessary charges accumulated in the CCDI between the readout pulse and the charge accumulation start pulse are swept away.

As a result, an image corresponding to the signal indicated by diagonal lines in FIG. 2 is photographed. At this time, within the charge accumulation time TCMG of the CCD 1, the display always emits light once, for example, and it is possible to prevent the occurrence of a region that emits light twice or a region that does not emit light at all, as in the conventional case.

By the way, the above-mentioned unnecessary accumulated charges must be swept away during blanking of the horizontal synchronization signal so as not to affect the output video signal. Therefore, the charge accumulation time TCMH of CCD 1 is controlled by the horizontal synchronization signal period (
This is discrete control in units of 18 hours (hereinafter referred to as 18 hours). Therefore, control for 18 hours or less is performed by changing the phase of the readout pulse.

Specifically, step S of the flowchart shown in FIG.
In the TI, the control circuit 21 sets the charge accumulation time TCNG of the CCDI to 1/60 seconds in the case of the NTSC system, sets the charge accumulation time TCHG to 1150 seconds in the case of the PAL system, and proceeds to step ST2. .

Here, FIG. 4 shows the Y signal from the signal processing circuit 2 and the control signal (hereinafter referred to as gate pulse) from the area setting circuit 12 when the charge accumulation time TeNG of the CCD 1 is longer than the display light emission period 17f□2. The relationship with the comparison results (V, Vn-+) from the detection circuit 10 is shown. Further, FIG. 5 shows the relationship between the Y signal, the gate pulse, and the comparison result from the detection circuit IO when the charge accumulation time TCHG is shorter than the display light emission period 1/f□. As shown in FIG. 4C, the charge accumulation time T of CCD 1
When CNG is longer than the display light emitting period 1/fosr, an edge (hereinafter referred to as (10--) edge) that changes from a positive value to a negative value occurs in the comparison result from the detection circuit IO, and as shown in FIG. As shown in , the charge accumulation time TCHG
is shorter than the display light emitting period 1/f++sr,
An edge that changes from a negative value to a positive value (hereinafter referred to as a (--+) edge) occurs in the comparison result from the detection circuit 10. Therefore, the timing of the charge accumulation start pulse and the lead-out pulse is controlled based on these edges. By the way, in this step STI, the area setting circuit 12 detects the peak value of the Y signal and sets a predetermined width in the vicinity of the peak value, for example, as shown in FIG. Generates gate pulse.

In step ST2, the control circuit 12 detects the detection circuit 10
Detect the (--10) edge of the signal from. (-10)
When an edge is not detected, the process proceeds to step ST3 by determining that the charge accumulation time TCMG is longer than the display light emission period 1/f□, and when a (-10) edge is detected, the process proceeds to step ST4.

In step ST3, the control circuit 21 performs step S
The period of the horizontal synchronization signal, that is, the IH waiting time is subtracted from the charge accumulation time TCHG set in TI, and the subtraction result is set as the new charge accumulation time TCHG, and step ST2
Return to That is, in the loop from step ST2 to step ST3, the control circuit 21 continues charge accumulation until the (--+) edge is detected, that is, until the charge accumulation time TCNG becomes shorter than the display light emission period 1/".3. Time TCM.

control is performed such that the difference between the charge accumulation time TCNG and the display light emission period 1/fosrO is within the IH time. Specifically, control is repeatedly performed to delay the phase of the charge accumulation start pulse by about the IH time.

In step ST4, the control circuit 21 adds the time for the CCD 1 to output a signal for one pixel (hereinafter referred to as 12 hours) to the charge accumulation time TCHG, sets this addition result as a new charge accumulation time TCNG, and steps ST
Proceed to step 5.

In step ST5, the ff1111 circuit 21 detects the (+--) edge of the signal from the detection circuit IO. (
(10--) When no edge is detected, charge accumulation time TC
It is determined that NG is shorter than the display light emission period 1/fosr, and the process returns to step ST4, and when the (10-) edge is detected, the process ends. That is, in the loop from step ST4 to step ST5, the control circuit 21
→−) Until the edge is detected, that is, the charge accumulation time T
Control is performed to increase the charge accumulation time TCNG by approximately IP time until CHG becomes longer than the display light emission period 1/fosr, and the difference between the charge accumulation time Tc, Ic and the display light emission period 1/fasPO becomes within the IP time. Control as follows. Specifically, control is repeatedly performed to advance the phase of the readout pulse by approximately 1P time.

Next, a specific example of controlling the charge accumulation time TCIIG of the CCD 1 will be described with reference to FIGS. 6 and 7.

Here, FIG. 6 shows the above-mentioned CCD 1 as an optical titl! consisting of, for example, a photodiode and a hole storage layer. It consists of a lead-out gate region, a horizontal and vertical shift register consisting of an n-type buried channel CCD, an output AMP section, etc. By controlling the potential of the n-substrate, unnecessary accumulated charges can be swept out to the n-substrate. The so-called vertical overflow drain (vertical OFD: Virtica
This is an interline transfer type solid-state imaging device having an overflow drain structure, and the timings of the n-substrate control potential (hereinafter referred to as shutter pulse), readout pulse, and charge accumulation time TCNG are shown.

The shutter pulse shown in Figure 6B corresponds to the charge accumulation start pulse described above, and is used during blanking of the horizontal synchronization signal so as not to affect the output video signal, that is, during blanking of the horizontal synchronization signal shown in Figure 6B. Generated in synchronization with the blanking pulse (negative pulse). The lead-out pulse shown in FIG. 6C is generated with a predetermined phase difference from the blanking pulse of the horizontal synchronization signal during the blanking pulse (negative pulse) of the vertical synchronization signal shown in FIG. 6A.

Then, by controlling these shutter pulses and readout pulses and supplying them to the CCD 1, the charge accumulation time TCM is determined. control. That is, as shown in FIG. 6, by supplying a shutter pulse until time t1 to sweep away the charges accumulated up to that point, and reading out the charges accumulated after time L1 with a readout pulse at time t2. Charge accumulation time Te at about IH time
Control ++c. Also, the blanking pulse B-, of the horizontal synchronizing signal shown in FIG. 7A, which is two steps before the lead-out pulse shown in FIG. 7B, is changed to 1/2H as shown in FIG. 7C.
Advance the time, delay the blanking pulse B1 after the lead-out pulse by 1/2H time, and set the blanking pulse B before the lead-out pulse to I as shown in FIG. 7C.
By controlling at the IP time within the H waiting time range, the time t2, that is, the generation timing of the lead-out pulse, is controlled at the IP time as shown in Figure 7.

Then, by controlling the shutter pulse and the readout pulse in this manner, the charge accumulation time TCIIG of the CCDI is controlled to be an integral multiple of the display light emission period 1/f++sr, for example, 1 time.

As described above, by controlling the charge accumulation time TCNG of the CCD 1 to an integer multiple of the display light emission period 1/fwsr, for example, 1 time, using the control circuit 21, horizontal stripe-like noise can be avoided on the imaging screen as in the conventional case. can be prevented from occurring.

In addition, the detection circuit 10 determines the charge accumulation time TcNG of CCDI.
The control circuit 21 detects the difference between the display light emission period 1/f+spO and the charge accumulation time Tc based on the detection result.
By controlling xc+, it is possible to automatically prevent horizontal stripe-like noise from occurring on the imaging screen.

In addition, by controlling the phase of the readout pulse at the IP time level, the charge accumulation time TCM can be adjusted. can be controlled to be smaller, and generation of horizontal stripe-like noise that cannot be prevented by controlling the IH time can also be prevented.

Note that the present invention is not limited to the above embodiments,
For example, the present invention can be easily applied to the case where a subject is photographed under an intermittent light source, and the occurrence of flicker can be prevented.

H0 Effects of the Invention As is clear from the above description, the solid-state imaging device according to the present invention includes a solid-state imaging device whose charge storage time can be varied and a control means for controlling the charge storage time of the solid-state imaging device. By controlling the charge accumulation time of the solid-state image sensor to an integral multiple of the intermittent period of the light beam from the subject using the control means,
It is possible to prevent horizontal stripe-like noise and flicker from occurring on the imaging screen.

Further, the detection means detects the intermittent frequency of the light beam from the subject based on the imaging output from the solid-state image sensor, and controls the charge accumulation time of the solid-state image sensor to an integral multiple of the intermittent cycle of the light beam based on this detection information. By doing so, it is possible to automatically prevent the occurrence of horizontal stripe-like noise and flicker on the imaging screen.

In addition, the charge accumulation time of the solid-state image sensor can be further reduced by controlling the charge discard period and the accumulated charge readout timing for discarding unnecessary accumulated charges by the control means based on the detection information from the detection means. (fine adjustment), thereby making it possible to more reliably prevent horizontal stripe-like noise from occurring.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a solid-state imaging device according to the present invention, and FIG. 2 is a block diagram showing a display screen when photographed by a solid-state imaging device with a field frequency lower than the synchronization frequency of the display. Light output and C
FIG. 3 is a waveform diagram showing the relationship between the charge accumulation time of the CD, FIG. 3 is a flowchart for explaining the operation of the solid-state imaging device, and FIG. 4 is a waveform diagram showing the relationship between the charge accumulation time of the CCD and the Y 5 is a waveform diagram showing the relationship between the signal and the comparison result from the detection circuit IO, and FIG. 5 is a waveform diagram showing the relationship between the Y signal and the comparison result from the detection circuit 10 when the charge accumulation time of the CCD is shorter than the display light emission period. 6 is a waveform diagram showing the timing of the CCD's input pulse, readout pulse, and charge accumulation time, and FIG. 7 is a waveform diagram for explaining the principle of phase control of the readout pulse. Yes, and Figure 8 is a diagram showing the display screen being photographed with a video camera.
FIG. 9 is a waveform diagram showing the relationship between the light emission output of the display and the output of the video camera. 1 ・ ・ 2 ・ ・ 10 ・ ・ 11, 1 12 ・ ・ l 3 ・ ・ 15 ・ ・ 16, 1 18 ・ ・ 19 ・ ・ 2 l ・ ・ 22 ・ ・ ・ CCD ・Signal processing circuit/detection circuit 4.20 ...Switch, area setting circuit, average value circuit, field switching circuit 7...Hold circuit, comparison circuit, inverting amplifier, control circuit, timing generation circuit

Claims (3)

[Claims] (1) A solid-state imaging device that receives intermittent light beams from a subject and photographs the subject using a synchronization signal with a frequency different from the intermittent frequency of the light beams, the solid-state image sensor having a variable charge accumulation time; , a control means for controlling the charge accumulation time of the solid-state image sensor, and the control means controls the charge accumulation time of the solid-state image sensor to be an integral multiple of the intermittent period of the light beam. Device. (2) It has a detection means for detecting the intermittent frequency of the light beam from the subject based on the imaging output from the solid-state image sensor, and the control means, based on the detection information from the detection means,
2. The solid-state imaging device according to claim 1, wherein the charge accumulation time of the solid-state imaging device is controlled to be an integral multiple of the intermittent period of the light beam. (3) The control means controls the charge accumulation period of the solid-state image sensor by controlling the charge sweep period for discarding unnecessary accumulated charges and the accumulated charge readout timing based on the detection information from the detection means. 3. The solid-state imaging device according to claim 2, wherein the solid-state imaging device is controlled with an accuracy of one period or less of a horizontal synchronization signal.