JPH04171977A - Substrate potential generation circuit - Google Patents

Substrate potential generation circuit

Info

Publication number
JPH04171977A
JPH04171977A JP2300112A JP30011290A JPH04171977A JP H04171977 A JPH04171977 A JP H04171977A JP 2300112 A JP2300112 A JP 2300112A JP 30011290 A JP30011290 A JP 30011290A JP H04171977 A JPH04171977 A JP H04171977A
Authority
JP
Japan
Prior art keywords
circuit
waveform
oscillation
reshaping
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2300112A
Other languages
Japanese (ja)
Inventor
Sumio Kuwabara
桑原 純夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP2300112A priority Critical patent/JPH04171977A/en
Publication of JPH04171977A publication Critical patent/JPH04171977A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To obtain a substrate potential generation circuit by means of which an oscillation frequency is oscillated stably and which has reduced a current consumption by providing the following: an oscillation circuit which can be changed over to a plurality of different oscillation frequencies; waveform-reshaping circuits installed at individual oscillation frequencies; and a charge pumping circuit which uses the output of the waveform-reshaping circuits as an input. CONSTITUTION:When a signal phi1 is at a high potential, an oscillation circuit 1 takes a higher oscillation frequency and a waveform-reshaping circuit 2 becomes inactive. As a result, sinusoidal waves as an output waveform of the oscillation circuit 1 are waveform-reshaped by a waveform-reshaping circuit 4 and are input to a charge-pumping circuit 3. When the signal phi1 is at a low potential, the oscillation circuit 1 takes a lower oscillation frequency and the waveform-reshaping circuit 4 becomes inactive. As a result, sinusoidal waves as the output waveform of the oscillation circuit 1 are waveform-reshaped by the waveform- reshaping circuit 2. At this time, since the waveform-reshaping circuit 2 is not required to operate with reference to the higher frequency and can be designed optimally with reference to the lower frequency, a current consumption can be reduced as compared with that of the waveform-reshaping circuit 2. The output of the charge-reshaping circuit 2 is input to the charge pumping circuit 3 in the same manner as a case where the potential of the signal phi1 is high.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は基板電位発生回路に関し、特に電流能力が切換
え可能な基板電位発生回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a substrate potential generation circuit, and more particularly to a substrate potential generation circuit whose current capability can be switched.

〔従来の技術〕[Conventional technology]

従来のこの種の基板電位発生回路は、MOSダイナミッ
ク・ランダム・アクセスメモリ (以下MO8DRAM
と称する)等において使用されているが、このMO8D
RAMのヒツト単価低下に伴なう使用分野の拡大により
、消費電流の低減が求められるようになってきた。
A conventional substrate potential generation circuit of this type is a MOS dynamic random access memory (hereinafter referred to as MO8DRAM).
), but this MO8D
With the decline in the unit price of RAM and the expansion of the fields of use, there has been a demand for lower current consumption.

以下に従来の回路例を示し説明する。An example of a conventional circuit will be shown and explained below.

第2図は、従来のMO8DRAMと同一の半導体基板上
に集積されている基板電位発生回路の一例を示す回路図
である。
FIG. 2 is a circuit diagram showing an example of a substrate potential generation circuit integrated on the same semiconductor substrate as a conventional MO8DRAM.

第2図において、本基板電位発生回路は、発振回路1と
、波形整形回路2と、チャージポンプ回路3とを有する
In FIG. 2, the substrate potential generation circuit includes an oscillation circuit 1, a waveform shaping circuit 2, and a charge pump circuit 3.

ここで発振回路1は、Pチャネル型トランジスタQ1〜
Q9.Q15と、Nチャネル型トランジスタQ16〜Q
25とを有する。波形整形回路2は、Pチャネル型トラ
ンジスタQIO,Qll。
Here, the oscillation circuit 1 includes P-channel transistors Q1 to
Q9. Q15 and N-channel transistors Q16 to Q
25. The waveform shaping circuit 2 includes P-channel transistors QIO and Qll.

Q12とNチャネル型トランジスタQ26.Q27゜Q
28とを有する。チャージポンプ回路3は、Pチャネル
型トランジスタQ13.Q14と、Nチャネル型トラン
ジスタQ29〜Q31とコンデンサC1とを有する。
Q12 and N-channel transistor Q26. Q27゜Q
28. Charge pump circuit 3 includes P-channel transistors Q13. Q14, N-channel transistors Q29 to Q31, and a capacitor C1.

第2図において、CMOSインバータ3段により構成さ
れた発振回路1は、信号φ1が高電位の時高い周波数で
発振し、信号φ1が低電位の時は低い周波数で発振する
様に構成されている。
In FIG. 2, an oscillation circuit 1 composed of three stages of CMOS inverters is configured to oscillate at a high frequency when the signal φ1 is at a high potential, and to oscillate at a low frequency when the signal φ1 is at a low potential. .

CMOSインバータにより構成された波形整形回路2は
、発振回路1の出力である正弦波を方形波に変換する機
能を有している。
A waveform shaping circuit 2 configured with a CMOS inverter has a function of converting a sine wave output from the oscillation circuit 1 into a square wave.

チャージポンプ回路3は、波形整形回路2で得られた方
形波を入力として接地電位以下の電位を発生する機能を
有する。
The charge pump circuit 3 has a function of receiving the square wave obtained by the waveform shaping circuit 2 as input and generating a potential below the ground potential.

第2図において、信号φ1は同一基板上に集積されてい
るMO8DRAMにより制御され、基板電位を急速に低
下させる必要のある時、もしくは多量の基板電流が流れ
る場合には、信号φ1は高電位となり、発振回路lの発
振周波数が高速になり、基板から電荷をくみだす能力は
増大するが、それに伴い消費電流も増加する。
In FIG. 2, the signal φ1 is controlled by the MO8DRAM integrated on the same substrate, and when it is necessary to rapidly lower the substrate potential or when a large amount of substrate current flows, the signal φ1 becomes a high potential. , the oscillation frequency of the oscillation circuit I becomes faster, and the ability to pump out charges from the substrate increases, but current consumption also increases accordingly.

一方、MO8DRAMが非活性状態であり、基板電位が
必要十分な電位である場合には、信号φ1は低電位とな
り、発振回路1の発振周波数が低速となり、基板から電
荷をくみだす能力は低下し、また消費電流も低減される
On the other hand, when the MO8DRAM is in an inactive state and the substrate potential is at a necessary and sufficient potential, the signal φ1 becomes a low potential, the oscillation frequency of the oscillation circuit 1 becomes low, and the ability to extract charges from the substrate decreases. , current consumption is also reduced.

=発明が解決しようとする課題〕 以上説明した様に、従来の基板電位発生回路は、同一基
板上に集積されているMO8DRAMの動作状態に応じ
て基板から電荷をくみ出す能力が変化し、またそれに伴
なって消費電流も変化する為、不要な電流消費を低減す
る効果があるが、第2図に示す波形整形回路2は、複数
の相異なる周波数について共に最適となる設計ができな
い。このため、特に発振回路1が低速の発振周波数時に
不要な消費電流が流れるという問題点があった。これは
、波形整形回路2を構成するCMOSインバータに入力
として正弦波が印加される為、電源電位から接地電位に
向けて貫通電流が流れることによるものであり、CMO
Sインバータの能力を小さくすることにより貫通電流を
低減可能であるが、それによって高い発振周波数時に動
作しなくなるという問題が生じる。
=Problem to be Solved by the Invention] As explained above, in the conventional substrate potential generation circuit, the ability to pump out charges from the substrate changes depending on the operating state of the MO8DRAM integrated on the same substrate, and Since the current consumption changes accordingly, there is an effect of reducing unnecessary current consumption, but the waveform shaping circuit 2 shown in FIG. 2 cannot be designed to be optimal for a plurality of different frequencies. Therefore, there is a problem in that unnecessary current consumption flows particularly when the oscillation circuit 1 has a low oscillation frequency. This is because a sine wave is applied as an input to the CMOS inverter that constitutes the waveform shaping circuit 2, so a through current flows from the power supply potential to the ground potential.
Although it is possible to reduce the through current by reducing the capacity of the S inverter, this causes the problem that it does not operate at high oscillation frequencies.

本発明の目的は、前記欠点を解決し、発振周波数が安定
に発振し、かつ消費電流を低減化した基板電位発生回路
を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a substrate potential generation circuit that solves the above-mentioned drawbacks, has a stable oscillation frequency, and reduces current consumption.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の基板電位発生回路の構成は、複数の発振周波数
に切換えられる発振回路と、前記発振周波数毎にそれぞ
れもうけられた波形整形回路と、チャージポンプ回路と
を備えたことを特徴とする。
The structure of the substrate potential generation circuit of the present invention is characterized by comprising an oscillation circuit that can be switched to a plurality of oscillation frequencies, a waveform shaping circuit provided for each of the oscillation frequencies, and a charge pump circuit.

〔実施例〕〔Example〕

次に図面を参照しながら本発明を説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の基板電位発生回路を示す回
路図である。
FIG. 1 is a circuit diagram showing a substrate potential generation circuit according to an embodiment of the present invention.

第1図において、本実施例は発振回路1と、波形整形回
路2,4と、チャージポンプ回路3とを含み、構成され
る。
In FIG. 1, this embodiment includes an oscillation circuit 1, waveform shaping circuits 2 and 4, and a charge pump circuit 3.

ここで、発振回路2は、Pチャネル型トランジスタQ1
〜QIOと、Nチャネル型トランジスタQ24〜Q33
とを有する。
Here, the oscillation circuit 2 includes a P-channel transistor Q1
~QIO and N-channel transistors Q24 to Q33
and has.

波形整形回路2は、Pチャネル型トランジスタQll〜
Q16と、Nチャネル型トランジスタQ34〜Q39と
を有する。
The waveform shaping circuit 2 includes P-channel transistors Qll~
Q16, and N-channel transistors Q34 to Q39.

その下の波形整形回路4は、Pチャネル型トランジスタ
Q17〜Q20と、Nチャネル型トランジスタQ40〜
Q43とを有する。
The waveform shaping circuit 4 below it includes P-channel transistors Q17 to Q20 and N-channel transistors Q40 to Q20.
Q43.

チャージポンプ回路3は、Pチャネル型トランジスタQ
21〜Q23と、Nチャネル型トランジスタQ44〜Q
47とを有する。
The charge pump circuit 3 includes a P-channel transistor Q
21 to Q23 and N-channel transistors Q44 to Q
47.

発振回路1は、第2図の発振回路と同様であり、信号φ
1が高電位のとき高い発振周波数を、信号φ1が低電位
のとき低い発振周波数をもつ発振回路である。
The oscillation circuit 1 is similar to the oscillation circuit shown in FIG.
This is an oscillation circuit that has a high oscillation frequency when the signal φ1 is at a high potential, and a low oscillation frequency when the signal φ1 is at a low potential.

波形整形回路2は、信号φ1が低電位のとき活性化し、
信号φ1が高電位のとき非活性化し、発振回路1がもつ
低い方の発振周波数の波形整形に対し、消費電流が低く
なる様に設計さ九ている。
The waveform shaping circuit 2 is activated when the signal φ1 is at a low potential,
It is inactivated when the signal φ1 is at a high potential, and is designed to reduce current consumption for waveform shaping of the lower oscillation frequency of the oscillation circuit 1.

チャージポンプ回路3は、第1図と同様のチャージポン
プ回路である。
The charge pump circuit 3 is a charge pump circuit similar to that shown in FIG.

波形整形回路4は、信号φ1が高電位のとき活性化し、
低電位のとき非活性化し、発振回路1がもつ高い方の発
振周波数の波形整形に対し、消費電流が低くなる様に設
計されている。
The waveform shaping circuit 4 is activated when the signal φ1 is at a high potential,
It is inactivated when the potential is low, and is designed to reduce current consumption for waveform shaping of the higher oscillation frequency of the oscillation circuit 1.

次に第1図の動作を説明する。信号φ1が高電位である
と、発振回路lは高い方の発振周波数をとり、波形整形
回路2は非活性となる為、発振回路lの出力波形である
正弦波は波形整形回路4により波形整形され、チャージ
ポンプ回路3に入力される。
Next, the operation shown in FIG. 1 will be explained. When the signal φ1 is at a high potential, the oscillation circuit l takes on a higher oscillation frequency and the waveform shaping circuit 2 becomes inactive, so the sine wave that is the output waveform of the oscillation circuit l is shaped by the waveform shaping circuit 4. and is input to the charge pump circuit 3.

信号φ1が低電位であると、発振回路1は低い方の発振
周波数をとり、波形整形回路4は非活性となる為、発振
回路1の出力波形である正弦波は波形整形回路2により
波形整形される。
When the signal φ1 is at a low potential, the oscillation circuit 1 takes on the lower oscillation frequency and the waveform shaping circuit 4 becomes inactive, so the sine wave that is the output waveform of the oscillation circuit 1 is shaped by the waveform shaping circuit 2. be done.

この時、波形整形回路2は、高い方の周波数に対しては
動作させる必要がない為と、低い方の周波数について最
適設計を行なうことができるので、第1図に示す波形整
形回路2よりも消費電流を低減することが可能となる。
At this time, the waveform shaping circuit 2 is better than the waveform shaping circuit 2 shown in FIG. 1 because it does not need to operate for higher frequencies and can be optimally designed for lower frequencies. It becomes possible to reduce current consumption.

波形整形回路2の出力は、信号φ1が高電位の場合と同
様に、チャージポンプ回路3に入力される。
The output of the waveform shaping circuit 2 is input to the charge pump circuit 3 in the same way as when the signal φ1 is at a high potential.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明による基板電位発生回路は
、複数の相異なる発振周波数に対し、各々専用の波形整
形回路をもうけることにより、波形整形回路を構成する
特にCMOSインノ・−タの貫通電流を必要最小限に低
減することが可能となり、消費電流か低減するという効
果を有する。
As explained above, the substrate potential generation circuit according to the present invention has a dedicated waveform shaping circuit for each of a plurality of different oscillation frequencies. This makes it possible to reduce the current consumption to the necessary minimum, which has the effect of reducing current consumption.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の基板電位発生回路の回路図
、第2図は従来の基板電位発生回路の回路図である。 1・・・・・・発振回路、2,4・・・・・・波形整形
回路、3・・・・・チャージポンプ回路、C1・・・・
・・コンテンサ。 代理人 弁理士  内 原   音
FIG. 1 is a circuit diagram of a substrate potential generation circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional substrate potential generation circuit. 1... Oscillation circuit, 2, 4... Waveform shaping circuit, 3... Charge pump circuit, C1...
... Contensa. Agent Patent Attorney Oto Uchihara

Claims (1)

【特許請求の範囲】[Claims]  複数の相異なる発振周波数に切換えられる発振回路と
、前記発振周波数毎にもうけられた波形整形回路と、こ
れら波形整形回路の出力を入力とするチャージポンプ回
路とを備えたことを特徴とする基板電位発生回路。
A substrate potential characterized by comprising an oscillation circuit that can be switched to a plurality of different oscillation frequencies, a waveform shaping circuit provided for each of the oscillation frequencies, and a charge pump circuit whose input is the output of these waveform shaping circuits. generation circuit.
JP2300112A 1990-11-06 1990-11-06 Substrate potential generation circuit Pending JPH04171977A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2300112A JPH04171977A (en) 1990-11-06 1990-11-06 Substrate potential generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2300112A JPH04171977A (en) 1990-11-06 1990-11-06 Substrate potential generation circuit

Publications (1)

Publication Number Publication Date
JPH04171977A true JPH04171977A (en) 1992-06-19

Family

ID=17880868

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2300112A Pending JPH04171977A (en) 1990-11-06 1990-11-06 Substrate potential generation circuit

Country Status (1)

Country Link
JP (1) JPH04171977A (en)

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE ISSCC=1985 *

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