JPH04171858A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04171858A
JPH04171858A JP2299422A JP29942290A JPH04171858A JP H04171858 A JPH04171858 A JP H04171858A JP 2299422 A JP2299422 A JP 2299422A JP 29942290 A JP29942290 A JP 29942290A JP H04171858 A JPH04171858 A JP H04171858A
Authority
JP
Japan
Prior art keywords
lead
semiconductor device
resin
time
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2299422A
Other languages
Japanese (ja)
Inventor
Shuichi Yamaura
山浦　修一
Takeshi Kizaki
木崎　健
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Ltd
Hitachi Tohbu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Tohbu Semiconductor Ltd filed Critical Hitachi Ltd
Priority to JP2299422A priority Critical patent/JPH04171858A/en
Publication of JPH04171858A publication Critical patent/JPH04171858A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce defective products of a semiconductor device with an outer lead provided at the outside of a sealing material by a method wherein the outer lead is constituted of a shape memory alloy. CONSTITUTION:An outer lead 3B of a resin-sealed semiconductor device with the outer lead 3B provided at the outside of a resin 1A is molded of a shape memory alloy in a J type. A heat treatment at a comparatively low temperature is performed on this lead 3B at the time of the molding and the form of the J type is made to memorize in the lead 3B. Accordingly, in the case the lead 3B is deformed by an external force at the time of the handling work, such as the time of mounting, the time of transfer, the time of storage or the like, of the device, the deformed lead 3B can be corrected into the form of the J type made to memorize previously by a heat treatment in a solder reflow method at the time of mounting of the device on the mounting surface of a mounting board, for example. Moreover, in the case this device is mounted on the mounting surface of the mounting board, the failure of the connection between wiring on the above mounting board and the lead 3B, which is caused by a loosening and a bent of the lead or the like due to the deformation of the lead 3B, can also be prevented from being generated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に関し、特に、半導体装置の製品
不良を低減できる技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a technique that can reduce product defects in semiconductor devices.

〔従来の技術〕[Conventional technology]

半導体チップを保護するために、半導体チップを樹脂パ
ッケージで封止する樹脂封止型半導体装置として１例え
ばＳ　ＯＪ　（Ｓｍａｌｌ　０ｕｔ−１ｉｎｅ　Ｊ−ｂ
ｅｎｄ）型がある。In order to protect the semiconductor chip, there is a resin-sealed semiconductor device that seals the semiconductor chip in a resin package.
end) type.

前記ＳＯＪ型の樹脂封止型半導体装置は、リードフレー
ムに一体に形成されたタブの主面上に接着層を介在して
半導体チップを搭載している。こ、の半導体チップの外
部端子（ポンディングパッド）は、ボンディングワイヤ
を介してアウターリードに一体に形成されたインナーリ
ードと電気的に接続されている。これらの半導体チップ
、インナーリード、ボンディングワイヤ等は樹脂パッケ
ージで気密封止される。前記樹脂封止型半導体装置のア
ウターリードは、樹脂封止後に、一体に形成された前記
リードフレームから切断され、Ｊ型の形状に成型される
。The SOJ type resin-sealed semiconductor device has a semiconductor chip mounted on the main surface of a tab integrally formed with a lead frame with an adhesive layer interposed therebetween. The external terminals (bonding pads) of this semiconductor chip are electrically connected to inner leads integrally formed with the outer leads via bonding wires. These semiconductor chips, inner leads, bonding wires, etc. are hermetically sealed in a resin package. After resin sealing, the outer leads of the resin-sealed semiconductor device are cut from the integrally formed lead frame and molded into a J-shape.

前記リードフレームは、前記インナーリード、アウター
リード及びタブ等で構成され、一体に形成されている。The lead frame is composed of the inner lead, outer lead, tab, etc., and is integrally formed.

このリードフレームは１例えばＦｅ−Ｎ１（例えばＮｉ
含有率４２又は５０［％］）合金、Ｃｕ系合金等で形成
される。This lead frame is made of 1, e.g. Fe-N1 (e.g. Ni
It is formed of an alloy with a content of 42 or 50%, a Cu-based alloy, or the like.

前記ボンディングワイヤは例えばアルミニウム（Ａｌ）
ワイヤを使用する。また、ボンディングワイヤは、金（
Ａｕ）ワイヤ、銅（Ｃｕ）ワイヤ、金属ワイヤの表面に
絶縁性の樹脂を被覆した被覆−ワイヤ等が使用される。The bonding wire is made of aluminum (Al), for example.
Use wire. In addition, the bonding wire is made of gold (
Examples of the wires used include coated wires such as Au) wires, copper (Cu) wires, and coated wires in which the surface of metal wires is coated with an insulating resin.

ボンディングワイヤの一方は、前述のように、半導体チ
ップの素子形成面に形成された外部端子に接続される。As described above, one end of the bonding wire is connected to an external terminal formed on the element forming surface of the semiconductor chip.

また、ボンディングワイヤの他方は、前記インナーリー
ドのボンディング面に金属メツキ層を介在して接続され
る。Further, the other bonding wire is connected to the bonding surface of the inner lead with a metal plating layer interposed therebetween.

この金属メツキ層は２例えば銀をメツキ処理して形成し
、インナーリードとボンディングワイヤとのボンダビリ
ティを高めている。ボンディングワイヤは１例えば熱圧
着に超音波振動を併用したボンディング法によりボンデ
ィングされる。This metal plating layer is formed by plating, for example, silver to improve bondability between the inner lead and the bonding wire. The bonding wire is bonded by, for example, a bonding method that uses thermocompression bonding in combination with ultrasonic vibration.

このように構成された樹脂封止型半導体装置は、例えば
メモリボード、ＣＰＵボード等の実装基板の実装面上に
複数個搭載される。A plurality of resin-sealed semiconductor devices configured in this manner are mounted on a mounting surface of a mounting board such as a memory board, a CPU board, or the like.

なお、この種の樹脂封止型半導体装置については、例え
ば、日経マイクロデバイス、１９８８年、５月号、第３
６頁乃至第４０頁に記載されている。Regarding this type of resin-sealed semiconductor device, see, for example, Nikkei Microdevice, May 1988, No. 3.
It is described on pages 6 to 40.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

前記樹脂封止型半導体装置のアウターリートは、実装基
板に実装する時、搬送する時、保管する時等の取り扱い
時に所定の形状に成型した形状が外力で変形し、製品不
良（不良品）を生じる問題があった。この製品不良とな
った樹脂封止型半導体装置を実装基板に実装すると、こ
の樹脂封止型半導体装置のアウターリードの変形による
リードの浮き１曲がり等により、実装基板の配線との間
に接続不良が生じる。The outer lead of the resin-sealed semiconductor device is molded into a predetermined shape during handling such as mounting on a mounting board, transporting, and storing, and may be deformed by external force, resulting in product defects (defective products). There were problems that arose. When this defective resin-sealed semiconductor device is mounted on a mounting board, the outer leads of this resin-sealed semiconductor device may be deformed and the leads may be lifted or bent, causing a connection failure between the wiring and the wiring on the mounting board. occurs.

また、前記樹脂封止型半導体装置は、半導体チップの外
部端子とインナーリードとをボンディングワイヤで接続
するボンディング時又はボンディング終了後の搬送時等
にボンディングワイヤが変形し、隣接するボンディング
ワイヤ同志のショート又は半導体チップのエリアとボン
ディングワイヤとのショートが発生し、製品不良（不良
品）を生じる問題があった。In addition, in the resin-sealed semiconductor device, the bonding wire is deformed during bonding to connect the external terminal and the inner lead of the semiconductor chip with the bonding wire, or during transportation after the bonding is completed, resulting in short-circuits between adjacent bonding wires. Alternatively, there is a problem in that a short circuit occurs between the semiconductor chip area and the bonding wire, resulting in product defects (defective products).

本発明の目的は、封止体の外部にアウターリードが設け
られた半導体装置の製品不良（不良品）を低減すること
が可能な技術を提供することにある。An object of the present invention is to provide a technique that can reduce product defects (defective products) of a semiconductor device in which an outer lead is provided outside a sealed body.

本発明の他の目的は、半導体チップの外部端子とリード
とをボンディングワイヤで電気的に接続する半導体装置
の製品不良（不良品）を低減することが可能な技術を提
供することにある。Another object of the present invention is to provide a technique capable of reducing product defects (defective products) of a semiconductor device in which external terminals and leads of a semiconductor chip are electrically connected with bonding wires.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

〔課題を解決するための手段〕[Means to solve the problem]

本願において開示される発明のうち１代表的なものの概
要を簡単に説明すれば、下記のとおりである。A brief overview of one typical invention disclosed in this application is as follows.

（１）封止体の外部にアウターリードが設けられた半導
体装置において、前記アウターリードを形状記憶合金で
構成する。(1) In a semiconductor device in which an outer lead is provided outside a sealed body, the outer lead is made of a shape memory alloy.

（２）半導体チップの外部端子とリードとをボンディン
グワイヤで電気的に接続し、これらを封止体で封止する
半導体装置において、前記ボンディングワイヤを形状記
憶合金で構成する。(2) In a semiconductor device in which external terminals and leads of a semiconductor chip are electrically connected with bonding wires and these are sealed with a sealing body, the bonding wires are made of a shape memory alloy.

〔作　　用〕[For production]

上述した手段（１）によれば５半導体装置を実装基板に
実装する時、半導体装置を搬送する時、半導体装置を保
管する時等の半導体装置の取り扱い作業時に変形した（
曲がった）アウターリードの形状を予め記憶させた形状
に修正（復帰）することができるので、半導体装置の製
品不良（不良品率）を低減できる。According to the above-mentioned means (1), deformation occurs during handling work of the semiconductor device, such as when mounting the semiconductor device on a mounting board, transporting the semiconductor device, and storing the semiconductor device.
Since the shape of the bent outer lead can be corrected (restored) to a previously memorized shape, product defects (defective product rate) of semiconductor devices can be reduced.

上述した手段（２）によ九ば、ボンディング時、ボンデ
ィング終了後の搬送時等で変形したボンディングワイヤ
を予め記憶させた形状に修正（復帰）することができる
ので、隣接するボンディングワイヤ同志のショート又は
半導体チップのエリアとボンディングワイヤとのショー
トを防止することができ、半導体装置の製品不良（不良
品率）を低減できる。According to the above-mentioned means (2), it is possible to correct (return) the bonding wire that has been deformed during bonding or during transportation after bonding to a pre-memorized shape, thereby preventing short-circuits between adjacent bonding wires. Alternatively, short circuits between the semiconductor chip area and the bonding wire can be prevented, and product defects (defective product rate) of semiconductor devices can be reduced.

以下、本発明の構成について、ＳＯＪ型の樹脂封止型半
導体装置に本発明を適用した一実施例とともに説明する
。Hereinafter, the structure of the present invention will be described together with an embodiment in which the present invention is applied to an SOJ type resin-sealed semiconductor device.

なお、実施例を説明するための全図において。In addition, in all the figures for explaining an example.

同一機能を有するものは同一符号を付け、その繰り返し
の説明は省略する。Components having the same function are given the same reference numerals, and repeated explanations thereof will be omitted.

〔発明の実施例〕[Embodiments of the invention]

本発明の一実施例である樹脂封止型半導体装置の概略構
成を第２図（断面図）に示す。A schematic configuration of a resin-sealed semiconductor device according to an embodiment of the present invention is shown in FIG. 2 (cross-sectional view).

第２図に示すように、樹脂封止型半導体装置はＳ　ＯＪ
　（Ｓｍａｌｌ　０ｕｔ−１ｉｎｅ　Ｊ−ｂｅｎｄ）型
のパッケージ１で構成されている。この樹脂封止型半導
体装置はタブ３Ｃの主面上に接着層４を介在して半導体
チップ２を搭載している。As shown in FIG. 2, the resin-sealed semiconductor device is an S OJ
(Small 0 out-1ine J-bend) type package 1. This resin-sealed semiconductor device has a semiconductor chip 2 mounted on the main surface of a tab 3C with an adhesive layer 4 interposed therebetween.

前記半導体チップ２は、図示していないが、平面が方形
状の例えば単結晶珪素基板で構成されている。この半導
体チップ２の主面（素子形成面）上には、方形状の各辺
に沿った最外肩部分に複数の外部端子（ポンディングパ
ッド）２Ｐが配置されている。この外部端子２Ｐは半導
体チップ２の主面に形成された半導体素子と電気的に接
続されている。Although not shown, the semiconductor chip 2 is made of, for example, a single-crystal silicon substrate having a rectangular plane. On the main surface (element forming surface) of this semiconductor chip 2, a plurality of external terminals (ponding pads) 2P are arranged at the outermost shoulder portions along each side of the rectangular shape. This external terminal 2P is electrically connected to a semiconductor element formed on the main surface of the semiconductor chip 2.

前記外部端子２Ｐは、ボンディングワイヤ５を介してイ
ンナーリード３Ａと電気的に接続されている。このボン
ディングワイヤ５は、例えば熱圧着に超音波振動を併用
したボンディング法によりボンディングされる。The external terminal 2P is electrically connected to the inner lead 3A via the bonding wire 5. This bonding wire 5 is bonded, for example, by a bonding method that uses thermocompression bonding in combination with ultrasonic vibration.

前記半導体チップ２は、接着層４を介在してタブ３Ｃ上
に接着固定されている。接着層４としては、例えばＡｇ
ペースト、Ａｕ−５ｉ共晶合金等が使用される。The semiconductor chip 2 is adhesively fixed onto the tab 3C with an adhesive layer 4 interposed therebetween. As the adhesive layer 4, for example, Ag
Paste, Au-5i eutectic alloy, etc. are used.

前記半導体チップ２、インナーリード３Ａ、タブ３Ｃ及
びボンディングワイヤ５等は、低応力化を図るために例
えばフェノール系硬化剤、シリコーンゴム及びフィラー
が添加された絶縁性のエポキシ系樹脂ＩＡ（封止体）で
封止されている。The semiconductor chip 2, inner leads 3A, tabs 3C, bonding wires 5, etc. are made of an insulating epoxy resin IA (sealing body) to which a phenolic curing agent, silicone rubber, and filler are added to reduce stress. ) is sealed.

前記インナーリード３Ａはアウターリード３Ｂと一体に
形成されている。このアウターリード３Ｂは、前述のよ
うに、半導体チップ２、インナーリード３Ａ、タブ３Ｃ
及びボンディングワイヤ５等をトランスファモールド法
に基づいて樹脂ＩＡで封止した後、リードフレーム（図
示せず）から切断され、Ｊ型の形状に成型される。The inner lead 3A is formed integrally with the outer lead 3B. As described above, this outer lead 3B includes the semiconductor chip 2, the inner lead 3A, and the tab 3C.
After sealing the bonding wire 5 and the like with resin IA based on a transfer molding method, it is cut from a lead frame (not shown) and molded into a J-shape.

前記インナーリード３Ａ及びアウターリード３Ｂを含む
切断前のリードフレームは、例えばニッケルーチタン（
Ｎｉ−Ｔｉ）合金で形成されている。The lead frame including the inner leads 3A and outer leads 3B before cutting is made of, for example, nickel-titanium (
It is made of a Ni-Ti alloy.

このＮｉ−Ｔｉ合金は、約１００℃程度に加熱すること
により、予め記憶させた形状に復帰できる形状記憶合金
である。この形状記憶合金で形成されたリードフレーム
のうち、少なくともインナーリード３Ａ及びアウターリ
ード３Ｂの表面上の全面には、第１図（第２図の要部拡
大断面図）に示すように１例えばＮｉで形成された金属
メツキ層６を介在させて半田メツキ層７が被覆されてい
る。This Ni-Ti alloy is a shape memory alloy that can return to a pre-memorized shape by heating to about 100°C. Of the lead frame formed of this shape memory alloy, at least the inner leads 3A and the outer leads 3B are coated with 1, for example, Ni, as shown in FIG. A solder plating layer 7 is coated with a metal plating layer 6 interposed therebetween.

つまり、インナーリード３Ａ及びアウターリード３Ｂは
金属層の３層構造で構成されている。前記金属メツキ層
６は形状記憶合金と半田メツキ層７とのボンダビリティ
を高める目的で形成されている。前記メツキ層７は、メ
モリボード、ＣＰＵボード等の実装基板の実装面に実装
する際に接合金属として使用される。In other words, the inner lead 3A and the outer lead 3B have a three-layer structure of metal layers. The metal plating layer 6 is formed for the purpose of improving the bondability between the shape memory alloy and the solder plating layer 7. The plating layer 7 is used as a bonding metal when mounting on the mounting surface of a mounting board such as a memory board or a CPU board.

前記タブ３Ｃは、前述のインナーリード３Ａ及びアウタ
ーリード３Ｃと同様にＮｉ−Ｔｉ合金で形成され、この
Ｎｉ−Ｔｉ合金の表面上の全面には、金属メツキ層６を
介在して半田メツキ層７が被覆されている。つまり、イ
ンナーリード３Ａ。The tab 3C is formed of a Ni-Ti alloy like the inner lead 3A and the outer lead 3C described above, and a solder plating layer 7 is formed on the entire surface of the Ni-Ti alloy with a metal plating layer 6 interposed therebetween. is covered. In other words, inner lead 3A.

アウターリード３Ｂ、タブ３Ｃの夫々は、Ｎｉ　−Ｔｉ
合金で形成されたリードフレームの表面上の全面に例え
ばＮｉを形成して金属メツキ層６を形成し、この金属メ
ツキ層６の表面上の全面に半田を形成して半田メツキ層
７を形成することにより構成される。なお１本実施例で
は、インナーリード３Ａ、アウターリード３Ｂ、タブ３
Ｃの夫々の表面上の全面に金属メツキ層６を介在して半
田メツキ層７を被覆しているが、マスクを使用してイン
ナーリード３Ａ及びアウターリード３Ｂ、又はアウター
リード３Ｂのみに前記金属メツキ層６及び半田メツキ層
７を形成してもよい。Each of the outer lead 3B and tab 3C is made of Ni-Ti.
For example, Ni is formed on the entire surface of a lead frame made of an alloy to form a metal plating layer 6, and solder is formed on the entire surface of this metal plating layer 6 to form a solder plating layer 7. It consists of: Note that in this embodiment, the inner lead 3A, the outer lead 3B, and the tab 3
A solder plating layer 7 is coated on the entire surface of each of the inner leads 3A and outer leads 3B, or only the outer leads 3B using a mask. A layer 6 and a solder plating layer 7 may also be formed.

前記樹脂封止型半導体装置のアウターリード３Ｂは、同
第２図に示すように、Ｊ型の形状に成型されている。こ
のアウターリード３Ｂは、成型時（例えばプレス加工時
）に約り５０℃〜２００℃程度の比較的低温度の熱処理
を約３０程度度施して、Ｊ型の形状を記憶させている。The outer lead 3B of the resin-sealed semiconductor device is formed into a J-shape, as shown in FIG. This outer lead 3B is subjected to heat treatment at a relatively low temperature of about 50° C. to 200° C. about 30 times during molding (for example, press working) to memorize the J-shaped shape.

このように構成された樹脂封止型半導体装置のアウター
リード３Ｂは、この樹脂封止型半導体装置の実装時、搬
送時、保管時等の取り扱い作業時に外力で変形した場合
、例えば樹脂封止型半導体装置を実装基板の実装面に実
装する時の半田リフローの熱処理（約２００℃前後）で
、予め記憶させたＪ型の形状に修正（復帰）することが
できる。If the outer leads 3B of the resin-sealed semiconductor device configured in this way are deformed by external force during handling operations such as mounting, transportation, and storage of the resin-sealed semiconductor device, for example, the resin-sealed semiconductor device When the semiconductor device is mounted on the mounting surface of the mounting board, the solder reflow heat treatment (approximately 200° C.) allows the semiconductor device to be corrected (restored) to the pre-memorized J-shaped shape.

前記インナーリード３Ａのボンディング面の半田メツキ
層７上にはメツキ層８が形成されている。A plating layer 8 is formed on the solder plating layer 7 on the bonding surface of the inner lead 3A.

このメツキ層８は、ボンディングワイヤ５とのボンダビ
リティを高めるために例えば銀（Ａｇ）又は金（Ａｕ）
で形成されている。ボンディングワイヤ５は、前述のリ
ードフレームと同様に例えばＮｉ−Ｔｉ合金で形成され
、約１００℃程度に加熱処理を施すことにより、予め記
憶させた形状に復帰できる形状記憶合金で構成されてい
る。このボンディングワイヤ５の表面は、第１図に示す
ように、例えば電気伝導率を高め、かつボンダビリティ
を高める目的で、Ａｕで形成された金属メツキ層５ａで
被覆されている。This plating layer 8 is made of, for example, silver (Ag) or gold (Au) to improve bondability with the bonding wire 5.
It is formed of. The bonding wire 5 is made of a Ni-Ti alloy, for example, like the lead frame described above, and is made of a shape memory alloy that can return to a pre-memorized shape by heat treatment at about 100°C. As shown in FIG. 1, the surface of the bonding wire 5 is coated with a metal plating layer 5a made of Au, for example, for the purpose of increasing electrical conductivity and bondability.

前記ボンディングワイヤ５は、第１図及び第２図に示す
ように、半導体チップ２とインナーリード３Ａとを電気
的に接続した時のループ形状と同等又はその形状に近い
形状の例えば円柱棒に、金属メツキ層５ａで被覆された
Ｎ　ｉ　−Ｔ　ｉ合金ワイヤを巻き付け、熱処理（約１
５０”Ｃ〜２００”Ｃ程度の温度で約３０分）を施して
予めループ形状を記憶させておく、このループ形状を記
憶させたボンディングワイヤ５はボンディング装置のリ
ール（スプール）に巻き取られる。このように構成され
た樹脂封止型半導体装置のボンディングワイヤ５は、前
記樹脂ＩＡでインナーリード３Ａ、半導体チップ２．ポ
ンデイグワイヤ５等をモールド封止する前に、例えば約
２００℃前後の熱処理を施すことにより、ボンディング
時又はボンディング終了後の搬送時等で発生したループ
形状の外力による変形を予め記憶させたループ形状に修
正（復帰）することができる。As shown in FIGS. 1 and 2, the bonding wire 5 is, for example, a cylindrical rod having a shape similar to or similar to the loop shape when the semiconductor chip 2 and the inner lead 3A are electrically connected. A Ni-Ti alloy wire coated with a metal plating layer 5a is wound and heat-treated (approximately 1
The bonding wire 5 with the loop shape memorized is wound onto a reel (spool) of a bonding device. The bonding wire 5 of the resin-sealed semiconductor device configured as described above is made of the resin IA and is connected to the inner lead 3A, the semiconductor chip 2. Before molding and sealing the bonding wire 5, etc., a loop is formed in which the deformation of the loop shape due to an external force that occurs during bonding or during transportation after bonding is memorized by applying heat treatment to, for example, around 200°C. The shape can be corrected (restored).

このように、樹脂（封止体）ＩＡの外部にアウターリー
ド３Ｂが設けられた樹脂封止型半導体装置において、前
記アウターリード３Ｂを形状記憶合金で構成する。この
構成により、樹脂封止型半導体装置を実装基板に実装す
る時、搬送する時、保管する時等の樹脂封止型半導体装
置の取り扱い時に外力で変形したアウターリード３Ｂの
形状を予め記憶させた形状に修正（復帰）することがで
きるので、樹脂封止型半導体装置の製品不良（不良品率
）を低減できる。また、この樹脂封止型半導体装置を実
装基板の実装面上に実装する場合、アウターリード３Ｂ
の変形によりリードの浮き、曲がり等で生ずる前記実装
基板の配線とアウターリード３Ｂとの接続不良を防止で
きる。In this manner, in the resin-sealed semiconductor device in which the outer leads 3B are provided outside the resin (sealed body) IA, the outer leads 3B are made of a shape memory alloy. With this configuration, the shape of the outer lead 3B that is deformed by external force during handling of the resin-sealed semiconductor device such as when mounting the resin-sealed semiconductor device on a mounting board, transporting, and storing is memorized in advance. Since the shape can be corrected (restored), product defects (defective product rate) of resin-sealed semiconductor devices can be reduced. In addition, when mounting this resin-sealed semiconductor device on the mounting surface of a mounting board, the outer lead 3B
Due to this deformation, it is possible to prevent poor connection between the wiring of the mounting board and the outer lead 3B caused by floating or bending of the lead.

また、半導体チップ２の外部端子２Ｐとインナーリード
３Ａ（リード）とをボンディングワイヤ５で電気的に接
続し、これらを樹脂（封止体）ＩＡで封止する樹脂封止
型半導体装置において、前記ボンディングワイヤ５を形
状記憶合金で構成する。Further, in the resin-sealed semiconductor device in which the external terminals 2P of the semiconductor chip 2 and the inner leads 3A (leads) are electrically connected with the bonding wires 5, and these are sealed with the resin (sealing body) IA, the above-mentioned The bonding wire 5 is made of a shape memory alloy.

この構成により、ボンディング時、ボンディング終了後
の搬送時等で変形したボンディングワイヤ５を予め記憶
させた形状に修正（復帰）することができるので、隣接
するボンデインワイヤ５同志のショート又は半導体チッ
プ２のエリアとボンデインワイヤ５とのショートを防止
することができ、樹脂封止型半導体装置の製品不良（不
良品率）を低減できる。With this configuration, it is possible to correct (return) the bonding wire 5 that has been deformed during bonding, during transportation after bonding, etc. to a pre-memorized shape, so that short circuits between adjacent bonding wires 5 or semiconductor chips 2 It is possible to prevent a short circuit between the area and the bond-in wire 5, and it is possible to reduce product defects (defective product rate) of the resin-sealed semiconductor device.

以上、本発明者によってなされた発明を、前記実施例に
基づき具体的に説明したが１本発明は。In the above, the invention made by the present inventor has been specifically explained based on the above embodiments, but one aspect of the present invention is as follows.

前記実施例に限定されるものではなく、その要旨を逸脱
しない範囲において種々変更可能であることは勿論であ
る。It goes without saying that the invention is not limited to the embodiments described above, and that various changes can be made without departing from the spirit thereof.

例えば１本発明は、半導体チップを樹脂で封止するＤ　
Ｉ　Ｐ　（Ｄｕａｌ上ｎ　１ｉｎｅ　Ｐ　ａｃｋａｇｅ
）型、ＱＦＰ（Ｑｕａｄ　Ｆｌａｔ　Ｐａｃｋａｇｅ）
型、　ＰＬＣＣ（Ｐｌａｓｔｉｃ　Ｌｅａｄｅｄ　Ｃｈ
ｉｐ　Ｃａｒｒｉｅｒ）型等のいずれの樹脂封止型半導
体装置にも適用することができる。For example, one aspect of the present invention is to seal a semiconductor chip with resin.
I P (Dual top n 1ine P package
) type, QFP (Quad Flat Package)
Type, PLCC (Plastic Leaded Ch
The present invention can be applied to any resin-sealed semiconductor device such as an ip carrier type.

また、本発明は、セラミックで形成された封止体で半導
体チップを封止するセラミック封止型半導体装置に適用
することができる。Further, the present invention can be applied to a ceramic sealed semiconductor device in which a semiconductor chip is sealed with a sealed body made of ceramic.

また、本発明は、アウターリードに電気的に接続したリ
ード配線（例えばメタライズ配線）と半導体チップの外
部端子とをボンディングワイヤで電気的に接続したセラ
ミック封止型半導体装置に適用することができる。Further, the present invention can be applied to a ceramic-sealed semiconductor device in which a lead wire (for example, a metallized wire) electrically connected to an outer lead and an external terminal of a semiconductor chip are electrically connected by a bonding wire.

また、本発明は、形状記憶合金として、　Ｎｉ　−Ｔｉ
合金以外のもの例えば半田メツキ層７と同等或はそれよ
りも低い温度で形状を記憶できる形状記憶合金を使用し
てもよい。Further, the present invention provides Ni-Ti as a shape memory alloy.
Other materials than alloys, such as shape memory alloys that can memorize their shape at a temperature equal to or lower than that of the solder plating layer 7, may also be used.

〔発明の効果〕〔Effect of the invention〕

本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

封止体の外部にアウターリードが設けられた半導体装置
の製品不良を低減できる。Product defects of semiconductor devices in which outer leads are provided outside the sealing body can be reduced.

また、半導体チップの外部端子とリードとをボンディン
グワイヤで電気的に接続する半導体装置の製品不良を低
減できる。Furthermore, product defects in semiconductor devices in which external terminals and leads of a semiconductor chip are electrically connected by bonding wires can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明の一実施例である樹脂封止型半導体装
置の要部拡大断面図、 第２図は、第１図に示す樹脂封止型半導体装置の全体の
断面図である。 図中、１・・・パッケージ、ＩＡ・・・樹脂、２・半導
体チップ、３Ａ・・・インナーリード、３Ｂ・・アウタ
ーリード、３Ｃ・・タブ、５・・ボンディングワイヤ、
５ａ・・・金属メツキ層、６，８・・金属メツキ層、７
・・・半田メツキ層である。FIG. 1 is an enlarged sectional view of essential parts of a resin-sealed semiconductor device according to an embodiment of the present invention, and FIG. 2 is an overall sectional view of the resin-sealed semiconductor device shown in FIG. 1. In the figure, 1... Package, IA... Resin, 2. Semiconductor chip, 3A... Inner lead, 3B... Outer lead, 3C... Tab, 5... Bonding wire,
5a... Metal plating layer, 6, 8... Metal plating layer, 7
...It is a solder plating layer.

Claims (1)

【特許請求の範囲】 １、封止体の外部にアウターリードが設けられた半導体
装置において、前記アウターリードを形状記憶合金で構
成したことを特徴とする半導体装置。 ２、半導体チップの外部端子とリードとをボンディング
ワイヤで電気的に接続し、これらを封止体で封止する半
導体装置において、前記ボンディングワイヤを形状記憶
合金で構成したことを特徴とする半導体装置。[Scope of Claims] 1. A semiconductor device in which an outer lead is provided outside a sealed body, characterized in that the outer lead is made of a shape memory alloy. 2. A semiconductor device in which external terminals and leads of a semiconductor chip are electrically connected by bonding wires and these are sealed with a sealing body, characterized in that the bonding wires are made of a shape memory alloy. .
JP2299422A 1990-11-05 1990-11-05 Semiconductor device Pending JPH04171858A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2299422A JPH04171858A (en) 1990-11-05 1990-11-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2299422A JPH04171858A (en) 1990-11-05 1990-11-05 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04171858A true JPH04171858A (en) 1992-06-19

Family

ID=17872362

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2299422A Pending JPH04171858A (en) 1990-11-05 1990-11-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04171858A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH067257U (en) * 1992-06-22 1994-01-28 ヤマハメタニクス株式会社 Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH067257U (en) * 1992-06-22 1994-01-28 ヤマハメタニクス株式会社 Semiconductor device

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