JPH04170526A - Light gate array - Google Patents

Abstract

PURPOSE:To execute a logical operation among plural inputs by a single gate by providing a constitution including plural light detecting parts per gate. CONSTITUTION:A plurality of light detecting parts S are formed on an insulative substrate IS or a conductive semiconductor substrate CS, on one of the light detecting parts S a light modulating part M together with a pair of electrodes C are formed, and a constant voltage power supply is connected therebetween. A plurality of input rays Pin are irradiated on the light detecting parts S from a substrate side and output rays Pout are output as reflected rays of bias rays Pbias irradiated on the light modulating part S. In this case, four kinds of gates can be formed in accordance with a connection method between the light detecting part S and the light modulating part M, and a mutual connection method between plural light detecting parts. Since a plurality of light beams per gate can be input, a multivalued logical operation can be executed by a single gate.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention relates to an optical gate array having a function of performing logical operations between a plurality of two-dimensional optical input information and outputting the results as two-dimensional optical information. It is related to.

[Prior Art] Conventionally, the development of optical gate arrays has been highly desired as key devices for optical information processing and optical signal processing. Conventionally, as this type of device, two multiple quantum well (MQW) pin-type optical converters formed on the same semiconductor substrate have been used, for example, as seen in the literature "Applied Physics Letters, Vol. 52, p. 1419." It has a configuration in which the external electrodes are connected in series and a constant voltage source is connected to both ends.
The optical input intensity of the first pin type optical modulator causes the second p
"Symmetric Seed (S-3EED)" has the function of changing the transmitted light of the light irradiated to the in-type optical modulator.
An element called J has been proposed. In this element, due to the quantum confined Stark effect (QC3E), transmitted light with a constant bias can be controlled by input light having the same wavelength. Its composition and characteristics are explained in the 12th section.
This will be explained using figures. As shown in the cross-sectional view of the main part in FIG. 12(a), the p-AlGaAs layer 101. i-MQW layer 10
2. MQW composed of n-AlGaAs layer 103
- pin structure 1001 is i p-AlGaAs insulating layer 1
It is laminated on a GaAs substrate 120 with 10 interposed therebetween.

First MQW-pin structure 100□ n-AlGaA
p- of the s layer 103 and the second MQW-pin structure 100□
The AlGaAs layer 101 is connected to the electrode 1 via the insulating film 130.
40. Note that 150 is a constant voltage source.

In such a configuration, the first M Q W-p in
The input light incident on the i structure (light detection section) 1001 is P l
n + second MQW-pinll structure (light modulation section) 10
The bias light incident on 0□ is P bias+the transmitted light is P. When ut, the positive logic bistable characteristic shown in FIG. 12(b) appears in the pin out characteristic.

[Problems to be Solved by the Invention] However, the above-described optical gate array has the following five problems.

(1) Since the number of inputs per gate is one, it is necessary to use a plurality of gates to perform logical operations between a plurality of optical inputs.

(2) Since the extinction ratio of the optical modulator is low, in order to connect this optical gate array in multiple stages and operate it, it is necessary to perform differential operation using two input lights, as shown in Figure 8. It was necessary to configure one gate with two pini structures.

(3) There is no gain in the photodetector section, and input light intensity comparable to that of bias light is required to operate the gate.

(4) When the input light is reduced to zero, the device is reset to the off state, so in order to maintain the on state, it was necessary to constantly irradiate light with a constant intensity.

(51 In order to improve the S/N ratio, it was necessary to separate the input light and bias light, and a highly accurate and complex optical system was required.

Therefore, an object of the present invention is to perform logical operations between multiple inputs in one
The object of the present invention is to obtain an optical gate array that can be made with a single gate, has a large extinction ratio, has a gain, is simple in structure, and has memory properties.

[Means for Solving the Problems] In order to solve such problems, the optical gate array according to the present invention includes a plurality of photodetecting sections whose electrical output changes by irradiating the first light onto the semiconductor substrate. , has a function of changing the reflected light intensity of the second light by this electrical output, and has a pin elliptic structure including a multiple quantum well (MQW) structure in the i layer and a multilayer reflective structure in the second layer or the n layer. The optical modulator is arranged in a direction perpendicular or parallel to the substrate surface, and arranged two-dimensionally.

[Function] In the optical gate array according to the present invention, the above problem is solved by the function described below.

(1) Since the optical gate array according to the present invention includes a plurality of photodetecting sections per gate, multi-value logical operations are possible with one gate.

(21) In the optical gate array according to the present invention, high contrast can be obtained due to the following three structural features, so that lead terminal operation is possible with a single pin structure.

(2) The thickness of the i-MQW layer is as thick as possible to form a depletion layer.

(2) By reducing the thickness of the barrier layer of the i-MQW layer to less than half that of the well layer, the total thickness of the well layer, that is, the effective absorption length, is increased.

02 layer or n layer is DBR (distributed).
By adopting a Bragg reflector structure, the effective absorption length is doubled.

(3) In an optical gate array in which the photodetector is a phototransistor J or a thyristor, high-gain first-element terminal operation is possible.

4) An optical gate array in which the photodetector is a thyristor has a function of maintaining the optical output state after switching even if the input light is turned off.

The four input lights and the bias light are incident from opposite directions across the semiconductor substrate, and the output light is taken out as reflected light of the bias light, so the input light and the output light are completely separated.

[Example] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIGS. 1(a) to (d) are cross-sectional configuration diagrams showing the schematic configuration of an optical gate array according to the present invention, and FIGS. 2(a) to (d)
) shows an equivalent block diagram corresponding to FIG. The basic structure of the optical gate array according to the present invention is that a plurality of photodetecting sections S are formed on an insulating substrate IS or a conductive semiconductor substrate CS, and a light modulating section is disposed on one of the photodetecting sections S. M is formed and a pair of electric currents [
An iC is formed between which a constant voltage source (not shown) is connected. In addition, a plurality of input lights Pi are incident on the photodetector S from the substrate side, and the output light Pout is the light modulator M.
The bias light P bias is output as reflected light. The following four types of gates are possible depending on the method of connecting the photodetecting section S and the light modulating section M and the method of connecting the plurality of photodetecting sections S to each other.

The conductivity of the substrate and the position at which the electrodes are taken out differ accordingly. To summarize the above, as shown in Table 1 below, the photodetector section S is composed of, for example, a photodiode (hereinafter referred to as PD), a heterophototransistor (hereinafter referred to as HPT), and a thyristor (hereinafter referred to as ST). The light modulation section M includes a DBR layer having a structure in which two semiconductor layers with different refractive indexes are alternately stacked, an MQW layer and a cladding layer in a structure in which two semiconductor thin layers with different band gaps are alternately stacked. It consists of a reflective MQW modulator consisting of:

Next, the operating principle of the optical gate array according to the present invention will be explained using FIGS. 3 to 8.

First, the operating principle of the MQW modulator will be explained using FIG.

FIG. 3 is a diagram explaining the operating principle of the MQW-pin modulator. The figure (a) shows the MQW-pi shown in the figure (b).
It shows changes in the absorption spectrum of the i-layer when a reverse bias voltage ■ is applied to the n-structure MQW optical modulator MD. Due to the quantum confinement Stark effect (QC3E), the exciton absorption peak appearing near the absorption edge shifts to the longer wavelength side as the reverse bias voltage V increases. Here, the absorption edge, that is, the exciton absorption wavelength when reverse bias is applied (V''VR) is ^1.
The exciton absorption wavelength at zero bias (V=O) is assumed to be λ2. The optical power P at these wavelengths. The voltage dependence of the intensity of ut is shown in FIG. 3(c).

As shown in FIG. 3(c), in the case of wavelength λ1, the optical output P increases as the reverse bias voltage V increases. , , , decreases, and conversely increases for wavelength λ2. As above, MQW
The optical output intensity of the -pin MQW optical modulator MD can be changed by a reverse bias voltage, and the direction of increase or decrease can be selected by the operating wavelength. Note that the following explanation assumes that the operating wavelength is λ1.

Next, the operating principle when an MQW modulator and a single photodetector are combined will be explained.

FIG. 4(a) shows a case where an MQW optical modulator MD and a photodiode PD or a phototransistor HPT are connected in series as shown in FIG. 4(b). Optical input P1. =
In the case of O, since the photodiode FD and the like are in an oven state, the MQW optical modulator MD is in a zero bias state and in a high output state (optical output P., 1-1). In the case of optical input P and fi=1, the photodiode PD is short-circuited, so the MQW optical modulator MD is in a reverse bias state and is in a low output state (p, , , = o). That is, the Pl, . . . -Pout characteristics have NOR type gate characteristics as shown in FIG. 4(c).

FIG. 5(a) shows a case where an MQW optical modulator MD and a photodiode PD or a phototransistor HPT are connected in parallel as shown in FIG. 5(b). Note that in this case, a load resistor R is connected between the constant voltage source and the constant voltage source. In the case of optical input P i,=O, since the photodiode PD is in an open state, the MQW optical modulator MD is in a reverse bias state and becomes a low output state (optical output P.ut=0). When the optical input P 1n: 1, the photodiode PD is in a short-circuit state, so the MQW optical modulator MD is in a zero bias state and in a high output state (Pou, -1).
becomes. That is, the P in Pout characteristic has an OR type gate characteristic as shown in FIG. 5(C).

FIG. 6(a) shows a case where an MQW optical modulator MD and a thyristor SI are connected in series. For optical input Pin-0,
Since the thyristor SI is in the off state, the MQW optical modulator MD is in a zero bias state and in a high output state (optical output P
. , t=1). When the optical input PI is 1, the thyristor SI is in the on state, so the MQW optical modulator MD is in the reverse bias state and is in a low output state (P,, t”O). When turned on,
Even if the optical input is Pz-"O, the state is maintained, so the optical output remains P.Ut-0. That is, PIn
As shown in FIG. 6(b), the Pout characteristic includes a NOR type gate characteristic having memory properties. Light output P
. To reset ut=1, it is sufficient to turn off the bias light of the MQW optical modulator MD, turn off the constant voltage source, or short-circuit the thyristor SI.

In Figure 7, (a) shows the MQW optical modulator MD and the thyristor SI.
This is the case when they are connected in parallel. When the optical input PI0=0, the thyristor SI is in the off state, so the MQW optical modulator MD is in the reverse bias state, and the optical output is in the low output state (optical output P
. , t=O). When the optical input P, a = 1, the thyristor SI is in the on state, so the MQW optical modulator MD is in the zero bias state, and the output state is low (Po-t = 1).
becomes.

Here, once the thyristor SI is turned on, even if the optical input P1. In order to maintain the state even if = O,
Light output P. ut=1 remains. That is, p In
As shown in FIG. 7(b), the Pout characteristic includes an OR type gate characteristic having a memory property. Light output P.

To reset ut-1, it is sufficient to turn off the bias light of the MQW optical modulator MD, turn off the constant voltage source, or short-circuit the thyristor SI.

Next, an explanation will be given of the operation when the photodetector S is composed of a plurality of photodiodes PD. What will be described below is common to all cases where the photodetector S is a photodiode PD, a phototransistor HPT, a thyristor SI, etc.

FIG. 8(a) is a direct-to-straight type, that is, an MQW optical modulator MD.
This is a case where n photodiodes PD are all connected in series. n photodiodes PD, , PD2.
..., PD, when light is input to all of them (pa
Since the MQW optical modulator MD is switched to a low output state (P,, t=O) only when n□= P ln2 =...-PIIIl-1), it becomes a NAND gate (see truth table 2 below) .

Table 2 FIG. 8(b) shows the direct subtype, that is, the case where all n photodiodes PD are connected in parallel and further connected in series with the MQW optical modulator MD. n photodiodes PD1. When optical input is made to any of PD2, ..., PD (PI-1=1, PIfi2
= 1, ... or P l+xn=1), M
Since the QW optical modulator MD is switched to a low output state (P ou, -〇), it becomes a NOR gate (see truth table 3 below).

Table 3 FIG. 8(c) shows a case of parallel-straight type, that is, a case where n photodiodes PD are connected in series and further connected in parallel with an MQW optical modulator MD. When light is input to all n photodiodes PD, PD2゜..., PD (pan1=P ln2='・' P
11111 = 1), since the MQW optical modulator MD is switched to the high output state (P,, t = 1>),
It becomes an AND gate (truth table 4 below).
This is the case when all n photodiodes PD are connected in parallel. n photodiodes PD□, PD2.
. . . When optical input is made to either PD (P
01=1, Pln2=1.

...or P1□=1), the MQW optical modulator MD is switched to high output state Fli (P,, t = 1), so it becomes an OR gate (as shown in the truth table 5 below). photodiode PD and MQW optical modulator M
N depending on the connection method between D and photodiode PD.
AND, NOR, AND, and OR gates are possible.

Next, in the MQW-pin structure of the optical gate array according to the present invention, improvements to obtain high contrast are made using AlGa.
The As/GaAs system will be explained as an example.

First, by reducing the residual carrier concentration in the MQW-i layer to 1014 cm-9, which is about two impulses lower than the normal value, the maximum i-layer thickness that can be depleted at zero bias is reduced to 4 μm, four times that of the conventional one. and applied this value to the optical gate array.

Second, the thickness of the AlGaAs barrier layer was reduced to 50%, which is half of the conventional thickness.
8, the total number of well layers included in the i-MQW layer was increased by nearly 1.5 times. i-MQW
When the layer thickness is 4 μm, the conventional MQW structure (100 layers in the barrier layer and 100 layers in the well layer) has 200 periods, but the structure according to the present invention (50 layers in the barrier layer and 100 layers in the well layer) has 270 periods. cycles are possible.

Third, the n-AlAs layer (7158) and n-AIo,
By creating a DBR (distributed Bragg reflector) structure in which 3caO7As layers (629^) are alternately stacked for 25 periods, the effective absorption length is reduced to 2.
It was doubled.

As a result of the above, the extinction ratio is more than 30 times that of the conventional one (100:1).
can be obtained. Note that these improvements are based on InGa
As/InP, InAlAs/InGaAs, GaA
Other material systems such as s/rnGaAs are also applicable.

[Specific example] A pin photodiode is used for the PD, and the gate is set to G for 4 types.
aAs layer 4 An example realized using lGaAs will be described in (1) to (4) below. Next, elements using PD as HPT and thyristor will be explained in (5) and (6) especially regarding NAND gate (direct-image type).Furthermore, HPT configuration NAN
Other material systems for D-gate, namely QaAs/I
nGaAs system, InGaAs/InAlAs system, I
Examples (7) to (9) realized using nGaAs/InP system
Explain.

(1) GaAs/AlGaAs PD configuration NAND gate As shown in FIG. 9(a), a semi-insulating GaAs substrate IA
On top is an n+-GaAs layer (thickness 2μ) as a contact layer.
m) 2i, n Al(1,3Ga□, 7As
pin photodiode 2 formed with a layer (thickness 0.5 μm) 22, 1-GaAs layer (4 μm thick) 23, p-Al03can, 7As layer (thickness 0.5 μm>24), and p”-GaAs layer (thickness 0.1 μm) 3)
, a tunnel junction 3 formed of 3□ n'' GaAs layers (thickness 0.1 μm), and an n-AlAs layer (629 mm thick) and n-AI□, 3ca07 As layers (715 Å thick) alternately. n-DBR layer 40 with a structure in which 25 periods are stacked.
Undoped GaAs (100 layers thick) and undoped A
lO,3ca0.7As layer (thickness 50 people) and 2
i-MQW layer 42, p with a structure stacked with 7070 periods
-Al0.3caO,7As layer (thickness 0.5μm>43
, an MQW modulator 4 consisting of an MQW-pin structure formed with a p'' GaAs layer (thickness 0.1 μm>) were stacked by molecular beam epitaxial growth. Be and Si were used as p-type and n-type dopants, respectively. .

A 1.5 cm square chip was cut from the grown wafer. IQOμm square over a 1cm square area in the center, 2
The mesa was divided into a 50×50 matrix with a pitch of 0.00 μm to form bit constituent elements. MQW modulator 4 and p
The laminated portion with in photodiode 2 is arranged in 5 rows (interval 10
column) and 9 adjacent columns (45 columns in total) MQW
The modulator 4 and the tunnel junction 3 are removed by selective etching, and the nine layers 2. of the pin photodiode 2 are removed. exposed. Note that the n'' layer portion of the pin photodiode 2 is exposed by selective etching, and its width is 100 mm.
The size is μm×40 μm. From the above, one gate was constructed from 10 bit constituent elements.

The surface of the p-GaAs layer 43 of the MQW modulator 4 has a thickness of 80μ.
m x 20 μm first AuZnNi ohmic electrode (thickness 100 OA)5. The exposed 9 layer 24 of the pin7 photodiode 2 is covered with a second Au layer of 80 μm×40 μm.
ZnNi electrode (thickness 100OA > 6.80tzm x 20 for the exposed n+ layer 2 of the pin photodiode 2)
A first AuGeNi electrode (1000 μm thick) 7 was formed. The side surfaces of each mesa structure were insulated with a SiN film 8. In order to connect ten pin photodiodes 2 in series, the first AuGeNi electrode 7 and the adjacent pin
A first Cr/Au electrode 9 was formed to connect to the second AuZnNi electrode 6 of the n-photodiode 2. Further, a second Cr/AU electrode 10 is formed to connect the first AuZnNi electrodes 5 of each gate component, and
The first AuGeN of the final stage pin photodiode 2
Third Cr/Au electrode 1 to connect i electrodes 7 to each other
1 was formed. p-GaAs layer which becomes the light receiving part 4. After separating the substrate and the GaAs substrate IA on the back side of the device by selective etching, a SiO□/TiO2 multilayer antireflection film 12 was formed.

Second Cr/Au electrode 10 and third Cr/Au electrode 11
A constant voltage source (30V) was connected between the two. 860 nm semiconductor laser light was used for both input light and bias light.

10 input lights per gate are pinned from the back side of the board.
The input light P, is made incident on the photodiode 2. The intensity was varied in the range of 0 to 1 mW. Laser light with an intensity of 1 mW is focused as bias light to a spot diameter of 20 μm or less, and is made to enter the light input/output section of the element surface, and the reflected light P
. The strength of the ut was measured using a power meter. Only when all optical inputs PI+ exceed 0.5 mW does the negative logic gate characteristic appear as shown in Figure 4, and the extinction ratio (Poa
tH/PoltL) is 100:1. Response speed is Ions
Met.

(2) GaAS/AlGaAs-based PD elliptical NOR gate Ninth configuration b) The layer configuration is shown. This configuration is shown in Figure 9(a).
It is similar to

A 1.5 cm square chip was cut from the grown wafer. 100μm square over a 1cm square area in the center, 2
The mesa was divided into a 50×50 matrix with a pitch of 0.00 μm to form bit constituent elements. MQW modulator 4 and p
The laminated portion with in photodiode 2 is arranged in 5 rows (interval 10
column) and 9 adjacent columns (45 columns in total) MQW
The modulator 4 and tunnel junction 3 were removed by selective etching to expose the two layers 24 of the pin photodiode 2. Note that a part of the two layers 24 of the pin photodiode 2 on which the MQW modulator 4 is stacked is also exposed by selective etching, and its width is 100 μm x 40 μm.
It is. From the above, one gate was constructed from 10 bit constituent elements.

The surface of the p-GaAs layer 43 of the MQW modulator 4 has a thickness of 80μ.
mx20μm first AuZnNi ohmic electrode (1000mm thick)5. MQW modulator 4 is stacked p
The exposed two layers 24 of the in photodiode 2 have a thickness of 80μ.
m×20 μm second AuZnNi electrode (thickness 1000 μm
person)6. A third AuZnNi layer of 80 μm x 80 μm is placed on the two layers 24 of the pin photodiode 2 exposed on the entire surface.
An electrode (1000 mm thick) 13, and a first AuGeNi/Cr/Au electrode (2000 mm thick) on the back surface of the n-type semiconductor substrate 1.
0 people〉14 were formed. SiN film 8 covers the sides of each mesa structure.
Insulated by In order to connect ten pin photodiodes 2 in parallel, a second AuZnNi electrode 6 and a third AuZnN electrode of the pin photodiode 2 adjacent thereto are used.
A first Cr/Au electrode 9 was formed to connect to the i-electrode 13. Further, a second Cr/Au electrode 10 was formed to connect the first AuZnNi electrodes 5 of each gate component.

After the p-GaAs layer 43 serving as the light-receiving portion and the n-type semiconductor substrate 1 on the back side of the device were separated by selective etching, a SiO□/TiO□ multilayer antireflection film was formed.

First AuGeNi/Cr/Au electrode 14 and second Cr
A constant voltage source (30V) was connected between the /Au electrode 10 and the Au electrode 10. 860 nm semiconductor laser light was used for both input light and bias light. Ten input lights per one gate were made to enter the pin photodiode 2 from the back surface of the substrate, and the intensity of the input light Pin was varied in the range of 0 to 1 mW. A laser beam with an intensity of 1 mW is used as a bias light with a spot diameter of 20 mm.
The reflected light P is narrowed down to less than μm and is incident on the light input/output section of the element surface. The strength of the ut was measured using a power meter.

Any one optical input P1. ．． When the current exceeds 0.5 mW, the negative logic type gate characteristics deteriorate as shown in Fig. 4, and the extinction ratio (P outH / P o,, tL > 100
:1, response speed was Ions.

(3) GaAs/Al GaAs-based PD configuration AND gate As shown in FIG. 9(C), a semi-insulating GaAs substrate IA
A p+-GaAs layer (thickness 2μ) is formed on top as a contact layer.
m) 25. p-AI. ,, Gao7As layer (thickness 0,5, czm) 24, 1-GaAs layer (thickness 4
μm)23. pin photodiode 2 formed of n-AI□, 3ca0.7As layer (thickness 0.5 μm), 2z, n-AIAs layer (thickness 629A) and n-A
I□, n-DBR layer 41 with a structure in which 3Ga(,,7As layers (thickness: 715A) are stacked alternately for 25 periods.Undoped GaAs layer (thickness: 100A) and undoped Alo
, 27 layers alternately with 3ca0.7As layer (50 layers thick)
i-MQW layer 42 with a structure stacked with 070 periods. p-
Alo, 3Ga, ), 7As layer (thickness O55μm)
43, an MQW modulator 4 having an MQW-pin structure formed of a p''-GaAs layer (thickness 0.1 μm) was laminated by molecular beam epitaxial growth. Be and Si were used as p-type and n-type dopants, respectively. Using.

Chips of 1.5 crr+square were cut from the grown wafer. 100μmX over a 1cm square area in the center
The mesa was divided into a 50x50 matrix with a square size of 140 μm and a pitch of 200 Jim to form bit constituent elements.

5 rows of laminated parts of MQW modulator 4 and pin photodiode 2 (10 rows apart)! 1 and the 9th column adjacent to it (
A total of 45 columns of MQW modulators 4 and tunnel junctions were removed by selective etching to expose the 0 layer 2□ of the pin photodiode 2. A part of the 0 layer 2□ of the pin photodiode 2 on which the MQW modulator 4 is stacked is also exposed by selective etching, and its width is 100 μm x 40 μm.
It is m. Note that the p+ layer portion of the pin photodiode 2 is also exposed by selective etching, and its width is 100 μm×40 μm. From the above, one gate was constructed from 10 bit constituent elements.

The surface of the p-GaAs layer 43 of the MQW modulator 4 has a thickness of 80μ.
m×20 μm first AuZnNi ohmic electrode (thickness 100 OA)5. 80 on the exposed 0 layer 22 of the pin photodiode 2 on which the MQW modulator 4 is stacked.
μm×20 μm second AuGeNi electrode (thickness 100 μm
0 people〉15. A third AuGeNi layer of 80 μm x 80 μm is placed on the 0 layer 2 □ of the pin photodiode 2 exposed on the entire surface.
The electrode (thickness: 1000) 16, the exposed p'' layer 25 of the pin photodiode 2 has a fourth electrode (80 μm x 20 μm).
A ZnNi electrode (thickness: 1000) 17 was formed. The side surfaces of each mesa structure were insulated with a SiN film 8. 10
A first Cr/Au electrode 9 was formed to connect the fourth AuZnNi electrode 17 and the third AuGeNi electrode 16 of the adjacent pin photodiode 2 in order to connect the pin photodiodes 2 in series. First AuZ
nNi electric [! A second Cr/Au electrode 10 is formed on the first AuZnNi electrode 5 and the final stage pin.
In order to connect the fourth AuZnNi electrode 17 of the photodiode 2, a third Cr/Au electrode 11 and a fourth Cr/Au electrode 19 were formed on each electrode, and these were connected by wire bonding. p which becomes the light receiving part
- After peeling off the GaAs layer 43 and the GaAs substrate IA on the back side of the device by selective etching, 5i02/T
An iO2 multilayer antireflection coating was formed.

Third Cr/Au electrode 11 and fourth Cr/Au electrode 19
A constant voltage source (30V) was connected between the two. 860 nm semiconductor laser light was used for both input light and bias light.

10 input lights per gate are pinned from the back side of the board.
The input light P1° was made incident on the photodiode 2, and its intensity was varied in the range of 0 to 1 mW. Laser light with an intensity of 1 mW is focused as bias light to a spot diameter of 20 μm or less, and is made to enter the light input/output section of the element surface, and the reflected light P
. The intensity of at was measured using a power meter. Only when all the optical inputs Pla exceeds 0.5 mW, as shown in Fig. 6, negative logic type gate characteristics are obtained, and the extinction ratio (Pou
tH/PoutL) is 100:1. Response speed is Ions
Met.

[lGa5a/AlGaAs-based P[)-structured OR gate FIG. 9(d) shows the layer structure. This configuration is shown in Figure 9 (
It is the same as C).

A 1.5 cm square chip was cut from the grown wafer. 100 μm x 1 over a 1 cm square area in the center
The mesa was divided into a 50×50 matrix with 00 μm square and 200 μm pitch to form bit constituent elements. MQ
Five rows (10 rows apart) of the laminated portion of the W modulator 4 and the pin photodiode 2 are left, and the adjacent nine rows (4 rows in total) are left.
5 rows) and the tunnel junctions are removed by selective etching, and the 0 layer 2 of the pin photodiode 2 is removed.
2 was exposed. pi on which the MQW modulator 4 is stacked
A part of the 0 layer 22 of the n photodiode 2 is also exposed by selective etching, and its width is 100 μm×40 μm. One gate was composed of 10 bit constituent elements.

p-GaAs layer 4 of MQW modulator 4. 80μ on the surface of
m x 20 μm first AuZnNi ohmic electrode (1000 mm thick)5. MQW modulator 4 is stacked p
80μ on the exposed 0 layer 2□ of in photodiode 2
m×20 μm second AuGeNi electrode (thickness 1000 μm
person)15. Fully exposed pin photodiode 2-9
Layer 22 includes a third 80 μm x 80 μm AuGeN layer.
i-electrode (1000mm thick) 16, exposed p-GaA
On the surface of the s-substrate 1, there is a fifth AuZ layer of 80 μm x 20 μm.
An nNi electrode with a thickness of 1000 mm) was formed. The side surfaces of each mesa structure were insulated with a SiN film 8. 10 pi
In order to connect the n photodiodes 2 in parallel, a second Au
A first Cr/Au electrode 9 was formed to connect the ZnNi electrode 15 and the second AuGeNi electrode 16 to each other. Further, a second Cr/Au electrode 10 was formed to connect the second AuZnNi electrode 15 and the fifth AuZnNi electrode 18. After the p-GaAs layer 43 serving as the light-receiving portion and the GaAs substrate IA on the back side of the device were separated by selective etching, a SiO□/TiO2 multilayer antireflection film was formed.

A constant voltage source (30 V) was connected between the first Cr/Au electrode 10 and the second Cr/Au electrode 10. 860 nm semiconductor laser light was used for both input light and bias light. 1
Ten input lights per gate were made to enter the pin photodiode 2 from the back surface of the substrate, and the intensity of the input lights P, . . . was varied in the range of 0 to 1 mW. Laser light with an intensity of 1 mW is focused as bias light to a spot diameter of 20 μm or less, and is made to enter the light input/output section of the element surface, and the reflected light P
. . .

The strength was measured using a power meter. All optical inputs P
Only when in exceeds 0.5 mW, positive logic gate characteristics appear as shown in Figure 6, and the extinction ratio (POutH/PO
,,tL) is 100:1. The response speed was 10 ns.

(51GaAs/AlGaAs-based HPT configuration NAND gate As shown in Figure 10, an n''-GaAs layer (2 μm thick
) 201, n-GaAs layer (thickness 2 μm) 20
2°p-GaAs layer (thickness 2 μm) 203, n
-AI(,,3Ga(.

HPT formed with 7As layer (thickness 0.5μm>204
20, n-AlAs layer (thickness 629λ), and n-Al0
．． 3ca0.7As layer thickness 715 people) and 25
N-DBR layer 4□ with periodic stacked structure, undoped G
aAs layer (100 layers thick) and undoped A1°3caO
, 7As layers (thickness: 50 layers) are stacked alternately for 27070 cycles. 4□, p-Alo, , GaO
, 7As layer (thickness 0.5.czm) 43 , p''-G
MQW-p formed of aAs layer (thickness 0.1 μm)
The MQW modulator 4 having an in structure was laminated by molecular beam epitaxial growth. Be and Si were used as p-type and n-type dopants, respectively. Other configurations are shown in Figure 9(a)
It is similar to

Second Cr/Au electrode 21 and third Cr/Au electrode 22
Do not connect a constant voltage source (30V) between the 860 nm semiconductor laser light was used for both input light and bias light.

HPT inputs 10 beams per gate from the back side of the board.
20, and the intensity of the input light PIo is set from 0 to 100.
It was varied between μW. Laser light with an intensity of 1 mW is focused as bias light to a spot diameter of 20 μm or less, and is made to enter the light input/output section on the surface of the element, and its reflected light P. The intensity of 1 t was measured using a power meter. Only when all the optical inputs Pi5 exceed 10 μW does the negative logic gate characteristic appear as shown in Figure 4, and the extinction ratio (PoutH/P,...
tL) is 100:1. The response speed was 50 ns.

(6) GaAs/AI GaAs-based HPTIII NAND gate As shown in Figure 11, semi-insulating GaAs
A p”-GaAs layer (
Thickness: 2 μm) 301, p-AI□, 3GaO, 7
As layer (thickness 1.czm) 302, n-GaAs
layer (thickness: 2 μm) 303, P-GaAs layer (thickness: 0.3 μm).
Thyristor 30 formed of 2μm) 304, n-Alo, 3Ga07As layer with a thickness of 0.5μm) 305
, n-AlAs layer (thickness 629), and n-AlO
, 3ca0.7As layer (thickness 715 people) and 25
N-DBR layer 412 with periodic laminated structure undoped G
aAs layer (100 layers thick) and undoped Al (,3c
i-MQW layer 4□, p-Alg, 3G with a structure in which aO, 7As layers (50 layers thick) are stacked alternately for 27070 cycles
ao, 7As layer (thickness 0.5 μm) 43. p"-G
MQW-pi formed of aAs layer (thickness 0.1 μm)
An MQW modulator 4 having an n-elliptic structure was laminated by molecular beam epitaxial growth. Be and Si were used as p-type and n-type dopants, respectively. The other configurations are the same as in FIG. 9(a).

Second Cr/Au electrode 21 and third Cr/Au electrode 22
A constant voltage source (30V) was connected between the two. 860 nm semiconductor laser light was used for both input light and bias light. ■10 input lights per gate from the back side of the board
T20, and the intensity of the input light P, n is O~10
It was varied between 0 μW. Intensity 1mW as bias light
The laser beam is narrowed down to a spot diameter of 20 μm or less, and is made incident on the light input/output section on the surface of the element, and the reflected light P. 3. The strength was measured using a power meter. All optical input Pi1
1 exceeds 10 μW, negative logic type gate characteristics appear as shown in FIG. 6, and the extinction ratio (PoutH/Po
utL) was 100:1, and the response speed was 50 ns.

(7) GaAs/InGaAs HPT structure NAND gate As shown in FIG. 10, an n''-GaAs layer (thickness 0°5
μm) 2o, n-GaAs layer (thickness 2zzm) 20
2, p-GaAs layer (thickness 0.2 μm) 203,
n-A1. ), 3ca0.7As layer (thickness 0.5μm
) 204 and the n-AlAs layer (
1118 n-DBR layer 4 consisting of 25 periods of alternately laminated n-GaAs layers (thickness: 758 layers) and n-GaAs layers (thickness: 629 layers).
1. The i-MQW layer 42 has a structure in which undoped InO, 15caO, 55As layers (thickness: 100 layers) and undoped GaAs layers (thickness: 100 layers) are stacked alternately for 100 periods.
, an MQW modulator 4 having an MQW-pin structure formed of a p''-GaAs layer (thickness: 0.5 μm) 43 were stacked by molecular beam epitaxial growth. P type.

Be and Si were used as n-type dopants, respectively. The element configuration is the same as that shown in FIG. 9(a).

Second Cr/Au electrode 21 and third Cr/Au electrode 22
A constant voltage source (3 ov) was connected between the two. Input light is 8
50nm semiconductor laser light, 11050n as bias light
A titanium-doped sapphire laser beam was used. Ten input lights per gate were made to enter the HPT 20 from the back surface of the substrate, and the intensity of the input light pin was varied between 0 and 100 μW. Laser light with an intensity of 1 mW is focused as bias light to a spot diameter of 20 μm or less, and the MQW modulator 4
The reflected light P is incident on the surface of P. The strength of the ut was measured using a power meter. All optical input P1□ is 10μW
As shown in Figure 4, negative logic type gate characteristics occur only when the extinction ratio (PoutH/PoutL) exceeds 1.
0:1, and the response speed was 50 ns.

(8) InGaAs/InAlAs-based HPT elliptic NAN
D gate semi-insulating configuration n”-Inn on nP substrate,
53caO, 47As layer (thickness 2 μm), n
-1no, 53A1. ), 47As layer (thickness 2μ
m), p InO, 53Ga□, 47As layer (
Thickness: 0.2μm), n”-In□, 53
H formed of ca0.47As layer (thickness 0.5μm)
PT, n-Ino, 52AIO, 4gAs layer (thickness 1225) and n 1no, 5z (Alo, zsG
ao7,). An n-DBR layer consisting of a structure in which 4gAs layers (thickness 1120 layers) are alternately stacked for 40 periods, undoped InO, 53ca0.47As well layers (70 layers thick) and undoped In (1,52Al., 4gAs barrier). i-MQW layer, P-Ino, 52AI(
,,4gAs grading layer (thickness 0.5μm), p”
-Ing, 53GaO, 47As cap layer (thickness 0
．． MQW-pin structure formed with a thickness of 1 μm)
Laminated by. The device configuration is the same as that in FIG. 9(a) except that the etching of the InP substrate of the optical input section is omitted.

Second Cr/Au electrode 10 and third Cr/Au electrode 11
A constant voltage source (30V) was connected between the two. Semiconductor laser light of 1520 nm was used for both input light and bias light.

10 input lights per gate are pinned from the back side of the board.
Inject it into photodiode 2, and set its intensity pin to 0 to 1.
It was varied between 00 μW. Intensity 1m as bias light
The W laser beam is narrowed down to a spot diameter of 20 μm or less. M
The reflected light intensity P is incident on the surface of the QW modulator 4. u
t was measured using a power meter. Only when all the optical inputs P1 exceed 10 μW, as shown in FIG. 4, negative logic type gate characteristics occur, and the extinction ratio (P,

tH/P,,,L) is 25:1, response speed is 5Q
It was ns.

f91 InGaAs/InP HPT type device n''-In, ), 53Ga(
,,47As layer (thickness 2μm), nIn□,
53GaO, 47As layer (thickness 2 μm), p I
No53Gao47As layer thickness 0. 2μm),
HP formed by n-1nP layer (thickness 0.5.um)
T, n-1nP (thickness 1222 people) and nIn0.63
GaO, 37AS0.80 Po, 20 (thickness 11
n consisting of a structure in which 30 people) were alternately stacked for 40 cycles.
-DBR layer, undoped In□, 53ca0.47
As well layer (80mm thick) and undoped InP barrier layer (
The i-MQW layer consists of a structure in which layers (thickness 50 layers) are laminated alternately for 230 periods, and the p-fnP grading layer (thickness 0
, 5 tt m), p” Ino, 53
An MQW-pin structure formed of a caO, 47As cap layer (thickness O, 1 μm) was grown using a gas source MBE method.

The element configuration is the same as in (1) above, except that the etching of the InP substrate of the optical input section is omitted.

A constant voltage source (30 V) was connected between the second Cr/Au electrode and the third Cr/Au electrode. Semiconductor laser light of 1550 nm was used as both input light and bias light. Ten input lights per gate are input to the pin photodiode from the back side of the board, and the intensity of the optical input PI+ is set to O~1.
It was varied between 00 μW. Intensity 1m as bias light
Focus the W laser beam to a spot diameter of 20 μm or less, and
The reflected light P is incident on the surface of the QW modulator. The strength of the ut was measured using a power meter. All optical input pins
Only when exceeds 10 μW, as shown in Figure 4, negative logic type gate characteristics occur and the extinction ratio (Po.1H/Pou
tL) is 20:1. The response speed was 50 ns.

``Effects of the Invention'' As explained above, according to the optical gate array according to the present invention, multiple optical inputs are possible per gate, so multivalued logical operations are possible with a single gate. 20
By using an MQW pin structure of db or more, an optical gate can be constructed with a single pin structure. In addition, an element whose photodetector is a phototransistor or a thyristor can perform a high-gain lead terminal operation, and when the photodetector is a thyristor, it has a memory function. Since the input light and the bias light are irradiated from opposite sides of the substrate, the separation between the input and output lights is good and the S/N ratio is high. With such a configuration, by using the optical gate array according to the present invention, an extremely excellent effect can be obtained in that multi-stage multi-valued logical operations between two-dimensional optical information can be performed with a simple configuration at high speed and with high precision. .

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the main parts showing the element configuration of the optical gate array according to the present invention, FIG. 2 is a block diagram of FIG. 1, FIG. 3 is a diagram showing the characteristics of the optical modulation section, and FIGS. The figure shows the characteristics of the photodetector, FIG. 8 shows the equivalent circuit of the optical gate array according to the present invention, and FIGS. 9 to 11 are cross-sectional views showing the configuration of the optical gate array according to the present invention. , FIG. 12 is a sectional view showing the configuration of a conventional optical gate array. CS: Semiconductor substrate, IS: Insulating substrate, M
...Light modulation section, S...Light detection section, MD...
MQW modulator, PD...photodiode, PHT
-・Heterophototransistor, SI...thyristor.

Claims (5)

[Claims] (1) Perform logical operations between two-dimensional input information of multiple lights,
In an optical gate array having a function of outputting the result as two-dimensional optical information, a plurality of photodetecting units whose electrical output changes by irradiating input light onto a semiconductor substrate;
an optical modulation section having a function of changing the optical output intensity according to the electrical output and having a pin structure including a multi-quantum well structure in the i-layer and a multi-layer reflective structure in the p-layer or n-layer in a direction perpendicular to the substrate surface; Alternatively, an optical gate array characterized in that they are arranged in parallel directions and arranged two-dimensionally. (2) The optical gate array according to claim 1, wherein all of the plurality of light detection sections and light modulation sections are connected in series. (3) The optical gate array according to claim 1, wherein the plurality of photodetectors are connected in parallel, and the optical modulators are connected in series. (4) The optical gate array according to claim 1, wherein the plurality of photodetectors are connected in series, and the optical modulators are connected in parallel. (5) The optical gate array according to claim 1, wherein all of the plurality of light detection sections and light modulation sections are connected in parallel.