JPH04314022A - Optical gate array - Google Patents

Abstract

PURPOSE:To obtain an optical gate array capable of optical signal processing and optical information processing at a high speed by accelerating an OFF time while holding light amplifying action and the high speed of an ON time which are characteristics in the case of using phototransistors. CONSTITUTION:A light receiving part T for changing an electric output at the time of irradiating a semiconductor substrate(SS) 101 with input light and an optical modulation part M having a function for changing the reflectivity factor of bias light by the electric output, including multiplex quantum well structure in an (i) layer and constituted of multiplex reflection structure of a (p) layer or pin structure are vertically laminated on the face of the SS 101 and connected to a constant voltage power supply series and a load resistor (micro-crystal silicon film 110) is connected to the modulation part M in parallel.

Description

[Detailed description of the invention]

0001

FIELD OF THE INVENTION This invention relates to optical gate arrays driven and controlled by optical signals.

0002

2. Description of the Related Art Optical gates and optical gate arrays are strongly desired to be developed as key devices for optical signal processing and optical information processing. Examples of this type of element include, for example, Japanese Patent Application No.
As disclosed in No. 179481, it has a configuration in which a multiple quantum well (MQW) pin type optical modulator and a phototransistor are connected in series, and a constant voltage power supply is connected to both ends of the modulator. An element has been proposed that changes the reflection intensity of bias light incident on an MQW-pin type optical modulator depending on the intensity of input light. A feature of this element is that the current amplification effect of the phototransistor allows a strong change in output light to be obtained with a weak input light, so it has an optical amplification function, and as a result, the elements can be optically connected in multiple stages. Furthermore, this optical gate array provides high contrast due to the three structural features described below.

[0003] The thickness of the i-MQW layer is increased to the maximum possible value for depletion. (2) By reducing the thickness of the barrier layer of the i-MQW layer to less than half that of the well layer, the total thickness of the well layer, that is, the effective absorption length, is increased. (2) By forming the p-layer or n-layer into a DBR (distributed Bragg reflector) structure, the effective absorption length is doubled. Furthermore, in this optical gate array,
By providing a DBR structure between the light receiving section and the light modulating section, it is possible to optically separate the input light and bias light, and electrically connect the light receiving section and the light modulating section in series. It has the feature that elements can be constructed on the same substrate.

0004

[Problems to be Solved by the Invention] However, the above-mentioned device has the following problems. Since a phototransistor is used as the light receiving section, the capacitance of the element increases by the current gain due to the Miller effect. The on-time response is faster than when using a photodiode because the current gain of the phototransistor cancels out the increase in capacitance due to the Miller effect, but there is a problem in that the off-time is delayed by the increase in capacitance due to the Miller effect.

Therefore, an object of the present invention is to speed up the off-time while maintaining the optical amplification effect and high-speed on-time, which are characteristics of using a phototransistor, thereby enabling high-speed optical signal processing and optical information processing. The object of the present invention is to provide a processable optical gate array.

[0006]

[Means for Solving the Problems] In order to achieve the above object, an optical gate array according to the present invention has a load resistor connected in parallel with the optical modulator as shown in the following figure. FIG. 7 is a cross-sectional view showing the configuration of an optical gate array according to the present invention. The figure shows a case where the light receiving section is a heterojunction phototransistor (HPT). As shown in the figure, the optical gate of the present invention includes an HPT 15 consisting of an n- collector layer 12, a p- base layer 13, and an n- emitter layer 14 grown on an n+ semiconductor substrate 11;
The n-DBR layer 16 has a structure in which two n-type semiconductor layers with different refractive indexes (n) are laminated alternately in several layers with a thickness of 1/(4·n) of the wavelength of the incident light and bias light. It is composed of a pin structure light modulation section 19 consisting of an i-MQW layer 17 and a p layer 18 which are formed by laminating a plurality of two different i-type semiconductor thin layers alternately. It has a structure in which a load resistor 20 is formed between it and 18. Also, for high contrast, AR
A coating 21 is applied, and Au is applied to the p layer 18 as an electrode.
The ZnNi electrode 22 is made of AuGe, and the n-type semiconductor substrate 11 is made of AuGe.
Using the Ni electrodes 23, the AuZnNi electrodes 22 of the p layer 18 of each element are collectively wired onto the polyimide layer 25 using the Cr/Au electrode 24, and a constant voltage -Vb is applied. Each pixel component operates independently depending on the input light Pin.

In such a configuration, the input light Pin enters the HPT 15 from the back side of the n+ semiconductor substrate 11, and the output light Pout is emitted as reflected light of the bias light Pbias irradiated onto the pin structure light modulator 19. be done. When the input light Pin is absorbed by the n+ semiconductor substrate 11, the n+ semiconductor substrate 11 is partially etched to transmit it.

[0008]

[Operation] In the optical gate array according to the present invention, the above-mentioned problems are solved by the operation explained below.

The operation of the optical gate will be explained using FIG. FIG. 8(a) shows an equivalent circuit of FIG. 7. Figure 8
(b) is an equivalent circuit of a conventional example without a resistor connected in parallel to the optical modulator. FIG. 8(c) shows the IV curves (dotted lines) of the MQW-pin structure and the load resistance, and the IV curve (straight line) that is the sum of the two, together with the constant voltage source. Also shown is the dependence of the IV curve of the phototransistor on the intensity of the incident light Pin. Now pi
The n-structure light modulator 19 is irradiated with bias light of a constant intensity, the intensity of the input light Pin incident on the HPT 15 is increased from zero, and the light intensity of the output light Pout as reflected light of the bias light Pbias is monitored. It shall be. As the input light Pin increases from L1, L2, ..., L4, the IV curve of the HPT 15 shifts upward along the I axis, so the operating points of this electric circuit become a, b, ...
, e. At this time, the voltage applied to the pin structure light modulator 19 increases, and the reflectance changes due to the quantum confined Stark effect. Note that the intensity of the incident light Pin is L4
Even in the above case, the operating point e remains constant, so
The intensity of the output light Pout remains unchanged. Next, input light Pin
Let us consider the response speed when the load resistance value is changed for the optical gate shown in FIG. 8(a) when the intensity of is L6. When the amount of voltage change during switching is ΔV and the capacitance of the element is C, the following equation holds. Q=C·ΔV (1) Here, the amount of charge Q is given by the integral shown in Equation 1.

0010

[Math 1]

Here, ts is the response time, and Δi is the current amount of HPT at a certain voltage V during switching and MQ
It is given as the difference between the total current amount of W-pin and load resistance. Therefore, from equations (1) and (2), the number 2
The formula shown is obtained.

0012

[Math 2]

From this equation, the response speed ts becomes faster as the element capacitance C becomes smaller, and becomes faster as Δi becomes larger. At this time, the capacitance of the element is given by the sum of the respective capacitances of the HPT 15 and the pin structure optical modulator 19, and this value is the load resistance 2
Even if you change the value of 0, it will not change. Furthermore, the value of ΔV is also approximately constant within a range that provides the same contrast. Therefore, the response time when the value of the load resistance 20 is changed can be compared based on the difference in the magnitude of Δi. Δi at the moment when the intensity of input light Pin changes from L0 to L6 in FIG. 8(c)
is the difference in the amount of current between point f and point a, and after that, while the voltage applied to the MQW-pin increases by ΔV to point e with time (on time), the current of HPT15 reaches point f.
to point e along the IV curve, and the amount of current flowing through the pin structure optical modulator 19 and the load resistor 20 changes from point a to point e. Further, Δi at the moment when the intensity of input light Pin changes from L6 to L0 is the difference in the amount of current between point g and point e, and the sign is opposite to Δi of the on time.
The voltage applied to the pin structure light modulator 19 decreases. Until the operating point returns to point a (off time), the amount of current in HPT 15 moves from point g to point a along the IV curve of HPT 15, and the amount of current between pin structure optical modulator 19 and load resistor 20 increases. The amount of current moves from point e to point a. When the value of the load resistor 20 changes, this Δi changes, and as the resistance value becomes smaller, the point e in FIG. 8(c) moves upward along the current axis. Therefore, as the load resistance 20 becomes smaller, the off-time ΔI becomes larger, and therefore the off-time becomes faster. On the other hand, Δi during the on-time becomes smaller, but since the current of the HPT 15 during the on-time is large, there is no significant increase in the resistance value within a range in which contrast, which will be described later, does not deteriorate.

Next, comparing the conventional example shown in FIG. 8(b) with the present invention, when the load resistor 20 is not connected, the operating point moves from point e to point h. Therefore, Δi of the on time becomes large and Δi of the off time becomes small. Comparing the case with and without the load resistor 20, the on-time Δi does not change much, but the off-time Δi becomes much larger in the case of the present invention. Therefore, in the optical gate array of the present invention, the off time can be increased without increasing the on time.

On the other hand, the optical amplification effect becomes smaller because the threshold input intensity increases from L1 in the conventional example to L4, but it is still larger than when a photodiode is used as the light receiving section.

As can be seen from the above description, the response speed and threshold input strength are variable depending on the resistance value, and therefore can be freely set depending on the application. At this time, the contrast does not decrease in a large range where the load resistance value satisfies the following formula: I(HPT)>I(MQW)+Vb/R.

[0017]

Embodiments Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings. FIG. 1 is a cross-sectional view of an element using GaAs/AlGaAs, showing the structure of one embodiment of the optical gate array according to the present invention. In the figure, Si-doped n
- Three components on a GaAs substrate 101 (thickness 350 μm): p-GaAs cap layer 108 (thickness 0.1 μm), p-Al0.3 Ga0.7 As cladding layer 107 (thickness 0.5 μm) , undoped GaAs
Well layer (thickness 10 nm) and undoped Al0.3 Ga
The i-MQW layer 106 and the n-
AlAs layer (thickness 71.5 nm) and n-Al0.3G
a0.7 As layer (thickness 62.9 nm) and 25
A reflection mode MQW pin modulator M having a structure in which n-DBR layers 105 having a periodic laminated structure are sequentially laminated, and an n-Al0.3 Ga0.7 As emitter layer 104.
(thickness: 0.5 μm), p-GaAs base layer 103 (thickness: 0.25 μm), and n-GaAs collector layer 102
A heterojunction phototransistor structure (HPT structure) T having a thickness of 4 μm was formed by molecular beam epitaxial growth. The p-type and n-type dopants include Be, respectively.
Si was used.

This grown wafer was processed as shown in FIG. AuZnNi is used as the p-type electrode 109, and the n-type electrode 113 is used as the p-type electrode 109.
As the material, AuGeNi was used. As a load resistance, a microcrystalline silicon film 110 is used as an n-DB.
A Cr/Au electrode 112 is grown on the R layer 105 to a thickness of approximately 1 μm.
The microcrystal silicon film 110 and the p-GaAs cap layer 10 of the reflection mode MQW pin modulator M are
By electrically connecting with 8, reflection mode MQW
A load resistance of 1KΩ was configured in parallel to the pin modulator M. At this time, a SiO2 thin film 116 is deposited to form a Cr/Au film.
The electrode 112 and the i-MQW layer 106 were prevented from electrically contacting each other. AR coating 114 is applied to obtain high contrast. When configuring as a two-dimensional array, a polyimide layer 11 is formed between the p-type electrodes 109 of each pixel.
Connection is made by a Cr/Au electrode 112 wired on top of the Cr/Au electrode 112.

Further, in this embodiment, the microcrystalline silicon film 110 is used as the load resistor, but it is also possible to use a metal thin film in addition to this.

FIG. 2 shows the measured response speed of the element according to this example. This figure shows the results when the mesa radius of the microcrystalline silicon film 110 is changed to change the value of the load resistance. In the figure, the conventional example is the response time when the load resistance is removed for the same sample. In this way, the smaller the load resistance, the shorter the off time.
The effect of arranging n modulators in parallel is shown. Even if the load resistance is reduced, the on-time does not change much. In this case, it also has an optical amplification function and has a high contrast of about 20 dB or more in any case.

FIG. 3 is a sectional view showing the structure of another embodiment of the optical gate array according to the present invention. The figure shows a configuration in which the DBR layer is used separately as another structure constituting the load resistor. The difference from the above-mentioned embodiment is that instead of using a microcrystalline silicon film or a metal thin film as a load resistor, the n-DBR layer 105 is separated into two parts by etching, one of which is used as a resistance layer. The n-DBR layer 105 used as a load resistor has an i
- Remove up to the MQW layer 106 by etching. At this time, the step between the separated n-DBR layers 105 is filled with a polyimide layer 111, and a SiO2 thin film 116 is deposited on it to prevent electrical contact between the Cr/Au electrode 112 and the i-MQW layer 106. I made it. In this case as well, the same results as in FIG. 2 were obtained.

FIG. 4 is a sectional view showing the structure of still another embodiment of the optical gate array according to the present invention. This is an example in which proton ion implantation is used to separate the DBR layer, eliminating the need for embedding. In the figure, the part where proton ions were implanted (n-DB
The R layer 117) becomes a high resistance layer of several tens of kilohms or more, and can electrically separate the DBR layer into two parts, providing the same effect as in FIG. 5. In this case as well, the same results as in FIG. 2 were obtained.

FIG. 5 is a cross-sectional view showing the structure of another embodiment of the optical gate array according to the present invention. This is an example. In this case, the portion of the p-AlGaAs layer 115 not used as a resistance layer was removed by selective etching up to the p-GaAs cap layer 108. The constructed resistance layer and DBR layer are Cr/Au.
Connected by electrode 112. When configuring this element as a two-dimensional array, only the p-type electrode 109 deposited on the p-GaAs cap layer 108 of each pixel is made of Cr.
/Au electrode 112, p-AlGaAs layer 115
Avoid contacting the upper p-type electrode 109. In this case as well, the same results as in FIG. 2 were obtained.

FIG. 6 is a cross-sectional view showing the structure of another embodiment of the optical gate array according to the present invention. In this embodiment, proton ions are implanted into the low resistance n-DBR layer to form that part (the n-DBR layer). 117) with high resistance and used as a load resistor. The difference from the example shown in FIG.
The following is used as a load resistance. In this case as well, the resistance value could be changed by changing the area and depth of ion implantation, and results similar to those shown in FIG. 2 were obtained.

Another example of increasing the resistance of the n-DBR layer is to diffuse a p-type dopant such as Be.

[0026] In the above-mentioned embodiment, GaAs/A
Although the optical gate is made of lGaAs, the present invention is not limited to this, and may be made of InGaAs/InP, InAlA
It can also be applied to other material systems such as s/InGaAs and GaAs/InGaAs.

[0027]

Effects of the Invention As explained above, according to the optical gate array according to the present invention, the off time is increased while maintaining the optical amplification effect and high on time, which are characteristics of using phototransistors. can. Therefore, optical signal processing and optical information processing can be performed at high speed. Furthermore, the optical gate array according to the present invention can change the optical amplification effect and response speed by changing the load resistance value without reducing the contrast, and can be freely set to a value suitable for the purpose of processing. Extremely excellent effects such as a large degree of freedom can be obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the structure of an embodiment of an optical gate array according to the present invention.

FIG. 2 is a diagram showing the response speed of the element in FIG. 1;

FIG. 3 is a sectional view showing the structure of another embodiment of the optical gate array according to the present invention.

FIG. 4 is a cross-sectional view showing a structure according to still another embodiment of the optical gate array according to the present invention.

FIG. 5 is a cross-sectional view showing the structure of another embodiment of the optical gate array according to the present invention.

FIG. 6 is a cross-sectional view showing the structure of another embodiment of the optical gate array according to the present invention.

FIG. 7 is a sectional view showing the configuration of an optical gate according to the present invention.

FIG. 8 is a diagram illustrating the operation of the optical gate.

[Explanation of symbols]

11 n+ semiconductor substrate 12 n-collector layer 13 p-base layer 14 n-emitter layer 15 heterojunction phototransistor (HPT)
16 n-DBR layer 17 i-MQW layer 18 p layer 19 pin structure optical modulator 20 load resistor 21 AR coating 22 AuZnNi electrode 23 AuGeNi electrode 24 Cr/Au electrode 25 polyimide layer 101 Si-doped n-GaAs substrate 102
n-GaAs collector layer 103 p-GaA
s base layer 104 n-Al0.3 Ga0.7 As emitter layer 105 n-DBR layer 106 i-MQW layer 107 p-Al0.3 Ga0.7 As cladding layer 108 p-GaAs cap layer 109
P-type electrode 110 Microcrystalline silicon film 111
Polyimide layer 112 Cr/Au electrode 113 N-type electrode 114 AR coating 115 p-AlGaAs layer 116 SiO2 thin film 117 n-DBR layer M Reflection mode MQW pin modulator T H
PT structure

Claims (3)

[Claims] 1. An optical gate array that controls output light intensity based on input light intensity, comprising: a light receiving section that changes electrical output by irradiating input light onto a semiconductor substrate, and a reflectance of bias light that changes based on the electrical output. It has a changing function and includes a multi-quantum well structure in the i-layer, and a multi-reflection structure in the p-layer.
an optical modulating section having a layer or a pin structure is stacked perpendicularly to the surface of the semiconductor substrate, the light receiving section and the modulating section are connected in series to a constant voltage power source, and a load resistor is connected in parallel with the optical modulating section. An optical gate array characterized by: 2. The optical gate array according to claim 1, wherein a high resistance semiconductor thin film layer or a thin metal resistance layer is used as the load resistor. 3. The optical gate array according to claim 1, wherein a high-resistance layer in which a part of a low-resistance semiconductor thin film layer is made high in resistance is used as the load resistor.