JP2657288B2 - Optical gate array - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical gate array having a function of controlling two-dimensional output information of a second light by two-dimensional input information of a first light. .

[Prior Art] Conventionally, development of an optical gate array has been highly desired as a key device for optical information processing and optical signal processing. Conventionally, as an element of this type, for example, a document “Applied
As shown in "Physics Letters, Vol. 52, p. 1419", two multi-quantum well (MQW) pin-type optical converters formed on the same semiconductor substrate are connected in series by external electrodes, and a constant voltage source is connected to both ends thereof. And the first pi
An element called “Symmetric Seed (S-SEED)” having a function of changing the transmitted light of the light applied to the second pin type optical modulator according to the light input intensity of the n-type optical modulator has been proposed. ing. In this device, the transmitted light of light with a constant bias can be controlled by the input light having the same wavelength as that of the light by the quantum confined Stark effect (QCSE). The configuration and characteristics will be described with reference to FIG. As shown in the sectional view of the main part in FIG. 8 (a), the p-AlGaAs layer 101,
MQW-pin structure composed of i-MQW layer 102 and n-AlGaAs layer 103
100 ₁ is stacked on the GaAs substrate 120 via the ip-AlGaAs insulating layer 110. N-AlGaAs layer of _first MQW-pin structure 100 ₁
103 and the second p-AlGaAs layer 101 of the MQW-pin structure 100 ₂ are connected by the electrode 140 via an insulating film 130. In addition,
150 is a constant voltage source.

In such a configuration, a bias light is incident input light incident first MQW-pin structure (light detection unit) 100 ₁ P _in, the second MQW-pin structure (light modulating unit) 100 ₂ Is P _bias , and the transmitted light is P _out, and a positive logic type bistable characteristic shown in FIG. 8B appears _{in the} Pin-P _out characteristic.

[Problem to be Solved by the Invention] However, in the above-mentioned optical gate array, the following 4
There were two problems.

(1) Since the extinction ratio of the light modulator is low, it is necessary to perform differential operation using two input lights in order to perform multi-stage operation, and as shown in FIG. Had to be configured.

(2) There is no gain of the light detection unit, and an input light intensity equivalent to that of the bias light is required.

(3) When the input light is set to zero, the light is reset to the off state. Therefore, in order to maintain the on state, it is necessary to constantly irradiate light of a constant intensity.

(4) Separation of input light and bias light is required from the viewpoint of improving the S / N ratio, and a highly accurate and complicated optical system is required.

Therefore, an object of the present invention is to provide an optical gate array having a large extinction ratio, a high gain, a simple configuration, and a memory property.

[Means for Solving the Problems] In order to solve such problems, a first optical gate array according to the present invention comprises a light detection unit whose electric output changes when a semiconductor substrate is irradiated with first light. And a pin structure having a function of changing the reflected light intensity of the second light by the electric output, including a multiple quantum well (MQW) structure in an i-layer, and including a multilayer reflection structure in a p-layer or an n-layer. A light modulating section and a light modulating section which are vertically stacked on the substrate surface and are two-dimensionally arranged, and provided with one electrode such that the light detecting section and the light modulating section are electrically connected in parallel. It is.

According to the second optical gate array of the present invention, in the first optical gate array, a load resistor and a constant voltage power supply are connected between a pair of electrodes, and the load resistor is formed on the same semiconductor substrate. It was made into a conductive thin film.

[Operation] In the optical gate array according to the present invention, i-MQW
The thickness of the layer is so large that it can be depleted.
By reducing the thickness of the barrier layer of the i-MQW layer to half or less of the well layer, the total thickness of the well layer, that is, the effective absorption length is increased. By making the p-layer or the n-layer a DBR (Distributed Bragg Reflector) structure, the effective absorption length is doubled. These structural features provide high contrast,
A single pin structure enables optical three-terminal operation.

In addition, the input light and the bias light are incident on the semiconductor substrate from opposite directions, respectively, and the output light is extracted as reflected light of the bias light, so that the input light and the output light are completely separated.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a cross-sectional view showing a configuration of an optical gate array according to an embodiment of the present invention.
The figure shows the case of a pin photodiode (hereinafter referred to as a PD type). In the figure, p layer 2 _1, i layer on p ⁺ semiconductor substrate 1
2 _2, n layer 2 ₃ consisting of a plurality of sets stacked structure of two alternating semiconductor thin layers having different photodiode 2 and the refractive index are formed by n-DBR layer 3 _1, two semiconductor thin layers having different band gaps I-MQW consisting of a structure in which a plurality of sets are alternately stacked
The MQW modulator 3 having a layer 3 _2, p layer 3 ₃ is a structure laminated. The p-layer 33 of the MQW modulator ₃ and the p ⁺ semiconductor substrate 1 are connected by a first electrode 5 via an insulating film 4.
The second electrode 6 is drawn out from the n layer 2 ₃ of the photodiode 2. Although not shown, a constant voltage source and a load resistor are connected between these electrodes 5 and 6.

In such a configuration, the input light P _in is incident to the photodiode 2 from the p ⁺ semiconductor substrate 1 side, the output light P _out is
The light is emitted as reflected light of the bias light P _bias applied to the MQW modulator 3. When the input light P _in is absorbed by the p ⁺ semiconductor substrate 1, by partially etching the p ⁺ semiconductor substrate 1, and transmits.

FIG. 1 (b) is a cross-sectional view showing the configuration of another embodiment of the optical gate array according to the present invention. Is shown. In the figure, n ⁺ semiconductor substrate 1 over the n- emitter layer 7 _1, p-base layer 7 _2, n- collector layer
7 ₃ HPT7 and FIG formed by (a) the same MQW modulator 3 are stacked. In this case, the n- emitter layer ₇₁ in order to increase the gain of the optical detection unit uses a semiconductor band gap greater than p- base layer 7 _2. The p-layer 33 of the MQW modulator ₃ and the p ⁺ semiconductor substrate 1 are connected by a first electrode 5, and the n-collector layer of the HPT 7
From 7 ₃ are led out second electrode 6.

In such a configuration, the input light P _in is incident on the HPT 7 from the p ⁺ semiconductor substrate 1 side, and the output light P _out is emitted as reflected light of the bias light P _bias applied to the MQW modulator 3.

FIG. 1 (c) is a cross-sectional view showing a configuration of an optical gate array according to still another embodiment of the present invention.
FIG. 1 shows a case where the light detecting unit is an optical thyristor having a pnpn structure (hereinafter referred to as a PNPN type). In the figure, n ⁺ first n layer 8 ₁ on the semiconductor substrate 1, a first p-layer 8 _2, the second n layer 8 _3, the thyristor 8 is formed in the second p-layer 8 _4, the thyristor 8 second p-layer 8 ₄ and MQW modulator 3 of n-DBR layer 3 ₁ and the electrically p ⁺⁺ layer 9 ₁ for short-circuiting, a tunnel is formed by n ⁺⁺ layer 9 ₂ joining 9 And the MQW modulator 3 similar to FIG. 1 (a) is sequentially connected. The p layer 3 ₃ and the n-type semiconductor substrate 1 of the MQW modulator 3 are connected by the first electrode 5 and second electrode 6 is drawn out from the first p-layer 8 ₄ of the thyristor 8 ing.

In such a configuration, the input light P _in is incident to the thyristor 8 from p ⁺ semiconductor substrate 1 side, the output light P _out is emitted as reflected light of the irradiated bias light P _bias the MQW modulator 3.

FIG. 1 (d) is a cross-sectional view showing the configuration of another embodiment of the optical gate array according to the present invention. In FIG. 1 (d), the p ⁺ layer 10 ₁ is used instead of the tunnel junction 9 of FIG. , n ⁺ layer 10 ₂
The thyristor 8 and the MQW modulator 3 are short-circuited by using the interconnect layer 10 and the electrodes 5 and 6 formed by the above.

Since the optical gate arrays shown in FIGS. 1 (a) to 1 (d) do not include a load resistance inside, one external voltage resistor is individually connected to each optical gate array, and then one constant voltage source is connected. Connected to.

On the other hand, the optical gate array shown in FIGS. 1 (e) and 1 (f) is an element in which a load resistance is formed monolithically, and a pair of electrodes formed in a modulator and a resistance layer are used for all array elements. Connected in common. An example using a resistive epitaxial film 11 made of a layer, ^- Fig. 1 (e) is n via the contact layer 7 ₄ between the semiconductor substrate 1 and HPT7
FIG. 1 (f) shows an example using a resistively deposited film 12 formed on a semi-insulating substrate 1A.

In FIGS. 1 (e) and 1 (f), the third electrode 13 is an MQW
P layer 3 ₃ ohmic electrodes of the modulator 3, the fourth electrode 14 HP
Connected contact layer 7 ₄ ohmic electrodes n- emitter layer ₇₁ of the T7, the fifth electrode 15 is an electrode for connecting the third electrode 13 and fourth electrode 14, the sixth electrode 16 electrodes for ohmic electrodes drawn from the n-layer 3 ₁ and HPT7 of n- collector layer 7 _third MQW modulator 3, the electrode 17 of the seventh connecting the sixth electrode 16 mutual array configuration device, eighth Electrodes 18
Reference numeral 7 denotes an electrode for connecting electrodes formed through the resistive epitaxial film 11 of the array constituent element.
A constant voltage source is connected between the third electrode 17 and the eighth electrode 18. In FIG. 1F, the resistively deposited film 12 formed on the semi-insulating substrate 1A is connected between the fifth electrode 15 and the eighth electrode 18.

Hereinafter, in the configuration described with reference to FIGS. 1 (a) to 1 (f), the conductivity type of each layer is all inverted, and a modulator and a photodetector are stacked in this order on a semiconductor substrate to form a light input / output direction. The reverse is also possible.

FIG. 2 shows an equivalent circuit of the optical gate array according to the present invention. FIG. 7A shows the case of the PD type, and the MQW
The modulator 3 and the photodiode 2 are connected in parallel with the same polarity, and a load resistance 19 made of the resistive epitaxial film 11 or the resistive vapor deposition film 12 is provided at both ends.
And the constant voltage source 20 are connected. Here, the MQW modulator 3 and the photodiode 2 are also reverse-biased. FIG. 2B shows a case of the HPT type, in which the MQW modulator 3 and the hetero phototransistor 7 are connected in parallel, and further, a load resistor 19 and a constant voltage source 20 are connected on both sides thereof. Here, the MQW modulator is reverse-biased, and the hetero-photo transistor 7 is forward-biased. FIG. 4C shows a case of the PNPN type, in which the MQW modulator 3 and the thyristor 8 are connected in parallel, and further, a load resistor 19 and a constant voltage source 20 are connected to both ends thereof. Here MQW
The modulator 3 is reverse biased and the thyristor 8 is forward biased.

Next, the operation principle and characteristics of the optical gate array according to the present invention will be described with reference to FIGS.

FIG. 3 is a diagram for explaining the operating principle of the MQW-pin modulator. FIG. 3A shows the MQW-pin modulator 3 shown in FIG.
3 shows the change in the absorption spectrum of the i-layer when the reverse bias voltage V is applied. Quantum confined Stark effect (QCSE)
As a result, the exciton absorption peak appearing near the absorption edge shifts to the longer wavelength side as the reverse bias voltage V increases. Here, the absorption edge, that is, the exciton absorption wavelength when a reverse bias is applied (V = V _R ) is λ ₁ , and the exciton absorption wavelength when a zero bias is applied (V = 0) is λ ₂ . Optical output P _{out at} these wavelengths
FIG. 3 (c) shows the voltage dependence of the intensity of the above. Figure (c)
For the wavelength lambda ₁ as shown in the intensity of the light output P _out with increasing reverse bias voltage V decreases, in the case of wavelength lambda ₂ is increased to the contrary. As described above, the light output intensity of the MQW-pin modulator 3 can be changed by the reverse bias voltage, and the direction of increase or decrease can be selected by the operating wavelength.

FIG. 4 shows an equivalent circuit generalizing the optical gate array according to the present invention. In the drawing, when the voltage applied to the MQW modulator 3 and V, the relationship between the photocurrent I _PD voltage V and a light detector (for example, a photodiode 2) is expressed by the following equation.

_{V = V B -R (I PD} + I MOD) = V 0 -R · I PD however, where _{V 0 = V B -R · I} MOD, V B is a voltage of the bias power supply, R represents the load resistance resistance , I _MOD is the photocurrent of the modulator.

The voltage V ₀ is the voltage of the MQW modulator 3 when the light detector is in a dark state (I _PD = 0). From this equation, the current I _PD
It can be seen that the voltage V decreases in proportion to.

FIG. 5 is a diagram for explaining how the optical output P _out of the MQW modulator 3 changes with an increase _in the optical input Pin when the optical detector is a photodiode or a phototransistor. In FIG. 3A, the solid line indicates the photodiode (F
The I-V characteristic of D), the broken line is the I-V characteristic of the phototransistor (HPT), FIG. (B) The MQW modulator P _out -V
It is a characteristic. P light input P _in is from P ₀ = P as shown in FIG.
_1, P _2, ···, current with the increase and P ₅ I _PD is light input P _in
Increase in proportion to Accordingly, the operating point of the photodiode is represented by W ₀ , W ₁ ,
W _2, ···, W ₅ and for continuously moving in the direction of the arrow, the voltage V is V _0, V _1, V _2, · · ·, decreases as V _5. Since the photodiode and the MQW modulator are connected in parallel, the voltage of the photodiode directly becomes the applied voltage of the MQW modulator.
As described with reference to FIG. 3, if the voltage V of the MQW modulator 3 decreases, the optical output P _out increases.

As described above, the gate characteristics as shown in FIGS. 7A and 7B appear in the light input / output characteristics of the PD type and the HPT type. The intensity of the light input P _in which switching takes place is an area where the product of the current generated by the light detecting unit and the load resistance is the voltage the same order of the constant voltage source. Here, if the operating wavelength (V _{B to} I _PD · R) is the absorption edge, it becomes OR, and if it is the exciton wavelength, it becomes NOR.

Figure 6 if the light detector of the optical thyristor, an optical input P _in
FIG. 7 is a diagram for explaining how the optical output P _out of the MQW modulator changes with an increase in. 2A shows the IV characteristic of the optical thyristor, and FIG. 2B shows the optical output P _out − of the modulator.
It is a V characteristic. As the light input P _in is increased and P _1, P ₂ from P ₀ = 0, the breakdown voltage of the optical thyristor is reduced. Along with this,
The operating point of the thyristor is the load straight line L corresponding to the load resistance R.
The move discontinuously in the arrow direction from W ₂ to W ₃ above, the voltage decreases abruptly from V _H to V _L. Since the thyristor and the MQW modulator are connected in parallel, the voltage of the thyristor becomes the applied voltage of the MQW modulator as it is. As described with reference to FIG. 3, if the voltage of the MQW modulator 3 decreases rapidly, the optical output P
_out increases rapidly.

Here, since the operating point even zero light input P _in again remains at W _3, the optical output P _out holds a high output state. To return to the initial state, the constant voltage source may be turned off or the thyristor section may be short-circuited.

As described above, the PNPN optical input / output characteristic has a gate characteristic having a memory characteristic as shown in FIG. 7 (c). The intensity of the light input P _in which switching takes place is that the switching of the thyristor occurs. When the operating wavelength is the absorption edge, the result is OR, and when the operating wavelength is the excitation output wavelength, the result is NO.

Next, in the MQW-pin structure of the optical gate array according to the present invention, an improvement point for obtaining a high contrast is described as AlGaAs / GaA.
The s-system will be described as an example.

First, by reducing the residual carrier concentration of the MQW-i layer to 10 ^-14 cm ^-3, which is about two orders of magnitude lower than the normal value, the maximum i-layer thickness that can be depleted at zero bias can be reduced. The value was extended to 4 μm, and this value was applied to the optical gate array.

Second, the total number of well layers included in the i-MQW layer was increased by about 1.5 times by reducing the thickness of the AlGaAs barrier layer to 50 ° which is 1/2 of the conventional thickness. That is, when the thickness of the i-MQW layer is 4 μm, the conventional MQW structure (barrier layer 100 #, well layer 100
In (ii), the period is 200, but in the structure according to the present invention (barrier layer 50 °, well layer 100 °), 270 periods are possible.

Third, an n-AlAs layer (715 °) and an n-Al _0.3 Ga _0.7 As layer (6
29Å) and a DBR (Distributed Bragg Reflector) structure in which 25 periods are alternately stacked to double the effective absorption length.

As described above, it is possible to obtain an extinction ratio (100: 1) of 30 times or more as compared with the conventional case. These improvements are based on InGaAs / InP, I
It can be applied to other material systems such as nAlAs / InGaAs and GaAs / InGaAs.

[Specific examples] Examples in which the PD, HPT, and PNPN devices are realized by the GaAs / AlGaAs system are described in (1) to (3) below. In particular, the HPT device is made of another material, that is, a GaAs / InGaAs system. , InGaAs / InAlA
Examples realized in s-system and InGaAs / InP-system are shown in (4) to (6) below.
Will be described. Finally, examples of monolithic lamination of resistive thin films for GaAs / AlGaAs-based HPT devices are given in (7) below.
This will be described in (8).

(1) GaAs / AlGaAs-based PD element As shown in FIG.
Al _0.3 Ga _0.7 As layer (thickness 0.5 μm), i-GaAs layer (thickness 4 μm)
m), p formed by n-Al _0.3 Ga _0.7 As layer (thickness 0.5 μm)
in photodiode structure and n-AlAs layer (629mm thick)
N-DBR layer and undoped GaAs layer (thickness: 1) having a structure in which an n-Al _0.3 Ga _0.7 As layer (thickness: 715 °) is alternately stacked for 25 periods.
00Å) and an undoped Al _0.3 Ga _0.7 As layer (thickness 50Å) are alternately stacked for 270 periods, i-MQW layer, p-Al _0.3 Ga _0.7
An MQW-pin structure formed of an As layer (thickness 0.5 μm) and ap ⁺ -GaAs layer (thickness 0.1 μm) was laminated by molecular beam epitaxial growth. Be and Si are the p-type and n-type dopants, respectively.
Was used.

1.5 cm square chips were cut out from the grown wafer. The mesa was divided into a 50 × 50 matrix at a pitch of 100 μm square and 200 μm over a central area of 1 cm square to form bit components. The n-layer portion of the pin photodiode is exposed by selective etching, and its width is
It is 100 μm × 40 μm. An 80 μm × 20 μm AuZnNi ohmic electrode (thickness: 1000 μm) is formed on the surface of the p-GaAs cap layer.
Iv) An AuGeNi electrode (thickness: 1000 mm) of 80 μm × 40 μm was formed on the exposed n-layer, and an AuZnNi ohmic electrode (thickness: 1000 mm) was formed on the exposed substrate surface by mesa etching. Insulate the sides of the bit component with SiN film,
A first Cr / Au electrode was formed to connect the AuZnNi ohmic electrodes on the aAs cap and on the substrate surface. Further, a second Cr / Au electrode was formed on the AuZnNi electrode formed on the n-layer. P-GaAs layer on the light-receiving part and GaAs on the back side of the device
After peeling off the substrate by selective etching,
An O ₂ / TiO ₂ multilayer antireflection film was formed.

A load resistance (10 KΩ) and a constant voltage source (30 V) were connected between the first Cr / Au electrode and the second Cr / Au electrode. 860 nm semiconductor laser light was used for both input light and bias light. Input light is incident from the rear surface of the substrate was varied the intensity of the input light P _in a range of 0～5MW. 1mW intensity as bias light
Was narrowed down to a spot diameter of 20 μm or less and made incident on the light input / output unit on the element surface, and the intensity of the reflected light P _out was measured with a power meter. When light input P _in = 1 mW as shown in FIG. 7 (a), P _in the -P _out characteristics appear positive logic gate characteristics, the extinction ratio _{(P out H / P out L} ) is 100: 1 And the response speed was 10ns.

(2) GaAs / AlGaAs based HPT type device As shown in FIG.
Al _0.3 Ga _0.7 As layer (thickness 0.5 μm), p-GaAs layer (thickness 0.2 μm)
m), and HPT structure formed by n-GaAs layer (thickness: 2μm), n-AlAs layer (thickness 629A) and n-Al _0.3 Ga _0.7 As layer (thickness 715A) and alternately 25 period stacking the N-D of the structure
BR layer, undoped GaAs layer (100mm thick) and undoped Al
I-MQW layer and p-Al _0.3 Ga _0.7 As layer (thickness 0.5 μm) having a structure in which _0.3 Ga _0.7 As layers (thickness: 50 °) are alternately stacked for 270 periods.
m), MQW-pin formed of p ⁺ -GaAs layer (0.1 μm thick)
The structure was laminated by molecular beam epitaxial growth. Other configurations are the same as those in FIG.

A load resistance (10 KΩ) and a constant voltage source (30 V) were connected between the first Cr / Au electrode and the second Cr / Au electrode. 860 nm semiconductor laser light was used for both input light and bias light. Input light is incident from the rear surface of the substrate was varied the intensity of the input light P _in a range of 0～100MyuW. A laser beam with an intensity of 1 mW is narrowed down to a spot diameter of 20 μm or less as bias light,
The light was made incident on the light input / output unit on the element surface, and the intensity of the reflected light P _out was measured by a power meter. When light input P _in = 10 .mu.W as shown in FIG. 7 (a), P _in -P _out characteristics appeared positive logic gate characteristics, the extinction ratio _{(P out H / P out L} ) is 100:
1.The response speed was 50ns.

(3) GaAs / AlGaAs PNPN type device As shown in FIG.
Al _0.3 Ga _0.7 As layer (thickness 0.5 μm), p-GaAs layer (thickness 0.2 μm)
m), an n-GaAs layer (2 μm in thickness), a PNPN structure formed of a p-Al _0.3 Ga _0.7 As layer (1 μm in thickness), and an n-AlAs layer (thickness)
629Å) and the n-Al _0.3 Ga _0.7 As layer (thickness 715Å) alternately
An n-DBR layer, an undoped GaAs layer (thickness 100 mm) and an undoped Al _0.3 Ga _0.7 As layer (thickness 50
Å) and i-MQW layer, p-
Al _0.3 Ga _0.7 As layer (thickness 0.5 μm), p ⁺ -GaAs layer (thickness 0.1
μm) and an MQW-pin structure formed by molecular beam epitaxy. Other configurations are the same as those in FIG.

A load resistance (10 KΩ) and a constant voltage source (30 V) were connected between the first Cr / Au electrode and the second Cr / Au electrode. 860 nm semiconductor laser light was used for both input light and bias light. Input light is incident from the rear surface of the substrate was varied the intensity of the input light P _in a range of 0～100MyuW. A laser beam with an intensity of 1 mW is narrowed down to a spot diameter of 20 μm or less as bias light,
The light was made incident on the light input / output unit on the element surface, and the intensity of the reflected light P _out was measured by a power meter. When light input P _in = 10 .mu.W as shown in FIG. 7 (b), positive logic gate characteristics appeared to have a memory effect in the P _in -P _out characteristics, the extinction ratio (P
_out H / P _out L) was 100: 1, and the response speed was 10 ns.

(4) GaAs / InGaAs based HPT type element An n-Al _0.3 Ga _0.7 As layer (thickness 0.5
μm), p-GaAs layer (thickness 0.2 μm), n-GaAs layer (thickness 2
μm) and an n-AlAs layer (thickness 758).
Å) and n-GaAs layer (thickness 629Å) are alternately stacked for 25 periods. An n-DBR layer, undoped In _0.15 Ga _0.85 As layer (thickness 100Å) and undoped GaAs layer (thickness 100Å) An i-MQW layer having a structure alternately stacked for 100 periods and an MQW-pin structure formed by a p ⁺ -GaAs layer (thickness: 0.5 μm) were stacked by molecular beam epitaxial growth. The element configuration is the same as (1).

A load resistance (10 KΩ) and a constant voltage source (30 V) were connected between the first Cr / Au electrode and the second Cr / Au electrode. For input light
A semiconductor laser beam of 850 nm was used, and a titanium-doped sapphire laser beam of 1050 nm was used as bias light. Input light is incident from the rear surface of the substrate, the intensity of the input light P _in 0
It was changed in the range of 100100 μW. Intensity 1 as bias light
A laser beam of mW was narrowed down to a spot diameter of 20 μm or less, made incident on a light input / output unit on the element surface, and the intensity of the reflected light P _out was measured by a power meter. Positive logic gate characteristics appear _{in the} Pin- _Pout characteristics, and the extinction ratio ( _PoutH / _PoutL ) is 10: 1,
The response speed was 50 ns.

(5) InGaAs / InAlAs-based HPT device An n-In _0.52 Al _0.48 As layer (thickness 0.5
μm), p-In _0.53 Ga _0.47 As layer (thickness 0.2 μm), n ⁺ -In
HPT structure formed of _0.53 Ga _0.47 As layer (2 μm thickness), n-In _0.52 Al _0.48 As layer (1225 mm thick) and n-In _0.52
(Al _0.25 Ga _0.75 ) _0.48 As layer (1120 mm thick) n-DBR layer consisting of 40 layers alternately laminated, undoped In
_0.53 Ga _0.47 As well layer (70 mm thick) and undoped In _0.52 Al
_An i-MQW layer having a structure in which a _0.48 As barrier layer (thickness of 50 °) is alternately stacked for 250 periods, a p-In _0.52 Al _0.48 As cladding layer (0.5 μm thick), p ⁺ -In _0.53 Ga _0.47 As An MQW-pin structure formed by a cap layer (thickness: 0.1 μm) was laminated by MBE. The element configuration is the same as the above (1) except that the etching of the InP substrate of the light input section is omitted.

A load resistance (10 KΩ) and a constant voltage source (30 V) were connected between the first Cr / Au electrode and the second Cr / Au electrode. A semiconductor laser light of 1520 nm was used for both input light and bias light. Input light is incident from the rear surface of the substrate was varied the intensity of the input light P _in a range of 0～100MyuW. A laser beam with an intensity of 1 mW is narrowed down to a spot diameter of 20 μm or less as bias light,
The light was made incident on the light input / output unit on the element surface, and the intensity of the reflected light P _out was measured by a power meter. Positive logic gate characteristics appear _{in the} Pin- _Pout characteristics, and the extinction ratio ( _PoutH / _PoutL ) is 2
5: 1, the response speed was 50 ns.

(6) InGaAs / InP-based HPT device An n-InP layer (0.5 μm thick), p-I on a Si-doped InP substrate
HPT structure formed of n _0.53 Ga _0.47 As layer (0.2 μm thickness) and n-In _0.53 Ga _0.47 As layer (2 μm thickness), n-InP layer (1222 mm thick) and n-In _0.63 Ga _0.37 As _0.80 P _0.20 layer (thickness 11
N-DB with a structure in which 30 cycles are alternately stacked for 40 cycles
R-layer, undoped In _0.53 Ga _0.47 As well layer (thickness 80 Å) and undoped InP barrier layer (thickness 50 Å) are alternately stacked for 230 periods i-MQW layer, p-InP cladding layer (thickness 0.5 μm), p ⁺ -In _0.53 Ga _0.47 As cap layer (thickness 0.1
μm) was grown using a gas source MBE method. The element configuration is the same as the above (1) except that the etching of the InP substrate of the light input section is omitted.

A load resistance (10 KΩ) and a constant voltage source (30 V) were connected between the first Cr / Au electrode and the second Cr / Au electrode. Semiconductor laser light of 1550 nm was used for both input light and bias light. Input light is incident from the rear surface of the substrate was varied the intensity of the input light P _in a range of 0～100MyuW. A laser beam with an intensity of 1 mW is narrowed down to a spot diameter of 20 μm or less as bias light,
The light was made incident on the light input / output unit on the element surface, and the intensity of the reflected light P _out was measured by a power meter. Positive logic gate characteristics appear _{in the} Pin- _Pout characteristics, and the extinction ratio ( _PoutH / _PoutL ) is 2
0: 1, the response speed was 50 ns.

(7) An element having the structure shown in FIG. 1 (e) was manufactured using a GaAs / AlGaAs system. N ^- AlG between the substrate and the n-emitter layer of the HPT
This is the same as the above (2) except that an aAs layer and an n ⁺ -GaAs layer are inserted. In this configuration, light input / output characteristics similar to the above (2) were obtained.

(8) A device having the structure shown in FIG. 1 (f) was manufactured using a GaAs / AlGaAs system. (2) except that a semi-insulating substrate is used as the substrate, and an n ⁺ -GaAs layer is inserted between the substrate and the n-emitter layer of the HPT.
Is the same as The resistive thin film was formed of a polycrystalline silicon film. In this configuration, light input / output characteristics similar to the above (2) were obtained.

[Effects of the Invention] As described above, according to the optical gate array of the present invention, by using the MQW-pin structure having a high extinction ratio,
An optical gate can be configured with a single pin structure. Also, an element in which the photodetector is a phototransistor or a thyristor can perform high-gain three-terminal operation, and has a memory function when the photodetector is a thyristor. Since the input light and the bias light are radiated from opposite sides of the substrate, the separation between the input and output light is good and the S / N ratio is high. With such a configuration, when the optical gate array according to the present invention is used, an extremely excellent effect that a multi-stage logical operation between two-dimensional information of light can be performed at high speed and with high accuracy with a simple configuration can be obtained.

[Brief description of the drawings]

1 (a) to 1 (f) are cross-sectional views of main parts showing the configuration of an optical gate array element according to the present invention, FIGS. 2 (a) to 2 (c) are diagrams showing equivalent circuits, and FIG. A diagram showing the characteristics of the modulation unit,
FIG. 4 is a diagram showing an equivalent circuit, FIG. 5 is a diagram for explaining the operating principle of the PD-type and HPT-type devices, FIG. 6 is a diagram for explaining the operating principle of the pnpn-type device, and FIG. FIG. 8 is a diagram showing output characteristics, and FIG. 8 is a diagram for explaining the configuration of a conventional element. 1 ... semiconductor substrate, 1A ... semi-insulating substrate, 2 ... photodiode (PD), 3 ... MQW modulator, 4 ... insulating film,
5 first electrode, 6 second electrode, 7 heterophototransistor (HPT), 8 thyristor, 9
Tunnel junction, 10 interconnect layer, 11 epitaxial film, 12 resistance deposited film, 13 third electrode, 14
... Fourth electrode, 15 ... Fifth electrode, 16 ... Sixth electrode, 17 ... Seventh electrode, 18 ... Eighth electrode, 19 ... Load resistance, 20 ... Constant voltage source.

Claims (2)

(57) [Claims] 1. An optical gate array for controlling two-dimensional output information based on two-dimensional input information of a first light, wherein a light detection unit whose electric output changes by irradiating the first light onto a semiconductor substrate; A light modulator having a function of changing the reflected light intensity of the second light by the electric output, including a multiple quantum well structure in the i-layer, and a pin structure including the multilayer reflection structure in the p-layer or the n-layer; An optical gate having a pair of electrodes stacked vertically in a substrate surface and arranged two-dimensionally and electrically connecting the photodetector and the light modulator in parallel. array. 2. The optical gate array according to claim 1, wherein
Connecting a load resistor and a constant voltage power source between the pair of electrodes;
An optical gate array wherein the load resistance is a resistive thin film formed on the same semiconductor substrate.