JPH04170515A - Drive circuit for liquid crystal panel - Google Patents

Abstract

PURPOSE:To obtain a drive circuit of a display panel which has a high general purpose property by making output number of a driver IC variable, and enabling drive, even if the number of terminal electrodes of panel differs from output number of the driver IC. CONSTITUTION:A terminal electrode 3 of a liquid crystal panel 2 is divided into a plural number of electrodes 4 in advance in accordance with bit number (m) of output of a driver IC 1, and driven by the driver IC 1 whose number is the same as that of the electrodes 4. In this case, a driver IC 1' which is provided with the number (n) of output pin which is larger than the number (m) of output pin of the driver IC 1 can be mounted, and the driver IC 1' allows that output timing of shift data is changed by a signal from the outside after (m) clock. Consequently, it is possible to drive a drive circuit of the liquid crystal panel by using the same drive circuit, even if the number of output bit of the driver IC is larger than the number of circuits of divided electrodes.

Description

[Detailed Description of the Invention] [Summary] Regarding a liquid crystal panel drive circuit that drives the liquid crystal panel by sharing the terminal electrodes of the liquid crystal panel with a plurality of driver ICs, the number of output bits of the driver IC is equal to the number of circuits in the divided electrode group. The purpose is to make it possible to drive the LCD panel drive circuit using the same drive circuit even if the number of terminal electrodes on the LCD panel is divided into multiple electrode groups according to the number of output bits of the driver IC (m). A driver IC having a number of output bins n greater than the number m of output pins of the driver IC can be attached to a drive circuit of a matrix type liquid crystal display panel which is divided and has the same number of driver ICs as the number of electrode groups. In addition, this driver IC is configured so that the output timing of shift data can be changed after m clocks by an external signal.

[Industrial Application Field] The present invention relates to a liquid crystal panel drive circuit, and more particularly to a liquid crystal panel drive circuit in which a plurality of driver ICs share terminal electrodes of the liquid crystal panel to drive the liquid crystal panel.

In recent years, TFT-type color liquid crystal display devices with excellent image quality have been commercialized, and in the future, multi-color display devices (8 or 16 color display) compatible with large-sized and large display capacity computers, and full-color color liquid crystal display devices for television display. is desired. Therefore, as the drive circuit, a low-cost STN type liquid crystal driver IC is used for multi-color display, and a high-performance analog driver IC is used for full-color display. However, driver I for multicolor display
Since the number of output bits differs between C and a full-color display driver IC, it is necessary to prepare a liquid crystal panel having terminal electrodes corresponding to each IC, and it is desired that they be made common.

[Conventional technology]

In recent years, liquid crystal display panels have become larger, and liquid crystal display panels with approximately 640 and 480 data signal input terminals and scan signal input terminals, respectively, have been put into practical use.

As liquid crystal display panels become larger in size, it is no longer possible to provide data signal input terminals or scan signal input terminals with one driver IC, and multiple driver ICs are used to support data signal input terminals and scan signal input terminals. Currently, the scan signal input terminals are shared and driven.

FIG. 6A shows the configuration of a conventional 162-bit shift register 61, and FIG. 6B shows the internal configuration of a conventional analog driver IC 60. The shift register 61 is composed of 162 flip-flops FF, the shift data input signal Sl is input to the D terminal, the clock signal CLK is input to the CLK terminal, and the Q terminal is the D terminal of the next stage flip-flop FF. It is designed to be connected to. The shift data input to the D terminal is output to the next stage flip-flop FF every clock signal CLK, and is also output to the outside by signals Q, ~Q16.
Output as 2.

On the other hand, the analog driver IC 60 receives a clock signal C.
A shift register 61 configured as shown in FIG. 6A that shifts the shift data input signal SI in accordance with LK, and R(
A data line 62 for transmitting data of the three primary colors of red), G (green), and B (blue), a sampling switch 63 turned on and off by a signal from a shift register 61, a sample hold circuit 64, and a buffer 65 are provided. ing. After passing through the shift register 61, the shift data input signal SI becomes a shift data output signal SO, which becomes the shift data input signal Sl of the analog driver IC 60 at the next stage. It is convenient for the number of output bits of the analog driver IC60 to be a multiple of 3, so currently analog driver ICs with the number of output bits of 162 are used.
60 mag is in practical use.

For example, 640x3 (RGB)x as shown in Figure 7.
The 480-dot full-color liquid crystal display panel 70 has mold on the scanning electrode side.7) Four drivers I with a total number of 120
C71, and the data electrode side is driven by analog drivers I and C60 for odd-numbered data electrodes, six each arranged on the top and bottom of the panel 70, and an analog driver IC60 for even-numbered data electrodes. ing. At this time, an analog driver IC 60 with an output pin number of 162 is used, but the first and last analog driver IC 60 do not use all the output bits, but only 156 of them to calculate the total number. I try to match it.

Figure 8 shows the analog driver I arranged as shown in Figure 7.
It shows the conventional connection of C60. The input terminal and output terminal of the shift data signal of the six analog driver ICs 60 are connected in cascade, and the first analog driver IC 60 is connected to the liquid crystal panel 90 from the seven output bits, and the output bit of the last analog driver IC 60 is connected to the liquid crystal panel 90. The end of the 156th line is connected to the liquid crystal panel 90. Each analog driver IC 60 receives a clock signal CL.
K is now input.

On the other hand, 640X3 (RGB) x 4 as shown in Figure 9
The 80-dot multicolor liquid crystal display panel 90 is driven by four driver ICs 91 with an output bit count of 120 on the scanning electrode side, but on the data electrode side, the panel 90
The number of output bits placed 6 each above and below is 1.
It is driven by 60 digital driver ICs 92. Since the ROB data is input to the digital driver 1c92 as serial data, the number of output bits does not need to be a multiple of 30, and the digital driver IC
The number of output bits of 92 may be a divisor of 480. The number of output bits of currently available driver ICs for STN liquid crystal display panels is 160 bits when data is 4/8 bits manually. Such a digital driver IC92
As shown in Fig. 10, six are connected in cascade, and the RGB data is sent as serial data to the first IC92.
It is now entered into

[Problems to be Solved by the Invention] However, when driving a panel with, for example, 640xRC, Bx480 pixels, the number of output bits of the digital driver IC is 160 bits (4/8 bit data input), and the number of output bits of the analog driver IC is 160 bits (data 4/8 bit input). is 81/162
With bits (27xRGB, 54XR(1,B)), there was a problem that the number of panel electrode terminals had to be changed depending on whether a 160-bit IC was used or a 162-bit IC.

It is an object of the present invention to solve the problems of the conventional liquid crystal panel drive circuit, and to provide driver ICs with different numbers of output bits.
To provide a driving circuit for a liquid crystal panel, in which one circuit can be used in common without having to prepare separate driving circuits even when a liquid crystal panel is used.

[Means to solve the problem]

The configuration of a driving circuit for a liquid crystal panel according to the present invention that achieves the above object is shown in FIG. In the figure, the terminal electrodes 3 of the liquid crystal panel 2 are divided in advance into a plurality of electrode groups 4 according to the number m of output focuses of the driver ICIs, and are driven by the same number of driver ICIs as the number of electrode groups 4. It has become. In such a drive circuit for a liquid crystal panel,
In the present invention, it is possible to install a driver IC1'' having a number n of output bins greater than the number m of output bins of the driver ICI, and this driver ICI' can change the output timing of shift data by m clocks by an external signal. The feature is that it can be changed later.

[Effect]

According to the liquid crystal panel drive circuit of the present invention, the driver IC
When the output focus number of matches the number m of terminal electrodes in the electrode group of the liquid crystal panel, which is divided into a plurality of electrode groups in advance, the output bits of the driver IC can be changed without using the auxiliary terminal (
Attach to the LCD panel. On the other hand, when the number of output bits of the driver IC is n, which is more than the number of terminal electrodes in the electrode group of the liquid crystal panel that is divided into a plurality of electrode groups in advance, the surplus output bits of the driver IC are Connect to an auxiliary terminal with an open end. Then, by adjusting the input/output terminals of the shift register inside each driver IC, selecting the output terminal, bypassing a predetermined shift register, etc., the shift data is output after m clocks from the shift register into which the shift data has been input. If you adjust it so that
The driver IC functions similarly to a driver IC with an output bit number of m.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 2 shows the structure of an embodiment of a shift register 20 built into a driver IC used in a driving circuit for a liquid crystal panel according to the present invention. Shift register 2 in this example
0 is provided with 162 flip-flops 21, the Q terminal of the first stage flip-flop 21a and the D terminal of the second stage flip-flop 21b are connected via a changeover switch 22, and each of the other flip-flops 21 is The Q terminal was connected to the D terminal of the next stage flip-flop 21. Further, the shift data input signal SI2 is input to the other terminal of the changeover switch 22, and the shift data input signal SII is input to the D terminal of the first stage flip-flop 21a. Furthermore, in this embodiment, the final stage (1
The shift data signal 30162 is output from the 62nd flip-flop 21, and the shift data signal 5 is output from the flip-flop 21 one stage before the final stage.
0161 is also output. Note that a clock signal CLK is input to the CLK terminal of each flip-flop 21, and the aforementioned changeover switch 22 is switched by an external changeover signal H/L to switch the second stage flip-flop.
The output terminal Q of the first stage flip-flop 21a or shift data SI2 from the outside is inputted to the D terminal of the amplifier 21b by the changeover switch 22. For example, this changeover switch 22 connects the output terminal Q of the flip-flop 21a to the D terminal of the second-stage flip-flop 21b when the changeover signal is H.

The shift data input to the D terminal of each flip-flop 21 is output to the next stage flip-flop 21 for each clock signal CLK, and the shift data is outputted to the next stage flip-flop 21 at every clock signal CLK.
-Q + hz. It is assumed that the liquid crystal panel (not shown) used in this embodiment has data-side terminal electrodes divided into electrode groups of 160 in advance in correspondence with a driver IC with an output focus number of 160 bits. It is assumed that an auxiliary terminal with the other end open is provided beside each electrode group so that a driver IC with an output bit number of more than 160 bits can also be attached.

FIG. 3 shows the configuration of an analog driver IC 30 using the shift register 20 configured as described above. This analog driver IC 30 includes, in addition to the shift register 20 configured as described above and which shifts the shift data input signal SI in accordance with the clock signal CLK, the R(
A data line 31 for transmitting data of three primary colors (red), G (green), and B (blue), a sampling switch 32 that is turned on and off by a signal from a shift register 20, a sample hold circuit 33, and a buffer 34 are provided. ing.

Then, when the switching signal is set to high level "H" and the shift data input signal 311 is input, the input shift data signal passes through the shift register 2o, and after 161 clocks becomes the shift data output signal 5016e, which is output to the analog driver. The signal is output from the IC 30, and after 162 clocks, it becomes the shift data output signal 5O162 and is output from the analog driver IC 30. Therefore, in this case, the number of output bits of the driver c30 can be set to 162 bits. Further, when the switching signal is set to L and the shift data input signal SI2 is input, the input shift data signal passes through the shift register 20 and becomes the shift data output signal 5O161 after 160 clocks and is output from the analog driver IC30. After the clock, it becomes the shift data output signal 5O162 and outputs the analog driver IC.
30 is output.

Therefore, in this case, the number of output bits of the driver IC 30 can be set to 160 bits.

Figure 4 shows the analog driver IC shown in Figure 3 with an output bit count of 160 bits, and one terminal electrode on the data side.
640X3 (RG
B) This shows an embodiment in which a drive circuit for a color liquid crystal display panel 40 of X480 dots is configured.

In this embodiment, the scan electrode side is driven by four driver ICs 41 with an output bit count of 120, and the data electrode side is driven by an analog driver IC 30 for odd-numbered data electrodes, six of which are arranged at the top and bottom of the panel 40. and an analog driver IC 30 for even-numbered data electrodes. That is, in this embodiment, the data side driver IC
30 is divided into data lines for odd-numbered lines and for even-numbered lines, and the data lines for odd-numbered lines are arranged above the liquid crystal panel 40 and the data lines for even-numbered lines are arranged below the liquid crystal panel 40. Then, as mentioned above, the 162-bit output driver IC3
The 0 output bits 2 to 161 bits are connected to the liquid crystal display panel terminal electrode, and the 1,162nd bit of each IC 30 is connected to an auxiliary terminal whose other end is open so that it is not connected to the panel.

In this circuit configuration, 12 data driver ICs
21 is divided into odd and even numbers, the clock signal CLKodd input to the upper driver TC30 and the clock signal CLK input to the lower driver IC30,
v, . . . may be obtained by dividing the clock signal CLK explained in FIG. 2 by two and delaying one of the clock signals by the clock signal CLK. The driver ICs 30 arranged above and below connect the shift data output terminal 5O161 to the shift data input terminal 312 of the next stage, and input the shift data signal SI to the shift data input terminal SI2 of the first stage. ,,, SI. 9
．． Make sure to input 7. Note that the switching signal H/L is set to a low level "L" in this case.

By connecting each driver IC 30 as shown in FIG. 4, each driver IC 30 with an output bit number of 162 has 16
It is possible to perform an operation equivalent to that of cascade-connected drivers with 0-bit output. Therefore, both a driver IC with an output bit number of 162 bits and a driver IC with an output bit of 160 bits can be connected in the same way to the liquid crystal panel drive circuit of this embodiment, and a liquid crystal panel with two types of terminal electrodes can be connected in the same way. There is no need to create one.

5A and 5B show the structure of an embodiment other than the shift register 20 shown in FIG. 2. In FIG. The shift register 50A in FIG. 5A is provided with 162 flip-flops 51, and the outputs SOI to SO4 of the 159th to 162nd stage flip-flops 51 are input to a multiplexer circuit 52, and output according to selection signals A and B. SOI
Select one of SO4 from the shift register 50A
It is now possible to output it as the output SO. As a result, the driver IC using this shift register 50A can vary the number of output bits within the range of 159 to 162.

The shift register 50B in FIG. 5B includes a circuit 54 for bypassing the first stage flip-flop 53a, and
This can be connected and separated by switches 55 and 56, and flip-flops 53y and 5 at the final stage and one stage before it.
3z is provided with an output changeover switch 57. The changeover switches 55, 56, and 57 output the changeover signal H/L.
For example, high level “H”
When the signal is input, the bypass circuit 54 is disconnected and the output of the flip-flop 53z is sent to the shift register 50.
When a low level "L" signal is input, the flip-flop 53a is disconnected and the bypass circuit 54 is connected, and the flip-flop 53a is
The output of 3y is outputted as the output SO of the shift register 50B.

As a result, when the switching signal H/L is at high level "H",
The shift data Sl is input to the flip-flop 53a, sequentially shifted by the clock signal, and outputted as the output of the flip-flop 53z after 162 clocks.
When the switching signal H/L is at low level "L", the shift data SI is input to the flip-flop 53b, sequentially shifted by the clock signal, and outputted as the output of the flip-flop 53y after 160 clocks. Therefore, the Drino IC using this shift register 50B can vary the number of output bits between 160 and 162.

Therefore, the drive circuit for the liquid crystal panel of the present invention can be constructed even by using the shift registers 50A and 50B shown in FIGS. 5A and 5B.

〔Effect of the invention〕

As explained above, according to the present invention, since the number of outputs of the driver IC can be varied, driving is possible even if the number of terminal electrodes of the panel is different from the number of outputs of the driver IC, and a highly versatile display panel can be realized. drive circuit can be realized.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of a driving circuit for a liquid crystal panel according to the present invention, FIG. 2 is a circuit diagram of an embodiment of a shift register used in a driving circuit for a liquid crystal panel according to the present invention, and FIG. 4 is a diagram showing the configuration of a driver IC of the present invention using the driver IC of FIG. 3, and FIG. 5A is a diagram showing the configuration of a driver IC using the shift register of FIG. 2. FIG. 5B is a circuit diagram of yet another embodiment of the shift register of FIG. 2; FIG. 6A is a circuit diagram showing the configuration of a conventional 162-bit shift register; FIG. 6B is a circuit diagram of another embodiment of the shift register; Figure 7 is a diagram showing the circuit configuration of a conventional analog driver IC. Figure 7 is a diagram showing the circuit configuration for driving a conventional full-color display. Figure 8 is a partial circuit diagram showing the connection of the analog driver IC. Figure 9 is a conventional diagram. FIG. 10 is a partial circuit diagram showing the connection of a digital driver IC. 20...Shift register, 21, 21a, 21b...Flip-flop, 22
...Selector switch, 30...Driver IC1 40...Liquid crystal panel, 41...Driver IC1 50A, 50B...Shift register, 51, 53a
, 53b, 53y, 53z--Flip-flop, 54... Bypass circuit, 55.56.57... Changeover switch, CLK... Clock pulse CLKo,... Odd line clock signal, CL
K,,,ゎ...Even line clock signal, S T
+~ST1g...Start pulse, S! ...Shift data input terminal (signal), SO...Shift data output terminal (signal). External signals Fig. 1: A block diagram of another embodiment of the present invention Fig. 5A: A block diagram of another embodiment of the present invention Fig. 5B: Conventional 162-bit noft reno star composition

Claims (1)

[Claims] 1. The terminal electrodes (3) of the liquid crystal panel (2) are arranged in advance in a plurality of electrode groups (4) according to the number m of output bits of the driver IC (1).
) and is equipped with the same number of driver ICs (1) as the number of electrode groups (4), in which the number of output pins n is greater than the number of output pins m of the driver ICs (1). This driver IC (1') is characterized in that it can be equipped with a driver IC (1') equipped with a driver IC (1'), and that the output timing of shift data can be changed after m clocks by an external signal. LCD panel drive circuit. 2. The shift register built in the driver IC (1') is provided with a plurality of shift data signal input positions and a plurality of shift data signal output positions, and by selecting the input position and output position of the shift data signal, the driver 2. The liquid crystal panel driving circuit according to claim 1, wherein the output timing of the shift data of the IC (1') can be changed after m clocks. 3. By providing a plurality of shift data signal output positions in the shift register built in the driver IC (1') and selecting the plurality of shift data signal outputs via a multiplexer, the driver IC (1') )
2. The liquid crystal panel driving circuit according to claim 1, wherein the output timing of the shift data can be changed after m clocks. 4. The shift register built into the driver IC (1') is provided with a circuit that bypasses a predetermined shift register using a changeover switch, and the shift data signal input position and shift data signal output position are switched by an external switching signal. 2. The liquid crystal panel driving circuit according to claim 1, wherein the output timing of the shift data of the driver IC (1') can be changed after m clocks.