JPH04170240A - Communication control system - Google Patents

Abstract

PURPOSE:To reduce the processing time of the entire reception processing by starting a DMA control means and selecting a reception address or an address from an address counter in response to a format of transmission information. CONSTITUTION:Since an output of AND gates 16,18 receiving a signal MULTI at its terminal is inputted to a bus driver 13 and an address counter 12, the bus driver 13 is active in the case of plural-word communication only, an address of the address counter 12 is fed to an address terminal of a memory 10 and the address counter 12 is counted up only in this case. On the other hand, since an output of an AND gate 17 receiving a signal BD and a signal SINGL is received to a bus driver 14, the bus driver 14 is active in the case of single word communication only and an address of an address register 8 is fed to an address terminal of the memory 10.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a system in which data processing devices are connected by a communication line such as an optical cable, and particularly relates to a communication format and communication on the receiving side according to the format. Regarding control.

(b) Conventional technology Generally, in order to communicate data via a communication line, the communication control device on the receiving side is equipped with a DMA controller and a dedicated register for storing the start address, data size, etc. necessary for reception. , Prior to reception, first set the start address, data size, etc. in the above dedicated register,
After setting, it notifies the sending side that it is ready to receive, and then performs the prescribed procedure of activating the DMA controller, and then actually receives the continuously transmitted data. .

(c) Problems to be Solved by the Invention Conventional methods are effective when communicating large amounts of data between devices, but they require a long time to carry out predetermined procedures before receiving data. It was unsuitable for reception. Therefore, the present invention adds a new method that simplifies the pre-reception procedure to the conventional method suitable for large amounts of data that requires a predetermined procedure before reception, thereby shortening the processing time of the entire reception process. The purpose is to

(d) Means for Solving the Problems The present invention provides a system for communicating information via a communication line, in which an identification bit is added to the transmitted information to identify whether the transmitted information is an address or data. Tenaru I
Word information is used as a communication unit, and when transmitting data of a predetermined number of words, the transmission information is configured in a format that includes an address in the first word, and data of more words than the predetermined number of words is transmitted. When transmitting information, the transmitted information is composed only of data, and the communication control device on the receiving side includes a receiver for receiving the transmitted information via the communication line, a memory for storing the received data, and a memory for storing the received data. DMA control means for controlling writing of received data; and an address is set prior to data transmission of words greater than the predetermined number of words;
an address counter whose contents are updated according to a clock signal from the MA control means; and an address counter that detects the identification bit of the received information and controls activation of the DMA control means according to the detection result; The above problem is solved by providing a control means for selectively supplying addresses from the address counter to the memory.

(E) Effect In the present invention, depending on the format of the transmission information, the DMA
Since the activation of the control means and the selection of the reception address and the address from the address counter are performed, data communication of more words than a predetermined number of words is performed using the same procedures and processing as before. The received data can be stored in the memory, and in data communication of a predetermined number of words, the received data can be automatically stored in the memory without performing any predetermined procedures before reception.

(F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention.
1) is a communication line made of an optical cable, and (2) is a communication control device on the subunit side that receives information transmitted from a communication control device (not shown) on the host unit side via the communication line (1). It is. This subunit is, for example,
In addition to the communication control device (2), it includes an I10 processor for adding a plurality of terminal devices.

In Fig. 1, (3) is a CPU for communication control, (4) and (5) are an address bus and a data bus, and (6) is a serial-to-parallel conversion @ (7) that is connected via communication port M (1). a receiver for receiving the transmitted information; (8) and (9) an address register and a data register for respectively capturing the address and data received by the receiver; (10)
is a memory connected to the address bus (4) and data bus (5) to store received data, (11) is a DMA controller that controls writing of received data to memory (10), and (12) is a DMA controller. In the DMA operation according to (11), an address counter for specifying the address of memory (10), (13) (14) (
15) (22) are inserted into the address bus and data bus and are used as a DMA controller (11) or an AND gate (1
6) A bus driver whose opening/closing is controlled by the output of (17), and (18) is an AND gate.

Further, (19) controls the loading of information into the address register (8) and data register (9) according to the signal from the receiver (6), and also controls the DMA controller (19).
1) Startup control, bus driver (13) (1,,4)
(20) is a DMA receiving controller that controls the opening and closing of
DMA operation by controller (11) and CPU (3
), and (21) is an address decoder that decodes the address on the address bus (4) and determines that the CPU access is to the memory (10).

Here, the wait controller (20) and address counter (12) will be explained in detail.

The wait controller (20) receives a DMA request signal DMARQ from the DMA controller (11),
an address strobe signal AS from the CPU (3);
The decode output of the address decoder (21) is input, and when the CPU (3) accesses the memory (10), if the DMARQ is not input, the CPU (3) can access the memory (10) without waiting. A data ACK signal DTACK is returned to the CPU at the appropriate timing.

Also, when making a DMA request, the CPU (3) uses the memory (3
), the wait signal WAIT is not generated, and therefore the DMA controller (11) can immediately start DMA.

However, the CPU (3) and DMA controller (11)
), and for this reason, the wait controller (20) inputs the signal DT after inputting the signal AS.
If DMARQ is input before ACK is returned to the CPU, the timing of returning DTACK is delayed to put a wait on the CPU, and the DMA operation is performed during this time. Furthermore, when DMARQ is input after returning DTACK after inputting the signal AS, the signal W is sent to the DMA controller (11) until the CPU finishes accessing the memory (io).
Control is performed so that AIT is issued and DMA access is made to wait.

In addition, the address counter (12) has a start address set before data transmission, and counts up in response to the clock signal MCLOCK from the AND gate (18), and ends when the contents of the counter go from all I's to all O's. Outputs the signal END, and this signal causes the CPU to
(3) The end of DMA is notified by an interrupt.

In other words, it serves as both a general address counter and a size counter, and these two counters may be used instead of the address counter (12).

Next, the communication format in this embodiment will be explained based on FIG.

In this embodiment, as shown in FIG. 2(a), an identification bit A/D for identifying whether the transmitted information is an address or data is added to the transmitted information consisting of an address or data. Word information is used as a communication unit.

When transmitting single word data, see Figure 2 (
As shown in b), the transmission information is configured in a format that includes an address word at the beginning of the data word to be transmitted, and when transmitting multiple words of data, the format shown in Fig. 2 (
As shown in C), the format is defined so that transmission information consists of only data.

The operation of this embodiment will be described in detail below with reference to FIGS. 3 and 4.

Here, in order to clarify the operation of this embodiment, we will explain it in Fig. 2 (
An example will be described in which the single word communication shown in FIG. 2 (1) is performed during and after the multi-word communication in the format shown in c).

That is, in FIG. 3, the information indicated by diagonal lines is the information to be transmitted by multi-word communication, and the information in pairs indicated by "(" is the information to be transmitted by single-word communication.First, prior to transmission,
When multi-word communication is started after the start address is set in the address counter (12), the transmitted one-word information is sequentially transmitted to the receiver (1) via the communication line (1).
6). The receiver (6) converts one word of information received serially into parallel information using a serial-to-parallel conversion circuit (7) and outputs it.
9).

The reception controller (19) receives the identification bit A/D which is the output of the receiver (6), as shown in FIG.
is input to the D terminal and the strobe signal STB is input to the CL terminal, a D flip-flop (30), an AND gate (31) that inputs the inverted Q output of the D flip-flop (30) and the strobe signal STB, and a D flip-flop. (
A that inputs the Q output of 30) and the strobe signal STB.
It consists of an ND gate (32), a D flip-flop (33) which inputs the inverted Q output of the D flip-flop (30) to the D terminal, and inputs the strobe signal STB to the CL terminal.

Therefore, if the received information is an address, the identification bit A/
Since D is "O", the D flip-flop (30) is reset and the result is as shown in FIG.
If the signal ALAT is output from 1) and the received information is data, the identification bit A/D is "1", so the D flip-flop (30) is set and the AND is performed as shown in FIG. 3 (1). A signal DLAT is output from the gate (32). Therefore, the address received by the receiver (6) is latched into the address register (8), and the received data is latched into the data register (9). Furthermore, the signal DLAT beam, M
The activation signal DMAGO is sent to the A controller (1), so every time data is latched, the DMA controller (1) is activated.
11) will be activated.

Also, the inverted Q output of the D flip-flop (30) is "1"
When the signal STB is input after , the D flip-flop (33) is set and as shown in Fig. 3 (e),
The signal 5INGL changes from "0" to r for one period of the signal STB.1. J, as shown in Figure 3 (force), the signal MU
LTI changes from [1] to "0". In other words, signal 5IN
GL indicates that the communication format is single word, and signal MULTI indicates that the communication format is multiple words.

When the DMA controller (11) is activated by the signal DMAGO, the DMA controller (12)
A request signal r) M A RQ is output to the weight controller (20). Weight controller (20
) performs arbitration with CPU access as described above, and DM
When A is permitted, the DMA controller (11) sets the signal BD to "1" and sends the write signal WE to the memory (11).
). After writing the data, the DMA controller (13) issues one signal CLOCK to count up the address counter (19). Since the signal BD is directly input to the bus driver (15), the output of the data register (9) is connected to the data terminal of the memory (10) via the data bus (5). Also, signal BD
Since the inverted signal of I) is input to the bus driver 22,
During MA operation, the bus driver (22) closes and the memory (
10) and the CPU (3) are disconnected.

However, the clock signal and signal BD are not directly input to the bus driver (13) and address counter (12), but the output of the AND gate (16) (18) which inputs the signal MULT I to one end is input. , only when communicating multiple words, the bus driver (13) opens as shown in FIG. 3(g), and the address of the address counter (12) is supplied to the address terminal of the memory (10), and
Only in this case, the address counter (J2) is counted up.

Therefore, the data words in the multi-word transmission shown in words 1, 2, and 5 in FIG. 3 are sequentially stored in consecutive addresses from the start address of the memory (11).

On the other hand, the bus driver (14) has a signal BD and a signal 5.
Since the output of the AND gate (17) that inputs INGL is input, the bus driver (14) opens only during single word communication as shown in Figure 3 (ri), and the memory (10)
The address of the address register (8) is supplied to the address terminal of.

Therefore, the data words in the single word transmission shown in the 4th and 7th words in FIG. 3 are stored in the memory location of the memory (10) designated by the immediately previous address.

As described above, the address of either the address counter (12) or the address register (8) is selected depending on the communication format, and the received data is stored in the selected address position of the memory (10).

If the capacity of the memory (10) is large, send only the lower address, add an address generation circuit that generates the upper address to the receiving side, and use both addresses to address the memory. Good too.

By the way, in the above embodiment, DMA was performed by placing a wait on the CPU, but a general method of issuing a hold request to the CPU and executing DMA in response to a hold ACK from the CPU may also be used. In this case, the bus driver (22) is not required. Further, in the above embodiment, the predetermined number of words is one word, but this number of words may be set as appropriate depending on the system.

(g) Effects of the Invention According to the present invention, when communicating a large amount of data exceeding a predetermined number of words, the received data can be stored in the memory using the same procedure as in the past. In word-based data communication, procedures before reception can be simplified and high-speed data communication can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG.
3 is a diagram showing a communication format in the embodiment, FIG. 3 is a diagram showing a timing chart of each signal in the embodiment, and FIG. 4 is a circuit diagram showing a specific example of the reception controller in the embodiment. (1)...Communication line, (2)...Subunit side communication control device, (3)...CPU, (4)
...address bus, (5) ...data bus, (6) ...receiver, (8) ...address register, (9) ...data register , (10
)...Memory, (11)...DMA controller, (12)...Address counter, (13)
(14) (15)...Bus driver, (19)...
...Reception controller.

Claims (1)

[Claims] (1) In a system that communicates information via a communication line, the unit of communication is one word of information obtained by adding an identification bit to the transmitted information to identify whether the transmitted information is an address or data, When transmitting data with a predetermined number of words, the transmission information is configured in a format that includes an address in the first word, and when transmitting data with more words than the predetermined number of words, only the data is transmitted. A receiver that configures the information and receives the transmitted information via the communication line in the communication control device on the receiving side, a memory for storing the received data, and a DMA that controls writing of the received data to the memory. a control means, an address is set prior to data transmission of words greater than the predetermined number of words;
an address counter whose contents are updated in accordance with a clock signal from the control means; detecting the identification bit of the received information; and controlling activation of the DMA control means according to the detection result; A communication control system comprising: control means for selectively supplying addresses from an address counter to the memory.