JPH04169948A - Buffer storage system - Google Patents

Abstract

PURPOSE:To reduce the number of bus interface signals of a CPU by certainly outputting one of outputs of a buffer storage device (BS), an address array (AA) reference address, BS data, and AA data on a multiplex bus by a bus control means. CONSTITUTION:Output data of an AA 21 outputted onto the multiplex bus is closed by a bus control means (BUSC) 24; and if access from the CPU is read access, output data of a BS 22 is opened on the multiplex bus 201 by the bus control means 24. If the AA 21 is hit, BS data is fetched. If the access is write access, BS write data is outputted onto the multiplex bus 201 by the bus control means 24; and if the AA 21 is hit, buffer storage control to execute the rewrite operation of BS data is performed. Thus, the number of interface signals in a buffer storage system is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to buffer storage devices, address array addresses, data configuration and control in buffer storage systems, and particularly relates to a method for reducing bus interface signals. .

[Conventional technology]

In conventional computer systems, as a means to reduce the number of interface signals between the central processing unit, main memory, and various ■/○ controllers, there is a method of making the data bus a multiplex bus and using one bus as two buses. It has been done. When this method is applied to a buffer storage system, 1) a method of connecting the data line of the buffer storage device to a multiplex bus between the central processing unit and the main storage device;

2) A method of multiplexing the address lines and data lines of a buffer storage device.

3) How to make the address lines and data lines of the address array into a multiplex bus.

is possible.

[Problem to be solved by the invention]

The above conventional technology relates to multiplexing of system addresses and data, and even if it were applied to a buffer storage system, it would result in multiplexing of addresses and data of a buffer storage device and multiplexing of addresses and data of an address array. , multiplexing of data in the buffer storage device and data in the address array is not considered.

However, when a controller for a buffer storage device is built into a one-chip microprocessor, in addition to the data bus of the buffer storage device, the data bus of the address array may become the bottleneck of the BS as an interface signal.

An object of the present invention is to utilize the difference in data determination time between AA and BS when the access time of BS is slower than the access time of AA, and to store addresses and buffers in a buffer storage device and an address array without degrading performance. The objective is not only to multiplex the data of the device, but also to multiplex the data of the address array, thereby reducing the number of interface signals within the buffer storage system.

[Means to solve the problem]

In order to achieve the above purpose, the central processing unit (hereinafter referred to as CPU)
(hereinafter referred to as MS), a main memory (hereinafter referred to as MS), and a buffer storage device (hereinafter referred to as BS) that holds part of the data in the main memory.
In a computer system that has an address array (hereinafter referred to as AA) that maintains the correspondence between the main memory and the BS, the address line and data line of the BS and the AA
The address line and data line of the address line and data line are used as a multiplex bus.

Address holding means holds BS and AA addresses on the multiplex line, and AA data holding means holds data read from AA.

A bus control means is provided on the multiplex bus to control the output of reference addresses of the BS and AA, the output of BS data, and the output of AA data. The means outputs the reference addresses of the BS and AA on the multiplex bus to activate the BS and AA, and after the address is determined on the multiplex bus, the address is held by the address holding means (2) the bus control Close the BS and AA addresses output on the multiplex hash, and
(3) After the output data is determined, the output data of the AA is held by the AA data holding means. Close the data, if CP
If the access from U is a read access, the hash control means opens the BS output data on the multiplex hash, if AA is a hint, fetches the BS data, and if the access is a write access. , the bus control means outputs the BS write data onto the multiplex bus, and if AA is hit, the BS write data is output to the multiplex bus.
It performs buffer storage control that executes operations to rewrite data.

[Effect]

The outputs of the BS, AA reference addresses, BS data, and AA data on the multiplex bus are exclusively controlled by the bus control means so that only one is output without fail, so that no collision occurs.

Also, in the first phase, output the reference address of AA,
Because the read activation is applied to AA, AA's hit (
BS has reference data) There is no delay in the timing of judgment.

In general, the storage capacity of BS memory elements is larger than that of AA, and since BS data is fetched in the next cycle of AA hit determination, BS memory elements are used with slower access times than AA memory elements. There are many things. Therefore, if optimal timing design is performed, in the present invention, even if BS data is zenerd or BS data is rewritten in the next phase of AA data retention, BS access will not be delayed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a system configuration when AA and BS are connected by a multiplex bus, and FIG. 2 shows a system configuration when a multiplex bus is not used.

In Figures 1 and 2, 11.16 is the central processing unit (
CPU), 12, 17 are main memory (MS), 13
゜18 is address array (AA), 14. ．． 19 is a buffer storage device (BS), and the central processing unit has a built-in buffer storage controller. In FIG. 1, 15 is a latch gate that holds the addresses of AA and BS, and line 101 is a multiplex bus.

In Figure 1, the CPU 11 is MS12, AA13, B514.
The CPU II is connected by a multiplex bus 101, and there are 32 bus interface signal lines for the CPU II.

Partly, in FIG. 2, -CP, tJ16 is MS17. A.A.
18, is connected to B519 by a separate bus, and AA1
8. Requires a total of 92 bus interface signals: 14 for the address line 102 of B519, 14 for data line 103 of AA18, 32 for data line 104 of B519, and 32 for data line 105 of MS17. There are 60 more lines compared to the figure.

FIG. 3 is a diagram showing details of an embodiment of the present invention.

31 is an MS, 21 is an AA, 22 is a BS, 23 is a latch gate, 24 is a bus control circuit (BUSC) that controls the multiplex bus, and 25 is a write data register (WDR).
), 26 is address register (ADR), 27 is B52
2. Register (R
DR), 28 is a register (AAR) that holds data read from the AA 21, 29 is a comparator, 30 is a selector, and 32 is a bidirectional driver.

Here, AA21 and B522 are static RAMs with an out enable, line 201 is a multiplex bus (MBUS), 202 is an out enable signal (CPUOE) of the bidirectional driver 32, and 203 is a latch enable signal (ALE) of the latch 23. .

204 is the write enable signal (BSWE) of B522
, 205 is the B522 out enable signal (BSOE
).

206 is the write enable signal (AAWE) of AA21
, 207 is the out enable signal (AAOE) of AA21.
), 208 indicates a select signal of the selector 30.

The buffer storage controller is built into the CPU.
Bidirectional driver 32, selector 32, WDR25, AD
R26, RDR27, AAR28 registers, comparator 29. BUSC24 is included in the CPU.

Here, CPU0W202, A A OE 207, B
SO205 is normally disabled and M
BUS201 is in a high impedance state.

When a memory access request is received from the CPU, a read start signal (READ) or a write start signal (WRITE) is transmitted to the BUSC 24, and access is started in synchronization with the basic clock (CLK). Selector 30 is normally A
When the DR26 is selected and the CPU OE 202.1rLE203 becomes '1' in response to a memory access request, the bidirectional driver 32
Natres is sent pressure to 201, and A L at the next clock.
E 203 becomes 10', and the address is latched into the latch gate 23. AA21 and B522 are in normal read mode and start read access after the address is determined in MBUS201. When the address is latched to the latch gate 23, the CPU OE 202 is 'O'.
', AAOE207 is set to '1', the read data of AA21 is output to MBUS 201, and after the read data is determined, it is stored in AAR2g. Here, the AAR28 consists of a through-latch type FF, and after the read data of AA21 is determined in the M BUS 201, it is compared with the ADRZ6 by the comparator 29.
It is determined whether an address exists (hit) in 1. At this time, 1) If the CPTJ access is a read access.

After storing the data of AA21 in AAR28, set AAOE207 to 'O' by BUSC24, B S OE 2
MBL read data of B522 from 03 to '11
:5201, and if the result of the comparator 29 is a match (bit), a Hi T signal is reported to the CPU.

The read data of B522 is taken into RDR27,
If there is a mismatch, MS, which is a known technology,
31 and B522.

2) If the CPU access is a write access, switch the selector 30 to WDR25 by the select signal 208, set A A OE 207 to '0'', and then
The OE 202 is set to 11' and the data of the WDR 25 is sent from the bidirectional driver 32 to the M BUS 201. At this time, if the result of the preparator comparator 29 is a match (hint), the BSWE 204 becomes '1' and the B522
Write WDR25 data to.

4(A) and 4(B) are diagrams showing timing charts of the embodiment of the present invention, FIG. 4()\) is for REIT access, FIG. 4(B) is for write access, Along with AA
This shows the case where the hit is a hit.

In Figure 4 (A), when READ becomes '1', A
L E becomes 1, the address is output to MBυS, and on the next rising edge of CLK, ALE becomes rO+, and at the same time as the address is latched, AAOE is set to '1' and M
Switch the BUS power to AA data, start AA hit judgment, and start the next CLK! J Te A A OE'
O', B50E is set to '1', MBUS output is switched to BS data, AA is hint (HiT='1')
If so, the BS data is fetched at the next rising edge of the clock.

Similarly to Fig. 4(A), in No. 41m (B), after WRiTE becomes 11', the address and AA data are output to MBUS, and the write data is output to MBUS at the next rising edge of CLK. , if AA is hit (HiT=1)
If so, set BSWE to '1' and update the BS data.

4(A) and 4(B), the access is completed in 3 clocks, but even when the multiplex bus is not used, the BS data can be confirmed or the AA hit (HiT
) is not completed in two clocks, the access time will be the same.

〔Effect of the invention〕

According to the present invention, in the buffer storage system, when the buffer storage controller is built into the CPU and the BS and AA are used externally, the address and data buses of the AA and BS can be used in multiplex, so that the CPU bus interface signal When a one-chip microprocessor is used for the CPU, it has the effect of eliminating bin necks in LSi. It is possible to prevent a decline in performance.

[Brief explanation of drawings]

Figure 1 is a system configuration diagram in which AA and BS are connected via a multiplex bus, Figure 2 is a system configuration diagram in which AA and BS are connected without using a multiplex bus, and Figure 3 is a detailed diagram of an embodiment of the present invention. Figure 4 (A), Figure 4 (B)
) is a diagram showing a timing chart of an embodiment of the present invention. 11...CPU, 12.MS, 13-A
A, 14-BS, 15 latch gate, 1, 01... multiplex bus.

Claims (1)

[Scope of Claims] 1. A computer comprising a central processing unit and a main memory device, and having a buffer memory device that holds part of the data in the main memory device, and an address array that maintains the correspondence between the main memory device and the buffer memory device. In the system, the address line and data line of the buffer storage device and the address line and data line of the address array are used as a multiplex bus, and address holding means for holding the address of the buffer storage device and the address array; A data holding means for holding read data is provided, and in response to a read/write activation from the central processing unit to the buffer storage device, a reference address of the buffer storage device and the address array is outputted onto the multiplex bus, and when the address is After being determined, the reference address is held by the address holding means, the output of the reference address on the multiplex bus is closed, and the data output of the address array is opened, and after the output data of the address array is determined, the data is held. 1. A buffer storage system, wherein data in an address array is held by a means, and after closing the output of data in the address array, read and write access to a buffer storage device is executed.