JPH04168991A - Motor controller - Google Patents

Abstract

PURPOSE:To suppress abrupt changes in torque and output current by interrupting transmission of voltage vector data and zero vector data by a gate circuit when the output current of an inverter becomes a predetermined value or more. CONSTITUTION:When the output current of an inverter 2 becomes larger than a predetermined value, gate circuits 21-23 interrupt supply of first and second vector data from a memory 5 to a switch controller 4. Thus, the inverter 2 substantially stops, an output current is reduced, generation of an excess torque is prevented, and then transmission of the first and second vector data is started again through the gate circuits 21-23. Reading of voltage vector based on the counted value of a counter 6 is continued even during a current limiting period. Accordingly, the continuity of a rotary magnetic field vector in a motor 1 is held excellently. Thus, an excess torque due to abrupt change in speed or load can be prevented.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention is a method for controlling an inverter by writing a PWM (pulse width modulation) switching pattern (unit vector data) in advance in a memory and reading it out. The present invention relates to a device that controls the speed of an AC motor connected to an inverter.

BACKGROUND OF THE INVENTION The use of PWM controlled inverters to provide speed control of AC motors is known. It is also known that in order to perform PWM control, a PWM switching pattern is written in advance in a ROM so that an approximate sine wave can be obtained, and the inverter is controlled based on this. Furthermore, a method has already been proposed in which a three-phase inverter is not controlled independently of each phase, but all three phases are collectively controlled, a desired voltage vector is generated, and a desired rotating magnetic field is obtained.

In addition, feedback control is possible with a simple configuration,
A speed control system for a motor that is capable of ultra-low speed control is disclosed in Japanese Patent Application Laid-Open No. 62-207196.

[Problems to be Solved by the Invention] By the way, in the motor control system disclosed in the above publication, when a command to suddenly increase the speed is given or when the load suddenly increases, the inverter control device instantly increases the maximum voltage. , the motor will operate to generate the maximum frequency, an excessive current will flow through the motor, and the largest possible torque will be generated. As a result, mechanical damage may be caused to the motor shaft and the load connected to the motor. Furthermore, it is necessary to set the capacitance of the switching elements of the inverter to be large.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a motor control device that can suppress sudden changes in torque and output current.

[Means for Solving the Problems] To achieve the above object, the present invention is connected to an AC motor to be controlled, and operates on and off in a predetermined switching pattern to generate a voltage vector and a zero vector. an inverter having a plurality of switching elements;
turning on and off the switch to obtain the voltage vector or the combination of the voltage vector and the zero vector in a predetermined order;
a memory in which first vector data indicating an off pattern and zero vector data indicating an on/off pattern of the switching element for obtaining the second vector are written; a switching element control circuit for operating the switching element based on the first vector data and the second vector data; a reference signal generation circuit for generating a reference signal indicating a target speed of the motor; A comparator circuit that generates a difference signal corresponding to the difference between the detection signal and the detection signal indicating the speed of the motor; and a triangular wave generation circuit that generates a triangular wave of a predetermined frequency; a second vector period determination comparator that controls the memory to read the second vector data from the memory during the period when the signal crosses; and a clock pulse having a frequency higher than the frequency of the triangular wave. a counter that is incremented by the clock pulse and specifies an address for reading the first vector data and the second vector data from the memory in a predetermined order;
connected between the clock generator and the counter;
and a counter input control gate that blocks passage of the clock pulse in response to a signal indicating selection of the second vector data obtained from the second vector period determination comparator. In the device,
a current detector for detecting the output current of the inverter; a reference voltage source for providing a reference voltage for detecting that the output current of the inverter has exceeded a predetermined value; and current detection obtained from the current detector. a current detection comparator that compares a voltage with the reference voltage; and a current detection comparator connected between the memory and the switch control circuit, and when the current detection voltage becomes larger than the reference voltage, the current detection comparator The present invention relates to a motor control device that is provided with a gate circuit that interrupts transmission of the voltage vector data and the zero vector data in response to an output obtained from the motor controller.

[Operation] The gate circuit according to the present invention interrupts supply of the first vector data and the second vector data from the memory to the switch control circuit when the output current of the inverter becomes larger than a predetermined value. As a result, the inverter is brought to a substantially stopped state, the output current is reduced, and excessive torque is prevented from being generated. Thereafter, transmission of the first vector data and second vector data through the gate circuit starts again. Reading of the voltage vector based on the counter continues during the current limit period. Therefore, the continuity of the rotating magnetic field vector in the motor is maintained well.

[Embodiment] Next, a three-phase motor speed control device according to an embodiment of the present invention will be described. In FIG. 1, a motor 1 consisting of a three-phase induction motor is equipped with a three-phase inverter 2 capable of PWM control.
is connected. The inverter 2 includes a DC power supply 3 and switch elements AI, A2, Bl, and B2 each consisting of transistors.
, CI, and C2 are bridge-connected. The six switching elements Al-C2 are connected to the switching element control circuit 4.
It operates on and off in response to a control signal supplied from the controller. Note that the three switch elements AI on the upper side of the inverter 2
, Bl, CL and the lower three switch elements A2, B
2 and C2 operate in reverse to each other, so if one control is specified, the control of the entire inverter is specified. Here, the inverter control state is specified by the first, second, and third signals A, B, and C read from the ROM (read-only memory) 5, and the signals A, B, and C are at high level, that is, logic "1". When the switching elements At, Bl, and C1 are on, when the logic is low, that is, the logic is "0°, the switching elements AI,
Bl and CI are turned off.

ROM5 is PWM for controlling inverter 2 by PWM.
A switching pattern (unit vector data) is written in advance. The ROM 5 includes a forward PWM pattern memory M1, a forward zero vector memory M2, a reverse PWM pattern memory M3, and a reverse zero vector memory M4. Each of the memories M1 to M4 has 512 addresses from O to 511, and is addressed by the value of the 9-bit binary column 6a of the up/down counter 6, respectively. However, one of the four memories M1-M4 is selected, and only the output of this selected memory is effectively used for controlling the inverter 2. In order to make this selection, the ROM 5 has a zero vector selection control signal input terminal 7.
and a forward/reverse rotation selection control signal input terminal 8. When the zero vector selection control signal input terminal 7 is at logic "0", one of the memories M1 and M3 is selected, and the logic is "1".
”, one of the memories M2 and M4 is selected. Also, the forward rotation/reverse rotation selection control signal input terminal 8 is
In the case of "1", one of the memories M1 and M2 is selected, and in the case of "1", one of the memories M3 and M4 is selected.

Now, if the 9 bits of line 6a are represented by BO to B8, the input bit of input terminal 7 is represented by 810, and the input bit of input terminal 8 is represented by B9, the address is specified by the 9 bits of BO to B8. Ru. Also, B9, BIO is [0
0], the first memory M1 (forward PWM switching pattern) is selected, and when the value is [01], the second memory M1 is selected.
2 (zero vector for forward rotation) is selected, the third memory M8 (reverse PWM switching pattern) is selected at [10], and the fourth memory M4 is selected at [11].
(Zero vector for reversal) is selected.

In order to control the output voltage of the inverter 2 by controlling the ROM 5 and the counter 6, a speed detector 9 consisting of a speed generator is coupled to the motor 1, and this output line 9a is connected to a comparison circuit 10.

For this reason, the comparator circuit 10 compares the speed detection signal consisting of a DC level with a reference signal corresponding to a desired rotational speed given from the reference signal line 11, and outputs a difference signal. The difference signal obtained from the comparison circuit 10 is sent to the proportional integration circuit 1.
2 is entered. Output line 13 of proportional-integral circuit 12
The difference signal Vd is input to the first comparator 14 for determining whether the difference signal Vd is positive or negative, and
The signal passes through the absolute value circuit 15 and is input to the second comparator 16 for determining the zero vector period.

The output terminal of the forward/reverse judgment comparator 14 is connected to the up/down input terminal U/D of the counter 6, and is connected to the RO
It is connected to the forward/reverse rotation selection signal input terminal 8 of M5.

17 is a clock oscillator (OS C), and 20 to 5
Generates a clock/curse around 0kHz.

The output terminal of this oscillator 17 is connected to one input terminal of an AND gate 18, and the output terminal of this AND gate 18 is connected to the clock input terminal CL of the counter 6. The output of the oscillator 17 is input to the counter 6 as a clock pulse only when the input terminal is at a high level.

A triangular wave generator 19 is connected to the non-inverting input terminal of the zero vector period determination comparator 16. Triangular wave generator 19
For example, 5kHz is lower than the output frequency of the oscillator 17.
A triangular wave voltage Vc (carrier) is generated at z, and this V
A comparator 16 compares c with the absolute value of the difference signal Vd.

The output terminal of the zero vector period determination comparator 16 is connected to the input terminal of the AND gate 18 via the NOT circuit 20, and is also connected to the zero vector selection control signal input terminal 7 of the ROM 5.

The three-phase output line of ROM5 is AND gate 2, 22.2
3 to a switching element control circuit 4. AND gates 2, 22, 23 interrupt the transmission of voltage vectors and zero vectors when the inverter output current becomes excessive.

In order to perform this current control, current detectors 24, 25, and 26 are provided on the output line of the inverter 2, and a three-phase rectifying and smoothing circuit 27 is connected to these. A third comparator 28 for current detection having hysteresis characteristics includes an operational amplifier 29, one input terminal of the operational amplifier 29, and a rectifying and smoothing circuit 27.
a resistor R1 connected between the other input terminal and the reference voltage source 30, a feedback resistor R8 connected between the output terminal and the right end of the resistor R2, and a resistor R2 connected between the other input terminal and the reference voltage source 30; It consists of a capacitor C1, the output terminal of which is connected to an AND gate 2, 22.23.

[ROM Contents] Data is written in the ROM 5 as shown in principle in FIG. That is, each memory M1-M4 of the ROM 5 has addresses O to 511, and the normal pwM pattern memory M1
For example, data of voltage vectors (first vectors) VB, V2, VB, V2 are sequentially written to addresses O to 3 of the zero vector memory M2 for normal rotation.
has zero vector (second vector) v7, vO1v7,
The vO data is written in order, and the reverse PWM/(addresses 0 to 3 of the turn memory M3 have the voltage vector V1,
Data of 5, vl, v5 are written in order, and zero vectors 0, V7, VO,
The data of V7 is written in order. Vector data is also written to the remaining addresses 4 to 511 using the same principle as addresses O to 3. Since the vector data of each address in FIG. 2 shows the principle, it differs from actual data. Now, the actual voltage vector data of addresses 0 to 84 (corresponding to the 06 to 60 @ interval) of the normal rotation PWM pattern memory Ml are shown as follows: VB , VB , VB , VB , Vl ,
Vl, Vl, Vl, Vl, Vl, V
B, v6, VB, VB, Vl, Vl
, Vl, Vl, Vl, v2, VB
, v6, v6, VB, Vl, Vl
, v2, v2, v2, Vl, v2, V
l, Vl, Vl, Vl, v2, Vl
, v2, Vl, v2, Vl, Vl
, v2, Vl, Vl, Vl, Vl
, Vl, Vl, Vl, v2, Vl,
v2, v2, Vl, Vl, Vl,
v2, Vl, Vl, Vl, VB,
VB, v3, VB, Vl, Vl, v2
, Vl, v2, v2, v3, VB, V
B, v3, Vl, Vl, v2, v2,
Vl, Vl, v3, VB, VB,
Become a VB.

[Voltage Vector] FIG. 3 shows six voltage vectors V1 to V6 and two zero vectors VO1V7. The possible switching states of the switching elements Al, Bl, and CI of the inverter 2 are (
000), (001), (010), (011), (1
00), (101), (110), (111), so this is VOlVl, Vl, VB, V4, v5
, VB, and V7. In the device of this embodiment, voltage vectors VO to V7 are written into the ROM 5 and output as control data (A, B, C). By combining the eight vectors VO to V7, a sinusoidal output voltage and rotating magnetic field vector can be obtained.

[Vector Selection] FIG. 4 shows the selection of a voltage vector to obtain the rotating magnetic field vector φl. In order to make the trajectory of the tip (end point) of the rotating magnetic field vector φ1 approach a circle, 330＠~
6th and 2nd nohector V6, Vl, 30 in 30″ section
e~90° interval Te second and third vectors V2, VB,
The third and first vector Vil in the 90″~150@ interval
l, Vl.

The first and fifth vectors vt in the 150° to 2106 interval
, V5. The fifth and fourth vectors V5 are selected in the 210° to 270@ interval, and the fourth and sixth vectors V4 and VB are selected in the V4.270° to 3300 interval. In principle, VB and Vl are selected as significant vectors in the 330'' to 30° section of FIG. 4, which is shown in principle, and zero vector v7 is selected when stopping vector rotation. The rotating magnetic field vector φ1 is rotated in the direction indicated by UP, and when reversing or braking, DOWN
It is rotated in the direction shown.

[Operation] Next, the operation of the circuit shown in FIG. 1 will be explained with reference to FIG. When a difference signal Vd is obtained based on the comparison between the speed detection signal obtained on the line 9a and the reference signal (target signal) on the line 11, the sign of this signal is determined by the first comparator 14 for determining whether the signal is positive or negative. If the signal is now positive, the comparison output is at a low level "0" as shown before t4 in FIG. 5(C).
This is input to the counter 6. Therefore, the counter 6 operates up during this period. In the second comparator 16 for determining the zero vector period, the absolute value of the difference signal Vd and the triangular wave voltage Vc are compared as shown in FIG. 5(A), and the output shown in FIG. 5(B) is generated. . That is, the period (tl to t) in which the triangular wave voltage Vc is higher than the absolute value of the difference signal Vd
2), a high level output “1” is generated, and a low period (t2~
At t3), a low level output "0" is generated. t1~t2
As shown in FIG.
When the output bit B9 of 4 is low level “0”, the ROM
5, the normal rotation zero vector memory M2 is selected in response to C84BIOI-(01), and the normal rotation PWM pattern M1 is selected when C84BIO)-(00) as in t2 to t3.

Further, in the period (tl to t2) in which the output of the zero vector period determination comparator 16 is at a high level '1'', N.

The output of the T circuit 20 becomes low level, and the AND gate 18
Since the clock pulse of the oscillator 17 is blocked from passing through and the counter 6 is not incremented, the same address continues to be specified. On the other hand, during the period (t2 to t3) in which the output of the zero vector period determination comparator 16 is at a low level, N
Since the output of the OT circuit 20 becomes high level, the oscillator 17
The output clock pulse of passes through AND gate 18 and becomes the input bus of the counter. As a result, counter 6
The value of 9-bit BO-88 is increased by the up operation, and the addresses of memory M1 are sequentially specified.

However, when the output of the zero vector period determination comparator 16 becomes high level at time t3, the clock input to the counter 6 is prohibited, and the counter 6 retains the address designation at this time. For example, as shown in FIG.
When the vector v6 of 1 is being read out, the memory M2
When is selected, the zero vector for normal rotation v7 (111) at the same address 2 is selected. The zero vector v7 continues to be generated while the output of the zero vector period determination comparator 16 is at a high level, and when the comparison output returns to a low level, a clock pulse is input to the counter 6 again, and the output of the counter 6 is incremented by one stage. Then, the normal rotation PWM pattern memory M
Voltage vector V2 (010) at address 3 of 1 is selected. The zero vectors are VO (000) and V7 (1
11), the switch elements A1 to C2
The vector that requires fewer switching is selected. When the counter 6 finishes generating binary numbers corresponding to decimal numbers 0 to 511, all voltage vector data from 0 to 360° of the normal rotation PWM pattern is read out, and the three-phase approximate sine wave voltage is output from the inverter 2. A rotating magnetic field vector having a nearly circular locus is generated in the motor 1.

In such control, as the difference between the target rotational speed and the detected speed becomes smaller, the period during which the output of the second comparator 16 is at a high level becomes relatively longer, and the period during which the zero vector is selected becomes longer. .

Furthermore, if the level of the reference signal on the line 11 is lowered to create a low-speed rotation command state, the level of the absolute value of the difference signal Vd will also be lowered, the output frequency f of the inverter 2 will be lowered, and the output voltage V will also be lowered. 1 is in a low speed drive state.

At t4 in FIG. 5, the command is switched to reverse rotation, and the difference signal Vd
When becomes negative, the output of the forward/reverse determination comparator 14 becomes high level, resulting in reverse control. In addition, in the above PWM control, when the voltage vector is switched, the pair of switch elements A1, A2 or Bl, B2 or CI,
Since there is a risk that the storage and the like may be short-circuited between C2 and destroyed, it is desirable to provide an uncontrolled period between the vectors in order to prevent this.

When a rapid increase in speed is required or when the load suddenly increases, the output current of inverter 2 will decrease as shown in Figure 6 (B).
The flow begins as shown in . Although only the U-phase current 1u is shown in FIG. 6(B), it flows in the other phases as well. This current has a relatively large level and a high frequency component corresponding to the continuity of switching elements A1-C2. The output current of inverter 2 is the rectifier smoothing circuit 2
7, from which the current detection voltage shown in FIG. 6(A) is obtained. This current detection voltage is compared with a reference voltage by a comparator 28 having hysteresis characteristics, and the comparator 28
The signal that controls AND gates 2, 22 and 23 from
This occurs as shown in Figure (C). While the output of the comparator 28 is at a low level, the AND gates 2, 22, and 23 prevent the output data from the memory 5 from being transmitted. As a result, the switching elements A1 to C2 of the inverter 2 are turned off,
Power supply from inverter 2 is interrupted.

Since the comparator 28 operates on hysteresis, even if the current detection voltage becomes lower than the reference voltage, it outputs an open level output for a while, and then returns to the high level output state. By limiting the input current to the motor 1 in this way, it is possible to prevent the motor 1 from entering an excessive torque state. Note that reading of the voltage vector from the memory 5 continues even when the operation of the inverter 2 is interrupted, so that inverter control can be continued smoothly.

[Modifications] The present invention is not limited to the above-described embodiments, and, for example, the following modifications are possible.

(1) The proportional-integral circuit 12 may be a proportional circuit or an integral circuit. Further, this type of constant circuit may be provided on the line 9a side.

(2) Instead of the speed detector 9, a temperature detection signal, a position detection signal, a pressure detection signal, a concentration detection signal, etc. obtained in response to the rotation speed of the motor 1 are used as detection signals, and these are compared with the reference signal. You may.

(3) Current detection of the inverter 2 can also be performed using only two phases or one phase.

(4) Instead of using only voltage vector data as the first vector data, a combination of voltage vector data and zero vector data may be used to improve the waveform. That is, a zero vector may be placed in the voltage vector array of the memory MI SM3.

(5) For example, set the number of addresses of memories M1 to M4 to 819.
The waveform may be improved by increasing the number to 3.

[Effects of the Invention] According to the present invention, generation of excessive torque due to sudden changes in speed or load can be easily prevented.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a motor control system according to an embodiment of the present invention, Fig. 2 is a diagram showing a part of the contents of the ROM in Fig. 1 in principle, and Fig. 3 is a diagram showing voltage vectors. , FIG. 4 is a diagram showing the rotating magnetic field vector, and FIG. 5 is a diagram showing the state of each part in FIG. 1. 1...Motor, 2...Inverter, 5...ROM
, 6...Counter, 9...Speed detector, 10...Comparison circuit, 14...Comparator for forward/reverse determination, 16...Comparator for zero vector period determination, 21, 22.23...・AN
D gate, 28... Comparator for current detection. Agent Nori Takano 112 Figure 6

Claims (1)

[Claims] [1] An inverter that is connected to an AC motor to be controlled and has a plurality of switching elements that operate on and off in a predetermined switching pattern to generate a voltage vector and a zero vector. , first vector data indicating an on/off pattern of the switch to obtain the voltage vector or a combination of the voltage vector and the zero vector in a predetermined order, and on/off of the switching element to obtain the zero vector. a memory in which second vector data indicating a pattern is written; and switching element control for operating the switching element based on the first vector data and the second vector data read from the memory. a reference signal generation circuit that generates a reference signal indicating a target speed of the motor; a comparison circuit that generates a difference signal corresponding to a difference between the reference signal and a detection signal indicating the speed of the motor; a triangular wave generating circuit that generates a triangular wave; and controlling the memory to compare the triangular wave and the difference signal, and read the second vector data from the memory during a period when the difference signal crosses the triangular wave. a second vector period determination comparator for determining a vector period; a clock generator for generating a clock pulse having a frequency higher than the frequency of the triangular wave; a counter that specifies an address for reading the first vector data and the second vector data; and a counter that is connected between the clock generator and the counter and obtained from the second vector period determination comparator. a counter input control gate that blocks passage of the clock pulse in response to a signal indicating selection of the second vector data; a current detector that detects an output current of the inverter; a reference voltage source for providing a reference voltage for detecting that the output current of the inverter has exceeded a predetermined value; and a current detection device for comparing the current detection voltage obtained from the current detector with the reference voltage. a comparator connected between the memory and the switch control circuit, and responsive to an output obtained from the current detection comparator when the current detection voltage becomes larger than the reference voltage. A motor control device comprising: a gate circuit that interrupts transmission of the first vector data and the second vector data.