JPH04167839A - Clock recovery circuit - Google Patents

Abstract

PURPOSE:To realize a clock recovery circuit to prevent production of jitter by connecting a buffer amplifier section of a low output impedance and a high input impedance between a tuning amplifier section and a waveform shaping section. CONSTITUTION:A clock recovery signal from an input terminal 1 is inputted to a tuning amplifier section 2 and its sinusoidal output is inputted to a buffer amplifier section 3 through a coupling resistor R1. Then the signal is shaped into a rectangular wave by a waveform shaping section 4 and outputted as a recovered clock signal from an output terminal 5. In this case, a bias voltage is impressed to the amplifier section 3 by using a bias resistor R2 to control its output DC level and to adjust an input DC bias quantity of the waveform shaping section 4 thereby adjusting the duty ratio of a clock signal at the terminal 5 to be 50%. As a result, even when the input impedance of the shaping section 4 of a logic IC is fluctuated by a voltage, the appearance of the result of fluctuation at the input of the amplifier section 3 is prevented. Thus, production of distortion in the sinusoidal wave from the amplifier section 2 is prevented and jitter of a recovered clock signal is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit provided at an input section of a digital wireless communication device for regenerating a clock signal from a multiplexed digital signal.

[Conventional technology]

Conventionally, this type of clock regeneration circuit, as shown in FIG. It consists of a waveform shaping section 4 that outputs a clock signal, and both are connected by a coupling resistor R1, and an input bias voltage of the waveform shaping section 4 is applied so that the duty ratio of the shaped clock signal is 50%. Resistor R2 for
via the bias power supply V'r I! connected to f.

In such a lock reproducing circuit, the waveform shaping section 4 obtains a clock signal by shaping a sine wave as shown in FIG. 3(a) into a rectangular wave as shown in FIG. 3(b).

[Problem to be solved by the invention]

Normally, the waveform shaping section 4 is composed of a logic IC, but in general, as shown in FIG. There is. Therefore, the tuned amplifier section 2
Even if a sine wave is output from the waveform shaping section 4, due to the influence of its nonlinearity, it becomes a distorted sine wave signal as shown in FIG. 4(a). . Since the distortion occurs near the threshold of the logic IC, the amplitude of the input signal stays near the threshold of the logic IC for a long time, and as a result, as shown in Fig. 4(b).
There is a problem in that jitter components occur in the output clock signal as shown in FIG.

An object of the present invention is to provide a clock recovery circuit that prevents the occurrence of such jitter.

[Means to solve the problem]

The clock regeneration circuit of the present invention has a low output impedance between a tuned amplification section that outputs a sine wave signal as a clock component and a waveform shaping section that shapes the output and outputs a rectangular clock signal. A buffer amplifier with high input impedance is connected.

In particular, the clock regeneration circuit of the present invention connects the tuned amplifier section and the waveform shaping section with a coupling resistor, and applies a bias voltage to this coupling section through the bias resistor so that the duty of the clock signal is 50%. It is applied to clock recovery circuits such as

[Effect]

According to the present invention, the characteristics of low output impedance and high input impedance of the buffer amplifier section prevent the influence of fluctuations in the input impedance of the waveform shaping section on the sine wave output from the tuned amplifier section.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In the figure, 1 is an input terminal into which a signal for clock reproduction is input, 2 is a tuned amplification section that tunes to this signal and outputs a sine wave, 3 is a buffer amplification section, and 4 is a clock that converts the sine wave into a rectangular wave. A waveform shaping section 5 is an output terminal composed of a logic IC that generates a signal. Further, R1 is a coupling resistor, and R2 is a bias resistor connected to a bias power supply (rllf) to provide a required bias voltage.

The buffer amplifier section 3 is configured to have high input impedance and low output impedance.

According to this configuration, the signal for clock reproduction is input to the input terminal 1.
and is input to the tuned amplifier section 2 which is tuned to that frequency. Then, the sine wave output is input to the buffer amplifier section 3 through the coupling resistor R1, and then waveform-shaped into a rectangular wave by the waveform shaping section 4, and outputted from the output terminal 5 as a reproduced clock signal. At this time, by applying a bias voltage to the buffer amplifier section 3 using the bias resistor R2, the output DC level of the buffer amplifier section 3 is controlled, and the input DC bias amount of the waveform shaping section 4 is adjusted and output. terminal 5
The duty ratio of the clock signal is adjusted to 50%.

In this configuration, since the buffer amplifier section 3 with high input impedance and low output impedance is connected to the front stage of the waveform shaping section 4, the waveform shaping section 4 composed of logic ICs is connected.
Even if the input impedance of the amplifier fluctuates depending on the input voltage, this fluctuation is prevented from appearing on the input side of the buffer-amplifying section 3. This prevents distortion from occurring in the sine wave output from the tuned amplifier section 2, and in the case of a sine wave without distortion, the time the signal amplitude remains near the threshold point is reduced, as shown in Figure 3(a). And as shown in (b), a clock signal with improved jitter can be obtained.

〔Effect of the invention〕

As explained above, the present invention connects a buffer amplifier section with low output impedance and high input impedance between the tuned amplifier section and the waveform shaping section, so that the input impedance of the waveform shaping section changes depending on the input voltage. This prevents this from affecting the sine wave output from the tuned amplification section, and always supplies a distortion-free sine wave to the waveform shaping section.
As a result, it is possible to significantly improve the amount of jitter in the reproduced clock signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the clock recovery circuit of the present invention, FIG. 2 is a block diagram of a conventional clock recovery circuit,
Figures 3 (a) and (b) are waveform diagrams of an undistorted sine wave and a regenerated clock signal, and Figures 4 (a) and (b) are waveforms of a distorted sine wave and a regenerated clock signal. FIG. 5 is a diagram showing input impedance characteristics in the waveform shaping section. 1... Input terminal, 2... Tuned amplifier section, 3... Buffer amplifier section, 4... Waveform shaping section, 5... Output terminal, R1
...Resistance for coupling, R2...Resistance for bias. Section (a) (a) Section (b) Figure 4 (b) Shy

Claims (1)

[Claims] 1. A tuned amplification section that outputs a sine wave signal as a clock component in tune with an input signal, and a waveform shaping of the output of this tuned amplification section to output a square wave clock signal. What is claimed is: 1. A clock regeneration circuit comprising a waveform shaping section, characterized in that a buffer amplifier section having a low output impedance and a high input impedance is connected between the tuned amplification section and the waveform shaping section. 2. Connect the tuned amplifier section and the waveform shaping section with a coupling resistor,
2. The clock recovery circuit according to claim 1, wherein a bias voltage is applied to this coupling portion through a bias resistor so that the duty of the clock signal becomes 50%.