JPH04167835A - Error rate deterioration check system and circuit - Google Patents

Abstract

PURPOSE:To set a desired monitor block immediately even when an error rate setting signal is revised in a direction to decrease a monitor block by detecting a rate of a change in the error rate setting signal and resetting a counter when a change point is detected. CONSTITUTION:A change point detection circuit 6 detects a change point of an error rate setting signal from an input terminal T2 and sends a reset signal to a counter 1' every time a change point is detected. The counter 1' receives a reset signal from both the circuit 6 and a selection circuit 3, counts a clock signal (a) and sends the result to a decoder 2. The decoder 2 decodes N-ways of decode values so as to generate a pulse for set N-ways of measured blocks and sends N-ways of decode pulses (f) to the circuit 3. The circuit 3 selects one output (g) from the pulse (f) by the error rate setting signal to reset the counter 1 and an error counter 4. Thus, the desired monitor block is immediately set and no setting wait time is required.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal transmission circuit, and particularly to a circuit for detecting error rate deterioration of a digital signal sent via a transmission path.

An error occurs in a digital signal sent through a transmission path with a certain average probability (error rate) P depending on the quality of the transmission path. The error serious illness warning is defined in advance by the number of errors counted at the receiving point during a monitoring interval predetermined for the error rate P. This is an alarm that is issued when the number of errors within a monitoring interval exceeds a threshold value, that is, when the quality of the transmission path has deteriorated.

[Conventional technology] FIG. 3 shows the configuration of a conventional error rate detection circuit.

In the figure, 1 is a counter, 2 is a decoder, 3 is a selection circuit, 4 is an error counter, 5 is an alarm detection circuit, TI is a reference clock input terminal for determining an error monitoring period,
T2 is an error rate setting signal input terminal, T3 is an error signal input terminal that detects an error in a digital signal sent via a transmission line and generates a pulse, and T6 is an error serious disease warning signal output terminal.

FIG. 4 is a timing chart showing the operation of each part when a conventional circuit is used. In order to explain this circuit, N different error rates that can be set are P(1), P(2),...
P (N), and the corresponding monitoring interval is L.
(1), L (2), ..., L (N). Here, the smaller the error rate P, the longer the monitoring interval needs to be set, so for convenience, P(1)>P (2)
...>P (N), L (1) <L (2) <
...<L(N).

Referring now to FIGS. 3 and 4, the counter 1 is operated by a clock signal j of a certain frequency F, which is used as a reference when determining a monitoring period, and sends a count result m to a decoder 2. The maximum value M that counter 1 can count is L (N)X
larger than F. In decoder 2, the set L (1),
N decode values (D
(1), D (2).

..., D (N) ) and sends N types of decode pulses n to the 2 selection circuit 3. The selection circuit 3 selects one corresponding pulse 0 from the N decode pulses in response to the error rate setting signal, and resets the counter 1 and the error counter 4 based on it. That is, the error counter 4 sequentially counts the number of errors p for each set monitoring section. The alarm detection circuit 5 receives the error rate setting signal and determines the corresponding threshold (
Y (1), Y (2),..., Y (N))
is selected, and when the number of errors actually counted in each monitoring section exceeds the threshold value, an error serious illness warning q is output from T6.

In the above operation, as an example in Fig. 4, a setting signal such as setting the error rate setting signal to P(5) is input, the monitoring interval is set to L(5), and the L threshold is set to Y(5). Indicates the case where If Y (5) = 4, an alarm q is generated when the output p of the error counter 4 reaches 5.

In this conventional circuit, when the error rate setting signal is changed in a direction that shortens the monitoring interval (for example, from L(5) to 1) (as of A in FIG. 4), the error rate setting signal If the count value of counter 1 at the moment when the value is changed is a value exceeding L(1) (C in FIG. 44), then decoder 2
does not emit a decode pulse, and L (5) and L (1)
If the difference is large, it will take a considerable amount of time (α in FIG. 4) until the desired monitoring section is set.

[Problems to be Solved by the Invention] In this way, in the conventional circuit, when the error rate setting signal is changed in a direction that shortens the monitoring interval, the count value of counter 1 at the time when the change is made is In some cases, there is a problem in that it takes time to set up the monitoring section.

The present invention solves these problems of the conventional ones, and provides an error deterioration detection circuit that immediately sets a desired monitoring period even when the error rate setting signal is changed in a direction that shortens the monitoring period. This is what we provide.

[Means for Solving the Problems] According to the present invention, a counter receives an externally applied error rate setting signal, decodes the output of the counter into a plurality of values and outputs the decoded values, and outputs a plurality of values according to the error rate setting signal. selects one of the plurality of outputs and sends a reset signal to the counter, while counting error signals input from the outside based on the reset signal, the number of which corresponds to the error rate setting signal. In an error rate deterioration detection method that issues an error overwriting alarm when the error rate exceeds a predetermined threshold, the rate of change of the error rate setting signal is detected, and when a change point is detected, the counter is reset. An error rate deterioration detection method characterized by the following is obtained.

Further, according to the present invention, a counter that uses a clock signal of a certain period as a clock input and can be reset by a reset signal, and a plurality of decoders that decode the output of the counter into a plurality of preset different values,
a selection circuit that selects one of the outputs of the plurality of decoders according to an error rate setting signal applied from the outside and sends a reset signal to the counter; and a selection circuit that counts error signals input from the outside and selects the an error counter that is reset by an output signal of the circuit; an alarm detection circuit that compares the number of errors counted by the error counter with a predetermined threshold value corresponding to the error rate setting signal; and the error rate setting. An error rate deterioration detection circuit is obtained, comprising a change point detection circuit that detects a change point of a signal and sends a reset signal to the counter.

[Example code] The present invention will be described below with reference to Examples.

FIG. 1 shows a configuration diagram of an embodiment of the error rate deterioration detection circuit of the present invention.

In FIG. 1, 1 is a counter and 2 is a decoder.

3 is a selection circuit, 4 is an error counter, 5 is an alarm detection circuit, Tl is a reference clock input terminal for determining the error monitoring period, T2 is an error rate setting signal input terminal, and 6 is a change point of the error rate setting signal. Detect.

A change point detection circuit that issues a reset signal every time a change point is detected, T4 is an input terminal for sending the reset signal issued from the change point detection circuit to counter 1, and T3 is sent via a transmission line. T6 is an error signal input terminal for inputting to the error counter 4 for detecting errors in the digital signal, and an error serious illness warning signal output terminal.

FIG. 2 is a diagram showing a timing chart of each part when the error rate deterioration detection circuit of FIG. 1 is used and the same external signal as that of FIG. 4 is input.

In order to explain this circuit, similar to the explanation of the conventional circuit shown in FIG.
2) ,..., P (N), and the corresponding monitoring interval is determined as L (1), L (2),...
As L (N), (P (1) > P (2)
...>P(N), L(1)<L (2)<...<L
(N) ).

The counter 1' is operated by a clock signal a of a certain frequency F, which serves as a reference when determining a monitoring period.

The counting result e is sent to the decoder 2. Note that this counter 1' operates upon receiving reset signals from both the change point detection circuit 6 and the selection circuit 3. The maximum value M that the counter 1' can count is L (N)XF, which is also large. Decoder 2 uses the set L(1), L(2),..., L(N
) to generate a pulse for each of the N measurement intervals (D(1), D(2), . . . ).
Decode D(N)).

N types of decode pulses f are sent to the selection circuit 3. The selection circuit 3 selects one corresponding output g from N decode pulses in response to the error rate setting signal.

Based on this, counter 1 and error counter 4 are reset. That is, the error counter 4 sequentially counts the number of errors for each set monitoring section. The alarm detection circuit 5 receives the error rate setting signal and determines the corresponding error thresholds (Y (1), Y (2) within the monitoring interval).
), .

Figure 2 shows, as an example, a case where a setting signal that sets the error rate setting signal to P(5) is input, the monitoring interval is set to L(5), and the L threshold is set to Y(5). . Y (5)
If =4, the alarm output i is generated when the output of the error counter 4 reaches 5.

= 10 - In this circuit, the detection circuit 6 detects the change point of the error rate setting signal, and every time a change point is detected, a reset signal is sent to the counter 1, and the counter 1 is reset. Therefore, even when changing the error rate setting signal in a direction that shortens the monitoring interval, for example, when changing from L(5) to 1) (as of B in Figure 2), the error rate setting signal changes. Since the instantaneous count value of counter 1 is reset, it does not exist in the count value of counter 1 before the setting change.

The desired monitoring interval is immediately set.

[Effects of the Invention] As explained above, the error rate deterioration detection circuit of the present invention can immediately set the desired monitoring period even when the error rate setting signal is changed in a direction that shortens the monitoring period. The effect is that there is no need for setting waiting time as in the past.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment of the error rate deterioration detection circuit of the present invention, FIG. 2 is a diagram showing a timing chart of each part when the error realization detection circuit of FIG. 1 is used, and FIG. 4 is a diagram showing the configuration of a conventional error rate deterioration detection circuit, and FIG. 4 is a diagram showing a timing chart of each part when the error rate deterioration detection circuit of FIG. 3 is used. Explanation of symbols = 1. 1-... Counter, 2... Decoder, 3... Selection circuit, 4... Error counter, 5...
... Alarm detection circuit, 6... Change point detection circuit.

Claims (2)

[Claims] (1) A counter receives an error rate setting signal given from the outside, decodes the output of this counter into multiple values and outputs them, and selects one of the multiple outputs according to the error rate setting signal. and send a reset signal to the counter,
On the other hand, error rate deterioration detection that counts error signals input from the outside based on the reset signal and issues an error rate deterioration alarm when the number exceeds a predetermined threshold corresponding to the error rate setting signal. An error rate deterioration detection method, characterized in that the rate of change of the error rate setting signal is detected, and when a change point is detected, the counter is reset. (2) A counter that uses a clock signal of a certain period as a clock input and can be reset by a reset signal, a plurality of decoders that decode the output of the counter into a plurality of preset values, and the plurality of decoders. A selection circuit that selects one of the outputs according to an error rate setting signal given from the outside and sends a reset signal to the counter; and a selection circuit that counts error signals input from the outside and resets it by the output signal of the selection circuit. an alarm detection circuit that compares the number of errors counted by the error counter with a predetermined threshold value corresponding to the error rate setting signal; and detecting a change point of the error rate setting signal. and a change point detection circuit that sends a reset signal to the counter.