JPH04167783A - Correction circuit for video signal - Google Patents

Abstract

PURPOSE:To prevent the generation of distortion in the edge part of a video signal after correction by reducing the amplitude level of the output where the data of the video signal is corrected according to an error generation rate. CONSTITUTION:A divider 6 inputs a signal A and processes it according to the number of error flags supplied from an error counter 2. In short, the divider 6 divides the signal A by an exponent EXP(X+alpha) of the number of error flags, and drops video contrast when many errors are generated by indexically reducing the amplitude level of the signal a according to the error generation rate. Thus, the generation of the distortion in the edge of the video signal after correction can be prevented, and the picture quality of the video can be improved.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention improves image quality by correcting errors in video signals in devices such as video tape recorders (VTRs) and magneto-optical disk recorders that record or reproduce video signals. The present invention relates to a video signal correction circuit.

[Prior Art] Conventionally, in this type of video signal correction circuit, a continuous 8-bit parallel video signal and a 1-bit error flag added to each byte of this video signal are input, and this error flag is to detect errors in the video signal. And when it detects an error in the video signal,
The data of signal samples that have no errors at four points around the detected signal sample and have the same phase as the target data are output as correction signals, and when all four points have errors, they are delayed by the N field memory. A correction signal N fields before is output. In this way, the video signal is corrected by replacing the error video signal with the correction signal.

[Problems to be Solved by the Invention] However, in the conventional video signal correction circuit described above, the edge portion of the video signal where the luminance signal or color component tends to change greatly when errors occur frequently in one field. When an error occurs, there is a problem in that distortion due to correction is likely to occur in the edge portion of the video signal after correction. Furthermore, if distortion occurs at the edge portions of the video signal, the image quality of the video will be significantly degraded.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a video signal correction circuit that can prevent distortion from occurring in the edge portion of a video signal after correction.

[Means for Solving the Problems] A video signal correction circuit according to the present invention inputs a video signal and an error flag added to the video signal, and corrects data of the video signal according to the error flag. a correction circuit; an error counter that counts the number of error flags during a period of N (arbitrary integer) fields;
a first field memory that delays the output of the error correction circuit by N fields; a division circuit that divides the output of the first field memory by a function whose index is a constant corresponding to the number of error flags; and this division circuit. and a selector that receives the output of the first field memory and outputs either one of them depending on the number of error flags.

Further, in addition to the above-mentioned circuit, another video signal correction circuit according to the present invention is configured such that the output of the first field memory is
A second field memory for field delay, a phase adjustment circuit for adjusting the color phase of the output of this second field memory, and an output of this phase adjustment circuit and an output of the first field memory are inputted and both are inputted. The selector inputs the output of the division circuit, the output of the first field memory, and the output of the addition circuit, and selects one of them according to the number of error flags. It is characterized by output.

[Operation] In the present invention, the error correction circuit inputs a video signal and an error flag added to the video signal, and corrects the data of the video signal in accordance with the error flag. On the other hand, the error counter counts the number of error flags during the N field period. The output of the error correction circuit is delayed by N fields in the first field memory and then supplied to the selector. The division circuit is a function whose index is a constant corresponding to the number of error flags.
, and the amplitude level of the output of the first field memory is exponentially lowered according to the number of error flags during the N field period, that is, the error occurrence rate. This slightly reduces the contrast of the image. The output of this division circuit is supplied to a selector. The selector inputs the output of the division circuit and the output of the first field memory, and outputs either one of them depending on the number of error flags.

According to the present invention, the output of the first field memory and the output of the division circuit can be switched depending on the error occurrence rate, and when the error occurrence rate is relatively high, the output is a corrected video signal. The amplitude level can be lowered. Therefore, even if an error occurs in the edge portion of the video signal, it is possible to prevent the luminance signal or color component from changing significantly, and it is possible to prevent distortion from occurring in the edge portion of the video signal after correction.

Further, in the present invention, in addition to the two types of outputs described above, the following outputs can be selected and outputted using a selector. That is, after the output of the first field memory is delayed by one field in the second field memory, its color phase is adjusted by a phase adjustment circuit. The adder circuit inputs the output of this phase adjustment circuit and the output of the first field memory, and outputs a combination of both. This makes it possible to reduce high-frequency noise components in the output of the first field memory. Then, the selector inputs the output of the division circuit, the output of the first field memory, and the output of the addition circuit, and outputs one of these depending on the number of error flags. In this case, each of the above outputs can be selected depending on the error occurrence rate.

[Embodiments] Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a video signal correction circuit according to an embodiment of the present invention.

The error correction circuit 1 receives an input signal S1 including a continuous 8-bit parallel video signal and a 1-bit error flag added to each byte of this video signal, and detects when the error flag is set in the input signal S1. Check to see if there is one. If the error flag is not set in the input signal S1,
The error correction circuit 1 determines that the data of the input signal S1 is correct and outputs it as is as a correction signal S3. Note that the correction signal S3 is input to the one-field memory 4, delayed, and fed back to the error correction circuit 1 again. On the other hand, when an error flag is set in the input signal S1, the error correction circuit 1 monitors the error flag at four points (a, b, C+d) whose color phase is equal to that of the target data and is separated by ±IH ± 2 CLK. A predetermined correction signal S3 is output according to the four error flags. That is, when error flags are not set at all four points, the error correction circuit 1 outputs (a+b+c+d)/4 as the correction signal S3. When the error flag is set at point b or point 0, the error correction circuit 1 outputs (a+d) as the correction signal s3.
/2 is output. When the error flag is set at point a or point d, the error correction circuit 1 outputs (b
Output c)/2. When the error flag is set at three points from point a to point d, the error correction circuit 1 detects the point where the error flag is not set (a+ 'b+ c or d).
The signal is output as a correction signal S3. Also, when error flags are set at all four points, error correction circuit 1
is the data fed back from the 1-field memory 4 (signal A corrected 1 field before) as the correction signal S3
Output as . The error flag of the input signal s1 is used for the above-mentioned processing in the error correction circuit engineer, and
The error flag signal q-82 is input from the error correction circuit 1 to the error counter 2.

The error counter 2 operates in response to the reset signal R8T input in l field cycles, counts the total number of error flags for each field, and calculates the number of error flags for each l field according to the number of error flags and this number of error flags. The generated select signal S4 is output.

The field memory 4 inputs the correction signal S3, delays it, and distributes and supplies the signal A to four systems. That is, the first system of the signal A is directly input to the selector 3, the second system is input to the divider 6, the third system is fed back to the error correction circuit 1, and the fourth system is input to the one field memory. 8 to the phase adjustment circuit 5.

The divider 6 inputs the signal A and processes the signal A according to the number of error flags supplied from the error counter 2. That is, the divider 6 converts the signal A into an index of the number of error flags EXP (
X+α) to exponentially lower the level of the amplitude of signal A according to the rate of error occurrence. This reduces the contrast of the video when many errors occur. Note that X is a value proportional to the number of error flags input from the error counter 2, and α is a threshold value.

Further, the signal A/EXP (X0α) whose amplitude level has been lowered in accordance with the error occurrence rate in the divider 6 is input to the selector 3.

The phase adjustment circuit 5 inputs a signal obtained by delaying the signal A in the one field memory 8, adjusts the phase so that the color phase of the signal A matches the color phase of the signal one field before, and outputs the signal B. do.

The adder 7 inputs the signal A from the one-field memory 4 and the signal B from the phase adjustment circuit 5, combines them, and outputs a signal (A+B)/2. This signal (A + B)/2 is the output of the 1-field memory 4 subjected to noise reduction, and becomes a signal with reduced high-frequency noise components.

The selector 3 inputs the signal A1 supplied from the 1-field memory 4, the signal (A+B)/2 supplied from the adder 7, and the signal A/EXP (X+α) supplied from the divider 6, and selects the error counter 2. These are selected according to the signal S4 and output as the output signal S5. For example, select signal A when the error rate of field ■ is less than 10%, and select signal (A+B) when the error rate is between 10 and 40%.
/2 may be selected, and if the error rate exceeds 40%, the signal A/EXP (X+α) may be selected.

In this embodiment, when the error rate of one field of the input signal S1 including the video signal reaches 0 to 40% per month, the output signal S5 reduces the high frequency noise component of the signal A according to the error rate. The signal switches to (A + B)/2. Furthermore, when the error occurrence rate of one field of the input signal S1 exceeds 40%, the output signal S5 is a signal A/A whose amplitude level is exponentially reduced according to the error occurrence rate.
Switch to EXP (X1α). Therefore, even if an error occurs in the edge portion of the video signal, it is possible to prevent the luminance signal or the color component from changing significantly, and it is possible to prevent distortion from occurring in the edge portion of the video signal after correction. This makes it possible to improve the image quality of videos from VTRs, magneto-optical disk recorders, and the like.

[Effects of the Invention] As explained above, according to the present invention, the amplitude level of the output obtained by correcting the data of the video signal can be lowered according to the error occurrence rate, and the high-frequency noise component thereof can be reduced. I can do it. Therefore, even if an error occurs in the edge portion of the video signal, it is possible to prevent the luminance signal or the color component from changing significantly, and it is possible to prevent distortion from occurring in the edge portion of the video signal after correction. This has the effect of improving the image quality of the video.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a video signal correction circuit according to an embodiment of the present invention.

Claims (2)

[Claims] (1) An error correction circuit that inputs a video signal and an error flag added to this video signal and corrects data of the video signal according to the error flag, and the number of error flags in a period of N (arbitrary integer) fields. an error counter that counts the number of error flags; a first field memory that delays the output of the error correction circuit by N fields;
and a selector that inputs the output of this division circuit and the output of the first field memory and outputs either one of them depending on the number of error flags. A video signal correction circuit characterized by: (2) An error correction circuit that inputs a video signal and an error flag added to this video signal and corrects data of the video signal according to the error flag, and the number of error flags in a period of N (arbitrary integer) fields. an error counter that counts the number of error flags; a first field memory that delays the output of the error correction circuit by N fields;
a division circuit that divides the output of the field memory; a second field memory that delays the output of the first field memory by one field; and a phase adjustment circuit that adjusts the color phase of the output of the second field memory. , an adder circuit that inputs the output of the phase adjustment circuit and the output of the first field memory, and outputs a combination of both;
A video signal generator comprising a selector inputting the output of the division circuit, the output of the first field memory, and the output of the addition circuit and outputting one of them according to the number of error flags. correction circuit.