JP3451629B2 - Digital closed loop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] The present invention relates to, for example, an ACC (Auto
matic Color Control: Automatic color saturation adjustment) and AGC
(Automatic Gain Control) circuit
Thus, a closed loop is configured by providing a feedback path
It relates to a digital closed loop circuit. [0002] 2. Description of the Related Art A conventional feedback path is provided to close
As a digital closed-loop circuit that configures a loop,
For example, it can be installed in television receivers, video tape recorders, etc.
So-called ACC (Automatic Color Control:
Automatic color saturation adjustment circuit and AGC (Automatic Gain Con
trol: automatic gain control) circuit. For example, the ACC circuit includes the television
Fluctuations in received radio waves and irregular antenna systems
The level difference between the luminance signal and the carrier chrominance signal varies depending on the situation.
Can cause irregularities in screen saturation,
Switching the channel can change only the saturation
The carrier color to be added to the demodulation circuit of the above-mentioned television receiver
Band amplification circuit that operates to keep the signal level constant
Is provided for automatically adjusting the gain of. This
ACC circuit compares the burst amplitude value with the reference value and
Gain control is performed so that the saturation is always maintained at a constant level.
Specifically, it is configured as shown in FIG.
Things. In FIG. 8, first, the ACC circuit
Is supplied with a carrier color signal.
The signal is sent to the level detection circuit 25 via the multiplier 23.
You. The level detection circuit 25 detects the level of the carrier color signal.
This is to detect the file. Where the chroma level is a bar
The level detection circuit
In path 25, the television supplied via terminal 22
Burst gate pal from synchronous deflection system block of receiver
When the transport color is, for example, “H” (high level),
A signal level, that is, a burst amplitude value is detected. Next, in the ACC circuit, the level detection is performed.
Difference between level detection output from output circuit 25 and reference
Determine the loop gain by integrating. That is,
In this ACC circuit, the level detection circuit 25
The output level detection output is supplied to the level reference value generation circuit 2.
8 is a predetermined level reference value (reference).
As an addition signal to the adder 26 supplied as a signal.
Can be From the adder 26, the level reference value and the
The difference from the level detection output is obtained, and this difference output is integrated
Sent to the vessel 27. The integration output integrated by this integrator 27
The force is sent to the multiplier 23 as a multiplication coefficient. The power
In the arithmetic unit 23, the carrier color signal from the input terminal 21 is
The multiplication coefficient from the integrator 27 is multiplied. This multiplier
The multiplication signal from 23 is output terminal 24 as ACC output
And output to the subsequent decoder. [0006] Here, as described above,
In a simple ACC circuit, when the transient response converges,
The level detection value from the level detection circuit 25 and the level
The difference from the level reference value from the
B (level detection-level reference value = 0). However, the ACC circuit is, for example, a digital type.
Tallied, the effect of the finite word length associated with quantization
The level may fluctuate near the level reference
Vibrations), external noise, quantization noise, etc.
The level fluctuates (loop fluctuates).
In other words, the closed loop is affected by external noise and quantization noise.
Even after the transient response of the
The level detection value may fluctuate and become unstable. Accordingly, the present invention has been made in view of the above-described situation.
It has been proposed in the
After the answer converges, the effects of external noise and quantization noise
Digit that can obtain a stable state without receiving
The purpose is to provide a closed loop circuit
You. [0009] SUMMARY OF THE INVENTION A digital closure according to the present invention is provided.
Loop circuit provides a closed loop by providing a feedback path.
The first level in the digital closed loop circuit
Generates a constant level output signal for a range of input signals
And for input signals outside the first level rangeinput
The difference between the level of the signal and the threshold that defines the first level range
Approximately proportional to minutesFirst core to generate level output signal
A ring means and a first level including a first level range.
For input signals in a second level range wider than the bell range
Generates a constant level output signal and a second level range
For input signals other thanInput signal level and second level
Is approximately proportional to the difference from the threshold that defines theLevel out
Second coring means for generating a force signal;First core
Output signal of constant level from ring means continues for predetermined time
Convergence determining means for determining whether or not to output
Inputting the output signal from the determination means, the first coring
Output signal of the means or output of said second coring means
Switching to output one of the signals to the feedback path
Control meansAnd [0010] According to the digital closed loop circuit of the present invention,
The feedback path via the first coring means
The transient response with this first coring means.
Bunch,Convergence of transient response is judged by convergence judgment means
When, Which has a core level larger than that of the first coring means.
Cut into a feedback path through a second coring means
In other words, closed loops such as external noise and quantization noise
To obtain more stable state for unstable elements of the system
are doing. [0011] Embodiments of the present invention will be described below with reference to the drawings.
explain. A digital closed loop circuit according to an embodiment of the present invention.
Is feedback, for example, as in the ACC circuit shown in FIG.
Closed loop with closed loop
A circuit having a first level range (core level C_I)of
The input signal (the output signal of the adder 26) has a fixed level.
Output level signal and the corresponding core level C_IOther than
The input signal has a level approximately proportional to the level of the input signal.
The first coring means to generate the bell output signal
The inner coring circuit 62 and the core level C_Iincluding
With the core level C_IWider second level range
(Core level C_O) Output signal of a certain level
Generate a force signal and the relevant core level C_OInput signal other than
Output level approximately proportional to the level of the input signal.
Outer core as second coring means for generating a force signal
Double coring block 29 including ring circuit 64
And the filter through the inner coring circuit 62.
After converging the closed loop of the feedback path,
Switch to the feedback path via the alling circuit 64
It is something that can be obtained. In FIG. 1, FIG. 8 and FIG.
The same components are denoted by the same reference symbols, and their description is given.
Is omitted. Here, the digital closed loop circuit of this embodiment is used.
In the road (ACC circuit), the ACC circuit
Of the above burst signal generated by digitization of the
To prevent fluctuation of level detection value (loop vibration, etc.)
To coring the above feedback path
I have to. That is, in the configuration of FIG.
The core is provided after the adder 26 (before the integrator 27).
(The inner coring circuit 62 and the
Dual coring block having outer coring circuit 64
(29). Incidentally, the above-mentioned coring is, for example, as shown in FIG.
As shown in (a), the core level is C (C> 0) and the core level is C.
X is the input to the arranging means (core input),
When the output from the stage (core output) is y,
When the core input (x) is below the core level (-C)
The core output (y) is y = x + C, and the core input (x) is
If the level is equal to or higher than (+ C), the core output (y) is set to y =
x−C, the core input (x) is the core level (−C) and
Core output when (-C <x <C) against (+ C)
(Y) is set to y = 0. That is, x ≦ −C
When y = x + C, when x ≦ C, y = x−C, −C
When x <C, y = 0. Also, without core
(When the core level is set to 0), as shown in FIG.
Thus, y = x. By the way, the digital closed loop of this embodiment
The influence of the finite word length associated with the above-mentioned quantization in the circuit
For the vibration of the loop near the above level reference value,
For example, a core level C as shown in FIG._IInput signal
A fixed level output signal for the
Level C_ILevel of the input signal
The inner core generates an output signal with a level approximately proportional to the
Inserting the ringing circuit 62 into the feedback path
Can be addressed. In this case, however, the input terminal 21
If the chroma level of
The core level C in the inner coring circuit 62_I
Need to be larger. Here, the above ACC circuit
And a coring process performed before the integrator 27
This means, as shown in equation (1), a-level reference value = ± C_I            ・ ・ ・ ・ ・ (1) Means that the transient response converges. However, this expression
(1) C in_IIs the core level of the inner coring circuit 62
Where a is the burst level. Also, this equation (1)
As shown in equation (2), a = level reference value ± C_I              ・ ・ ・ ・ ・ (2) However, this is because the ACC circuit has an offset.
Means that the transient response ends in a state where the error has occurred. But
Therefore, in the inner coring circuit 62, the core
Bell C_IIncreasing the offset means increasing the offset
It is equally unfavorable to make. Also, the inner coring circuit 62
Even if the loop stops vibrating,
Due to external noise and quantization noise, etc.
Core level C_IThe loop shakes around. From the above, it is considered that the digital
In a closed loop loop circuit (ACC circuit), the above double
In the coring block 29, the loop
The above core array as shown in FIG.
Bell C_ITogether with the inner coring circuit 62 of FIG.
Loops are affected by noise and quantization noise.
As a countermeasure in case_IIncluding
Core level C_IAs shown in Fig. 3 (a)
Note Core Level C_OOutput at a constant level with respect to the input signal
Signal and the relevant core level C_OInput signal other than
Output signal with a level approximately proportional to the input signal level.
The outer coring circuit 64 for generating a signal is also provided.
You. That is, in this embodiment, the inner side
After the transient response is converged by the coring circuit 62,
Switch to the outer coring circuit 64 with a higher level
The core level C_INeighborhood
Core output even if the burst level detection value fluctuates
(Y) is constant (y = 0), and the loop gain of the ACC circuit is
It is possible to make the inn constant. In addition, this implementation
In the example digital closed loop circuit,
By performing double processing, the inner core
Level C in the switching circuit 62_ICan be reduced
I am able to do it. In the outer coring circuit 64,
Above core level C_OFor example,
When changing, the chroma level changes due to VTR noise bar, etc.
Level is set so that the core will come off when
You. Returning to FIG. 1, the digital
Configuration of Double Coring Block 29 in Closed Loop Circuit
And operation will be described. In FIG. 1, the output of the adder 26 is
The signal (the difference output) is output from the double coring block
29 through the input terminal 61 of the internal coring circuit 6
2 and the outer coring circuit 64. The inner side
The output terminal of the combining circuit 62 is a switched end of the selector 66.
Output terminal of the outer coring circuit 64
The child is connected to the switched terminal b of the selector 66. Ma
The common terminal of the selector 66 is
The integrator 27 via an output terminal 67 of the
Connected to the input terminals of the
Network is configured. Therefore, the selector 6
Depending on which of the switched terminals of item 6 is selected,
Which of the coring circuits 62 and 64 is
It will be determined if they are connected. From the above, as described above,
After the transient response is converged by the inner coring circuit 62,
Cut feedback path to outer coring circuit 64
Switching control (switching control of the switched terminal of the selector 66)
To do so, first, the switched terminal a of the selector 66
Side and the feed of the inner coring circuit 62
Whether the loop due to the back path is converging
Judgment and feedback on the inner coring circuit 62 side
If the loop by the loop path is determined to have converged,
In such a case, it is difficult to select the switched terminal b side of the selector 66.
Disconnection and switching control must be performed. That is, in the present embodiment, FIG.
As shown in (b), the core input (x) is in the region E_ThreeAnd territory
Area E_FourIf core level C_IPlace in
In this case, select the outer coring circuit 64 side and
The input (x) is the area E₁And region E₆Ie if it is within
Core level C_IAlso within core level C_OPlace not inside
In this case, select the inner coring circuit 62
I have. Further, the core input (x) is in the region E_TwoAnd region E_Five
If core level C_OWithin and at the core level
Le C_IThe transient response converges when
In the process of the inner coring circuit 62
After the transient response converges,
When the level detection value of the level detection circuit 25 has changed.
In this case, select the outer coring circuit 64
I have. In this embodiment, the inner side
Switching between coring circuit 62 and outer coring circuit 64
Of the inner coring circuit 62 and the outer
A selector 66 for switching the coring circuit 64
The generation of the switching control signal (core switching signal SEL)
By the removal circuit 63 and the determination circuit 65
I have. The isolated point removing circuit 63 and the decision circuit 6
In step 5, the determination of the switching selection and
The core switching signal SEL is generated. First, from the inner coring circuit 62,
Is an inner core control signal CNT as shown in FIG.₁
Is also output, and this inner core control signal CNT is output.₁ Is isolated above
The signal is sent to the point removing circuit 63. The inner core control signal
No. CNT₁ Is, for example, "L" (low level or
“0”), the core input (| x |)
The level (core level) at which the core does not
Le C_I "H" (high level)
Alternatively, when “1”), the inner coring circuit 62
A level (core level C)_I Within)
are doing. The isolated point removing circuit 63 includes the inner core
Control signal CNT_IAre continuously "H", for example.
Sometimes it goes to "H" level and at other times
Outputs an isolated point removal signal IS of "L" level
The isolated point removal signal IS is transmitted to the determination circuit 65.
Sent. The inner core control signal CNT_IIs continuous
The internal coring circuit 62
Will converge. On the other hand, from the outer coring circuit 64
Similar to the inner coring circuit 62, the core level C
_O(The outer core control as shown in Fig. 3 (d))
Control signal CNT_O) Is output.
Outer core control signal CNT_OIs also sent to the determination circuit 65.
It has become so. The determination circuit 65 determines whether the outer core control signal
No. CNT_OAnd the isolated point removal signal IS (the inner core control signal)
No. CNT_I) Based on "H" or "L"
Output the core switching signal SEL to the selector 66 as described above.
It is something to empower. Note that the selector 66 is connected to the
When the switching signal SEL is, for example, "L", the switched terminal a
Side is selected and the core switching signal SEL is, for example, "H"
The switched terminal b side is selected. [0032] [Table 1]Note that, as shown in Table 1, the core
Force (x) is area E_TwoAnd region E_FiveInside if above
Between the coring circuit 62 and the outer coring circuit 64
Specifically, the switching is performed 1H before (one horizontal period before).
When the core switching signal SEL is "L", the inner coring circuit
On the 62 side, the above core switching 1H before (one horizontal period before)
When the signal SEL is “H”, the outer coring circuit 64 side
Switch so that That is, in Table 1, the number of times of the determination is
The road 65 is such that the core input (x) is in the region E ₁And region E₆Inside
Core control signal CNT_IAnd the outer core control signal CNT_Oas well as
When the core switching signal SEL 1H before is all “L”, the core
The switching signal SEL is set to “L”, and the core input (x) is in the region E
_TwoAnd region E_FiveAnd the inner core control signal CNT_IAnd 1H ago
A) The switching signal SEL becomes "L" and the outer core control signal CN
T_OIs "H", the core switching signal SEL is set to "L".
And the core input (x) is in the region E_ThreeAnd region E_FourWith inner core system
Control signal CNT_IAnd the outer core control signal CNT_OIs "H"
1H before the core switching signal SEL is "L"
The switching signal SEL is set to “H”, and the core input (x) is in the region E
₁And region E₆And the inner core control signal CNT_IAnd outer core system
Control signal CNT_OBecomes “L” and the core switching signal S 1H before
When the EL is “H”, the core switching signal SEL is set to “L”.
And the core input (x) is in the region E_TwoAnd region E_FiveWith outer core system
Control signal CNT_OAnd the core switching signal SEL 1H before is “H”.
And the inner core control signal CNT _IWhen "L" is the core
The switching signal SEL is set to “H”, and the core input (x) is in the region E
_ThreeAnd region E_FourAnd the inner core control signal CNT_IAnd outer core system
Control signal CNT_OAnd the core switching signal SEL before 1H is all
When the core switching signal SEL is set to “H” when “H”,
You. Next, the inner coring circuit 62, the outer coring circuit 62,
FIG. 4 shows a specific configuration of the coring circuit 64. In addition,
A normal coring circuit has a core input (x) and a core level
A comparator is used to find the magnitude relationship of C.
In the example, the structure shown in FIG.
It has been done. In FIG. 4, via input terminal 31
When the supplied core input (x) is sent to the adder 32,
The sign bit (S) of the core input (x)₀) Cash register
It is sent to the star 34. The register 34 stores the core input.
Sign bit of force (x) (S ₀) Is “0” (core input)
Core level (C) held when force (x) is positive)
Bit inversion of the data of the core level (-C).
Data is sent to the adder 32, and the core input
(X) sign bit (S₀) Is “1” (core input
(When (x) is negative), the core level C data
Is sent to the adder 32 as it is. That is,
The output R of the register 34 is S₀= 1, R = C,
S₀When R = 0, R = -C. In the adder 32,
Data of the core input (x) and output of the register 34
R data and the addition output (A) is selected.
Is sent to one of the selected terminals of the connector 36. The core input via the input terminal 31
(X) sign bit (S₀) Is an exclusive OR gate
(EX-OR) 33 so that it is also sent to one input terminal.
It has become. The other input of this exclusive OR gate 33
The output terminal has a sign bit of the addition output of the adder 32.
(S₁) Is supplied. That is,
In the exclusive OR gate 33, the core input (x) is
The sign of the addition output (A) is compared. Where
At the boundary where y = 0 in FIG.
(X) sign bit (S₀) And the above addition output (A)
Sign bit (S₁) And this is exclusive
Is detected by the exclusive OR operation in the exclusive OR gate 33.
ing. The output of the gate 33 is selected by the selector 36.
It is sent to the selection control signal input terminal SW.
The output of the exclusive OR gate 33 is connected to a terminal 37.
From the core switching signal (inner core switching signal or outer core off signal
(A replacement signal). Further, the other selected end of the selector 36
The child receives the data from the register 35 storing the data “0”.
An output (B) is provided. That is, the selector
36 is supplied to the selection control signal input terminal SW.
According to the output of the exclusive OR gate 33,
Output by switching between force (A) and register output (B) data.
It is designed to help. Here, the selector 36
Is, for example, data to the selection control signal input terminal SW.
When the (output of the gate 33) is "1", the above register is output.
Output the force (B) data and input the selection control signal
When the data to the SW is "0", the addition output (A)
Outputs data. Output of this selector 36
Is output to the terminal 38 as a core output (y). That is, the coring circuit shown in FIG.
, The output of the exclusive OR gate 33 (core
When the switching signal is "1", the core output (y) is y = B = 0.
And the output of the exclusive OR gate 33 is "0".
At this time, the core output (y) becomes y = A. In FIG. 4, the inner coring
The configurations of the circuit 62 and the outer coring circuit 64 are substantially the same.
Therefore, the data stored in the register 34 is different.
Only. That is, the inner coring circuit 62
In this case, the data of the register 34 is the core level C._I
In the case of the outer coring circuit 64,
Indicates that the data in the register 34 is the core level C_ONo
Data. FIG. 5 shows a specific example of the isolated point removing circuit 63.
Fig. 2 shows a typical configuration. In FIG. 5, the isolated point removing circuit
63 has an input terminal 41 connected to the inner coring circuit 62.
Inner core control signal CNT from_IIs supplied. This
Inner core control signal CNT_IAre n cascade-connected
Delay element 42₁~ 42_nAre sent in sequence. In addition,
The inner core control signal CNT via the force terminal 41_Ias well as
Each delay element 42₁~ 42_nOutput is (n + 1) input
To each input terminal of the AND gate 43
Can be The output of the AND gate 43 is an isolated point removal signal.
It is output from the output terminal 44 as IS. That is, the isolated point removing circuit 63 of FIG.
Determines whether or not the ACC circuit of this embodiment has converged.
This is to perform with a simple configuration, and remove the isolated point.
According to the circuit 63, the core coring circuit 62
Above the continuous "H" indicating that
Core control signal CNT_IIn this example,
Of isolated points of "H" indicating that the ACC circuit of FIG.
Output signal IS; otherwise, "L" isolated point
A removal signal IS is output. FIG. 6 shows a specific configuration of the determination circuit 65.
Show. In FIG. 6, an input terminal of the determination circuit 65
51 has an inner core control signal CNT._IIs supplied to the input end
The outer core control signal CNT is_OIs supplied. Up
The input terminal 51 is one input of an exclusive OR gate 53.
And the input terminal 52 is connected to the exclusive OR.
It is connected to the other input terminal of the gate 53. Also,
The input terminal 51 is a two-input OR gate (OR gate).
G) is also connected to one of the input terminals of the
52 is also connected to one input terminal of a two-input OR gate 55.
Has been continued. The output of the exclusive OR gate 53 is
The input terminal is connected to the other input terminal of the OR gate 55.
And the output A from the OR gate 54 is
It is supplied to one of the selected terminals and output from the OR gate 55.
Selection of the selector 56 in which the force B is supplied to the other selected terminal.
The selection control signal input terminal SW is also connected. The selector 56 is connected to the exclusive OR gate.
The output of the port 53 is supplied as the selection control signal S, and
Therefore, the output A and the output A are output in accordance with the selection control signal S.
B is switched. The output of this selector 56 is delayed
The other input terminal of the OR gate 54 via the element 57
And output as the core switching signal SEL.
Output from the force terminal 58. That is, the judgment circuit 65 shown in FIG.
In the above, the operation of Table 1 described above is performed by the above configuration.
You. In other words, the operation of the determination circuit 65 is first
First, before the inner coring circuit 62, the outer core
Core in the switching circuit 64 (ie, the outer core
Control signal CNT_OIs "H" even if the inner core control signal
CNT_ISwitching of coring circuit until becomes "H"
Second, the inner coring circuit 6
After the core in step 2, the outer coring circuit 63 is disconnected.
Until the core in the outer coring circuit 64 comes off.
To maintain this state (ie, the outer core control signal C
NT_OUntil it becomes "L")
Third, the core in the outer coring circuit 64 has come off.
Are returned to the first state. FIG. 7 shows the double core phosphorus according to the embodiment of the present invention.
Another specific configuration of the block 29 is shown. That is, before
The double coring block 29 of FIG.
While having a ring circuit, the double circuit shown in FIG.
In the coring block 29, the inner coring process is performed.
Core level C for science_IData and outer coring process
Core level C for_OData and the inner core
Reference holding means 74 and outer core reference holding means
With the holding means 74 and 75
Core Level C_IAnd core level C_OSwitch data
Switched by switch 76, core input via input terminal 71
(X) is sent to the coring circuit 72 to be supplied.
It is a thing. Further, the switching control by the switch 76 is performed.
The core is cut from the coring circuit 72 as described above.
This is performed by the exchange signal SEL. Coring circuit 72
From the output terminal 73 as the core output (y)
Is forced. Although illustration is omitted, FIG.
The configuration includes an outer core when the transient response is in the process of converging.
There is also a circuit that prevents convergence during the
You. As described above, the digital closing of this embodiment is
In a loop circuit, external noise and quantization noise
Transient response converges once for unstable elements in closed loop system
After the core in the inner coring circuit 62
The outer coring circuit 64 having a larger core level.
By switching, a more stable state can be obtained
It has become. That is, as a digital closed loop circuit
For example, negative circuits such as ACC and AGC circuits of television
Double feedback as described above in the feedback loop feedback system
By providing the coring block 29, transient response
Is stable against external noise and quantization error after
A stable state can be obtained. Further, according to this embodiment, a single core
Core level can be made smaller than when using a
Therefore, the offset becomes small. It should be noted that the double coring block as in this embodiment is used.
In the lock 29, the output of the block 29 is “0”.
Sometimes, the output of the integrator 27 is completely unchanged.
It is only valid for integrators, and
It can be applied to any system. [0053] As described above, the digital closure of the present invention is
In a loop circuit, input signals in the first level range
To generate a constant level output signal and
Input signal level and input signal levelThe first
Approximately proportional to the difference from the threshold that defines the bell rangeOf level
First coring means for generating an output signal;
A second range that includes the bell range and is wider than the first level range
Output signal of constant level for input signal of level range
Input signal that is generated and is out of the second level range.
With the level of the force signalWith a threshold value defining a second level range
Almost proportional to the differenceA second connector that generates a level output signal
Alling means,A certain level from the first coring means
To determine whether or not the output signal is output continuously for a predetermined time.
Convergence determining means for determining
Input, the output signal of the first coring means or the
Either the output signal of the second coring means is fed.
Switching control means for outputting to the backup path;To have
After the transient response converges in the closed loop system,
Stable without being affected by local noise or quantization noise
It is possible to get the state that was.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block circuit diagram showing a schematic configuration of an ACC circuit as a digital closed loop circuit according to an embodiment of the present invention. FIG. 2 is a diagram illustrating a coring process. FIG. 3 is a diagram for explaining a double coring block of the digital closed loop circuit of the present embodiment. FIG. 4 is a block circuit diagram showing a specific configuration of a coring circuit. FIG. 5 is a block circuit diagram showing a specific configuration of an isolated point removing circuit. FIG. 6 is a block circuit diagram showing a specific configuration of a determination circuit. FIG. 7 is a block circuit diagram showing another example of a double coring block. FIG. 8 is a block circuit diagram showing a schematic configuration of an ACC circuit as an example of a conventional digital closed loop circuit. [Description of Signs] 23... Multiplier 25... Level detection circuit 26... Adder 28... Level reference value generation circuit 27. ... Double coring block 62... Inner coring circuit 63... Isolated point removing circuit 64... Outer coring circuit 65... Determination circuit 66. ····selector

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 9/68 H04N 5/21

Claims (1)

(57) [Claim 1] In a digital closed loop circuit having a closed loop by providing a feedback path, an output signal of a constant level is generated for an input signal in a first level range, and For input signals other than the first level range, the input signal level and the first level range
First coring means for generating an output signal having a level substantially proportional to a difference from a threshold value to be defined; and an input signal having a second level range including the first level range and being wider than the first level range. Output signal of a fixed level with respect to the input signal level, and the input signal level and the second level
A second coring means for generating an output signal having a level substantially proportional to a difference from a threshold value defining a bell range; and a constant level output signal from the first coring means.
Convergence judgment to determine whether output is continued for a predetermined time
A constant unit inputs an output signal from said convergence judgment means, said first
The output signal of the coring means or the second coring
One of the output signals of the
Digital closed loop circuit; and a switching control means for force.