JPH04167665A - Picture input device - Google Patents

Abstract

PURPOSE:To display an arbitrary reduction picture without degrading the picture quality of an original picture by executing the low-pass frequency compensation in the subscanning direction on a linear image sensor and executing it in the main scanning direction by a digital filter. CONSTITUTION:A linear image sensor 9 outputs stored picture data to perform the low-pass frequency compensation in the subscanning direction every time the timing signal is received from a subscanning address processing part 8. A digital filter 10 not only counts the pixel clock of picture data but also adds the output of the linear image sensor 9 synchronously with the pixel clock till reception of the timing signal from a main scanning address processing part 7 and generates display data based on the addition result and the counted value of the pixel clock to perform the low-pass frequency compensation in the main scanning direction. Thus, the picture is reduced and displayed without degrading the picture quality of the original picture.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image input device that reduces and displays image data input from a wide area in a limited display area.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional image input device.

In the figure, reference numeral 1 denotes a scanning address processing section that generates a timing signal every time the scanning address of input image data becomes a multiple of a predetermined addition address. Reference numeral 2 denotes an extractor for extracting display data from input image data according to the timing signal from the scanning address processing section 1; This is a frame memory that stores the display data extracted.

Further, 4 is a latch buffer that stores a predetermined addition address given from the outside, and 5 is a latch buffer that sequentially adds the addition address stored in this latch buffer 4 to its own output and compares it every time it receives a control signal. This is an adder that generates addresses. 6 compares the scanning address of the input image data with the addition result of this adder 5, and when a match is detected, it gives a control signal to the adder 5, and the extractor 2
and a comparator that generates a timing signal to the frame memory 3.

The scanning address processing section 1 includes these latch buffers 4,
It consists of an adder 5 and a comparator 6.

Next, the operation will be explained. In the scanning address processing unit 1, a predetermined addition address set from an external processing device (hereinafter referred to as CPU), etc., not shown, is stored in a latch buffer 4, and its output is sent to one input terminal of an adder 5. It is connected.

Further, the adder 5 sends its output to its other input terminal and to the comparator 6. Scanning addresses including main scanning and sub-scanning of input image data are input to this comparator 6. The comparator 6 compares this scan address with the comparison address calculated by the adder 5, and if they match, it sends a control signal to the adder 5 and also sends a control signal to the extractor 2 outside the scan address processing section 1. and sends a timing signal to the frame memory 3.

At this time, the extractor 2 uses a charge-coupled device (hereinafter referred to as CCD) (not shown) or a near image sensor to read and digitize the data according to the timing signal from the comparator 6 of the scan address processing section 1. Display data is extracted from the sent image data and sent to the frame memory 3. The frame memory 3 stores the display data extracted by the extractor 2 in accordance with the timing signal from the comparator 6.

On the other hand, in the scanning address processing section 1, the adder 5 is connected to the comparator 6.
In response to a control signal from the latch buffer 4, the add address stored in the latch buffer 4 is added to the currently output comparison address, and the added address is sent to the comparator 6 as a new comparison address. Thereafter, by repeating the above-mentioned process, the input image data is thinned out at intervals indicated by the set addition address, stored in the frame memory 3, and then outputted to a display means (not shown) to reduce the size. It is possible to display image data.

[Problem to be solved by the invention]

Conventional image input devices are configured as described above, so even if the image has low frequency components, depending on the thinning interval, the frequency components of the image may increase to the sampling frequency component, resulting in poor image quality. The problem was that it deteriorated significantly.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an image input device capable of reducing and displaying input image data without deteriorating the image quality of the original image.

[Means to solve the problem]

The image input device according to the present invention divides the scanning address processing section into a main scanning address processing section and a sub-scanning address processing section, and stores image data each time a timing signal is received from the sub-scanning address processing section. Until the timing signal is received from the output linear image sensor and the main scanning address processing unit, the linear image sensor outputs are added in synchronization with the pixel clock and the pixel clock is counted, and based on the addition result and the counted value. It is equipped with a digital filter that generates display data.

[For production]

The linear image sensor according to the present invention performs low frequency compensation in the sub-scanning direction by outputting the accumulated image data every time a timing signal is received from the sub-scanning address processing section, and the digital filter is arranged in the main-scanning address processing section. Until the timing signal is received from the pixel clock, the pixel clock of the image data is counted, and the output of the linear image sensor is added in synchronization with the pixel clock, and the display data is displayed based on the addition result and the counted value of the pixel clock. By generating the image and performing low frequency compensation in the main scanning direction, an image input device that can perform reduced display without deteriorating the image quality of the original image is realized.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 3 is a frame memory equivalent to the conventional one. 7 is a main scanning address processing unit that generates a timing signal every time the main scanning address of the input image data becomes a multiple of a predetermined main scanning addition address, and 8 is a main scanning address processing unit that generates a timing signal every time the main scanning address of the input image data becomes a multiple of a predetermined main scanning addition address; This is a sub-scanning address processing unit that generates a timing signal every time the sub-scanning addition address becomes a multiple of the sub-scanning addition address. The main scanning address processing section 7 and the sub-scanning address processing section 8 are composed of a latch buffer 4, an adder 5, and a comparator 6, similar to the conventional scanning address processing section 1.

A CCD linear image sensor 9 outputs the accumulated image data each time it receives a timing signal from the sub-scanning address processing section 8. 10
counts the pixel clocks of the image data until it receives the next timing signal from the main scanning address processing unit 7, adds the outputs of the linear image sensor 9 in synchronization with the pixel clocks, and calculates the addition result and This is a digital filter that generates display data based on the count value and outputs it to the frame memory 3.

Further, FIG. 2 is a block diagram showing the configuration of this digital filter 10. In the figure, reference numeral 11 denotes an adder that sequentially adds the outputs of the linear image sensor 9 in synchronization with the pixel clock, and its contents are cleared when it receives a timing signal from the main scanning address processing section 7. Reference numeral 12 denotes a counter that counts the pixel clock and is similarly reset when the main scanning address processing section 7 receives a timing signal. 13 is a read-only memory table (hereinafter referred to as "read-only memory table") which uses the addition result of the adder 11 and the count value of the counter 12 as addresses, reads out the value obtained by dividing the above-mentioned addition result by the count value, and outputs it to the frame memory 3 as display data. , ROM table).

Next, the operation will be explained. In the main scanning address processing section 7, a predetermined main scanning addition address set by a CPU (not shown) or the like is stored in its latch buffer 4, and its output is connected to one input terminal of an adder 5.

Further, the adder 5 sends its output to its other input terminal and to the comparator 6. The comparator 6 compares the main scanning address of the input image data with the comparison address output from the adder 5, and if they match, sends a control signal to the adder 22 to execute the next addition. At the same time, a timing signal is sent to the digital filter 10 and frame memory 3.

On the other hand, in the sub-scanning address processing section 8, a predetermined sub-scanning addition address set by the CPU or the like is stored in its latch buffer 4, and operates in the same way as the main scanning address processing section 7, and its own adder 5 and a timing signal to the linear image sensor 9. When the linear image sensor 9 receives a timing signal from the comparator 6 of the sub-scanning address processing section 8, it transfers the charge signal of the accumulated image data to an internal shift register. This charge signal is analog-to-digital converted on the way and transmitted to the digital filter 10.

In the digital filter 10, the output of the linear image sensor 9 is input to an adder 11. The adder 11 is cleared by a timing signal output from the comparator 6 of the main scanning address processing section 7 every time the address data match, but in the meantime, that is, after writing one piece of image data to the frame memory 3, the next one is cleared. Until the image data of
Send to 3. Further, the counter 12 counts the pixel clocks at the same intervals as the adder 11 and sends the counted value to the ROM table 13. In the ROM table 13, the addition result from the adder 11 and the count value of the counter 12 are input as addresses,
The addition result of the adder 11 is converted into a value divided by the count value of the counter 12, and the result is output to the frame memory 3 as display data.

〔Effect of the invention〕

As described above, according to the present invention, the low frequency compensation in the sub-scanning direction is realized on the linear image sensor, and the low-frequency compensation in the main scanning direction is realized by the digital filter. Compensation is performed in two dimensions, making it possible to display any reduced image without degrading the image quality of the original image, and furthermore, providing an inexpensive image input device with a simple circuit configuration. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an image input device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a digital filter thereof, and FIG. 3 is a block diagram showing a conventional image input device. 3 is a frame memory, 7 is a main scanning address processing section, 8 is a sub-scanning address processing section, 9 is a linear image sensor, 1
0 is a digital filter. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant Mitsubishi Electric Corporation

Claims (1)

[Claims] a main scanning address processing unit that generates a timing signal every time the main scanning address of input image data becomes a multiple of a predetermined main scanning addition address; a sub-scanning address processing unit that generates a timing signal every time the address is a multiple of the address; a linear image sensor that outputs the image data accumulated each time it receives a timing signal from the sub-scanning address processing unit; Until a timing signal is received from the address processing section, the pixel clocks of the image data are counted, and the output of the linear image sensor is added in synchronization with the pixel clock, and the addition result and the counted value of the pixel clock are added. An image input device comprising: a digital filter that generates display data based on the digital filter; and a frame memory that stores the display data output from the digital filter.