JPH04165843A - Communication controller - Google Patents

Communication controller

Info

Publication number
JPH04165843A
JPH04165843A JP2292910A JP29291090A JPH04165843A JP H04165843 A JPH04165843 A JP H04165843A JP 2292910 A JP2292910 A JP 2292910A JP 29291090 A JP29291090 A JP 29291090A JP H04165843 A JPH04165843 A JP H04165843A
Authority
JP
Japan
Prior art keywords
line
connection
information
buffer memory
adapters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2292910A
Other languages
Japanese (ja)
Inventor
Kazuo Kobayashi
和夫 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Engineering Ltd
Original Assignee
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Engineering Ltd filed Critical NEC Engineering Ltd
Priority to JP2292910A priority Critical patent/JPH04165843A/en
Publication of JPH04165843A publication Critical patent/JPH04165843A/en
Pending legal-status Critical Current

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  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To reduce conventional man-hour to connect plural cables with manual work by providing a storage part storing the control information of a connection between a line control part and a line adapter(LA), and a line terminating circuit recognizing connection information from the storage part and switching the connection between the LA and a line control part. CONSTITUTION:This device is constructed by a buffer memory 1, a line terminating circuit 3 storing line adapters LA 4, 5 and 6, and a line control part 2 controlling the buffer memory 1, the line terminating circuit 3 and the whole device by a bus 10 and a signal 11. The buffer memory 1 stores the control information for the construction and the connection of transmitting data/ receiving data, the addresses of the LA 4, 5 and 6, and the like. The line terminating circuit 3 is equipped with a line changeover parts 21 and 22, and drivers 23-28. The construction of the LA 4, 5 and 6 and the information of the addresses of the LA 4, 5 and 6 stored in advance are read out from the buffer memory 1 through a signal line 18 by a recognition part 20. The recognition part 20 switches the connection of the LA 4, 5 and 6 from the read information by the line changeover parts 21 and 22.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は通信制御装置に関し、特に複数の回線アダプタ
を収容する通信制御装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a communication control device, and particularly to a communication control device accommodating a plurality of line adapters.

〔従来の技術〕[Conventional technology]

従来、この種の通信制御装置は、複数の回線アダプタ(
以下LA)を制御するための回線制御部との接続にケー
ブルを使用し、LAの精成を変更するときには、ケーブ
ルの接続を手動で変更していた。
Conventionally, this type of communication control device has multiple line adapters (
A cable is used to connect to a line control unit for controlling the LA (hereinafter referred to as LA), and when changing the refinement of the LA, the cable connection is manually changed.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の通信制御装置は、複数のLAを制御する
のに回線制御部との接続にケーブルを使用して接続し、
LAの精成を変更するときには、いちいちケーブルを手
動で接続し直さなければならないので、人手による工数
がかかるという欠点がある。
The conventional communication control device described above uses a cable to connect to a line control unit to control multiple LAs, and
When changing the LA refinement, the cables must be manually reconnected each time, which has the disadvantage of requiring a lot of manual labor.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の通信制御装置は、複数の回線アダプタを収容す
る通信制御装置において、回線制御部と前記複数の回線
アダプタのとの間を接続する接続情報を予め記憶する記
憶部と、回線終端回路とを備え、前記回線終端回路は、
前記記憶部から前記複数の回線アダプタの前記接続情報
を読出して認識する認識部と、この認識部からの指示に
より前記回線制御部と前記複数のアダプタとの間の接続
を切り替える接続切替部とを有している。
A communication control device of the present invention is a communication control device that accommodates a plurality of line adapters, and includes a storage unit that stores connection information for connecting a line control unit and the plurality of line adapters in advance, and a line termination circuit. The line termination circuit comprises:
a recognition unit that reads and recognizes the connection information of the plurality of line adapters from the storage unit; and a connection switching unit that switches connections between the line control unit and the plurality of adapters according to instructions from the recognition unit. have.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.

第1図において、本実施例はバッファメモリ1と、回線
アダプタ(以下LA)4,5.6を収容する回線終端回
路3と、バス10および信号11でバッファメモリ1お
よび回線終端回路3並びに本実施例全体を制御する回線
制御部2とを有して構成している。
In FIG. 1, this embodiment includes a buffer memory 1, a line termination circuit 3 accommodating line adapters (hereinafter referred to as LA) 4, 5, 6, a bus 10 and a signal 11, The system includes a line control section 2 that controls the entire embodiment.

バッファメモリ1は、送信データ/受信データ及びLA
4,5.6アドレス等の構成及び接続のための制御情報
を格納するメモリである。
Buffer memory 1 stores transmit data/receive data and LA
4, 5.6 A memory that stores control information for configuration and connection such as addresses.

回線制御部2は、回線終端回路3を介して信号線15〜
17からの割込み処理によるデータ転送を制御する。
The line control unit 2 connects the signal lines 15 to 15 through the line termination circuit 3.
Controls data transfer by interrupt processing from 17.

回線終端回路3は、回線制御部1とLA4,5゜6の接
続を制御する。
The line termination circuit 3 controls the connection between the line control section 1 and the LAs 4 and 5.6.

LA4〜6は、伝送制御手順の制御を行い、処理要求を
回線終端回路3を介して回線制御部2へ通知する。
The LAs 4 to 6 control transmission control procedures and notify the line control unit 2 of processing requests via the line termination circuit 3.

第2図は第1図内の回線終端回路の一例を示すブロック
図である。
FIG. 2 is a block diagram showing an example of the line termination circuit in FIG. 1.

第2図において、回線終端回路3は認識部20と、回線
切換部21.22と、ドライバ23〜28とを有して構
成している。
In FIG. 2, the line termination circuit 3 includes a recognition section 20, line switching sections 21, 22, and drivers 23-28.

認識部20は、バッファメモリ1からLA4゜5.6の
構成とLA4,5.6のアドレスの情報を認識し、回線
切換部21.22に指示を出す。
The recognition unit 20 recognizes the configuration of LA4°5.6 from the buffer memory 1 and the address information of LA4, 5.6, and issues an instruction to the line switching unit 21.22.

また、ドライバ23〜28を送信、受信時の状態により
切り換える。
Further, the drivers 23 to 28 are switched depending on the state at the time of transmission and reception.

回線切換部21.22は、送信時処理要求が受は付けら
れたLAの接続を切り換える。
The line switching units 21 and 22 switch the connection of the LA to which the transmission processing request has been accepted.

ドライバ23〜25は、送信状態の時イネーブルとなり
、受信状態の時ハイインピーダンスとなる。また、ドラ
イバ26〜28は、送信状態の時ハイインピーダンスと
なり、受信状態の時イネーブルとなる。
The drivers 23 to 25 are enabled when in the transmitting state, and have high impedance when in the receiving state. Further, the drivers 26 to 28 have high impedance when in the transmitting state, and are enabled when in the receiving state.

次に、本実施例の動作について第1図、第2図を併用し
て説明する。
Next, the operation of this embodiment will be explained using FIG. 1 and FIG. 2 together.

予め記憶されているLA4,5.6の構成とLA4,5
.6のアドレスの情報がバッファメモリ1から信号線1
8を介して認識部2oによって読取られる。認識部20
は、読取った情報から回線切換部21.22によりLA
4,5.6の接続を切り換える。
Pre-stored configuration of LA4, 5.6 and LA4, 5
.. The information at address 6 is transferred from buffer memory 1 to signal line 1.
8 and is read by the recognition unit 2o. Recognition unit 20
The line switching units 21 and 22 select LA from the read information.
4. Switch the connections in 5.6.

次に、本実施例における送信時の動作をLA6からの処
理要求を例に説明する。まず、認識部20はバッファメ
モリ1からの情報によって回線切換部21.22をLA
6の方向へ切り換える。そして、ドライバ25をイネー
ブル、ドライバ28をハイインピーダンスに切り換え、
信号線11゜回線切換部21.信号線30.回線切換部
22゜信号線31.ドライバ25.信号!14.回線ア
ダプタ6の順序でデータが転送され、回線17へ送出さ
れる。
Next, the operation at the time of transmission in this embodiment will be explained using a processing request from the LA 6 as an example. First, the recognition unit 20 switches the line switching units 21 and 22 from LA to LA based on information from the buffer memory 1.
Switch to direction 6. Then, enable the driver 25, switch the driver 28 to high impedance,
Signal line 11° line switching section 21. Signal line 30. Line switching section 22° signal line 31. Driver 25. signal! 14. Data is transferred in the order of line adapter 6 and sent to line 17.

次に、本実施例における受信号の動作をLA4からの処
理要求を例に説明する。愛す、認識部20はバッファメ
モリ1がらの情報によってドライバ23をハイインピー
ダンス、ドライバ26をイネーブルに切り換え、LA4
.信号線12.ドライバ26.信号線11の順序で信号
線15がらのデータが転送される。
Next, the operation of the received signal in this embodiment will be explained using a processing request from LA4 as an example. The recognition unit 20 switches the driver 23 to high impedance and the driver 26 to enable based on the information from the buffer memory 1, and switches LA4 to
.. Signal line 12. Driver 26. Data from the signal lines 15 is transferred in the order of the signal lines 11.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、回線制御部とLAとの間
の接続の制御情報を記憶する記憶部と、記憶部からの接
続情報を認識してLAと回線制御部との接続を切り換え
る回線終端回路とを有することにより、従来のような複
数のケーブルの人手による接続する工数を削減すること
が出来る効果がある。
As explained above, the present invention includes a storage unit that stores control information for connection between a line control unit and an LA, and a line that recognizes connection information from the storage unit and switches the connection between the LA and the line control unit. By having a termination circuit, it is possible to reduce the number of man-hours required for manually connecting a plurality of cables as in the conventional method.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロック図、第2図は
第1図内の回線終端回路の一例を示すブロック図である
。 1・・・バッファメモリ、2・・・回線制御部、3・・
・回線終端回路、4〜6・・・回線アダプタ(LA)、
10・・・バス、11〜18・・・信号線、20・・・
認識部、21〜22・・・回線切換部、23〜28・・
・ドライバ、30〜31・・・信号線、40〜43・・
・信号線。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of the line termination circuit in FIG. 1... Buffer memory, 2... Line control section, 3...
・Line termination circuit, 4 to 6...Line adapter (LA),
10...Bus, 11-18...Signal line, 20...
Recognition unit, 21-22... Line switching unit, 23-28...
・Driver, 30-31...Signal line, 40-43...
·Signal line.

Claims (1)

【特許請求の範囲】[Claims] 複数の回線アダプタを収容する通信制御装置において、
回線制御部と前記複数の回線アダプタのとの間を接続す
る接続情報を予め記憶する記憶部と、回線終端回路とを
備え、前記回線終端回路は、前記記憶部から前記複数の
回線アダプタの前記接続情報を読出して認識する認識部
と、この認識部からの指示により前記回線制御部と前記
複数のアダプタとの間の接続を切り替える接続切替部と
を有することを特徴とする通信制御装置。
In a communication control device that accommodates multiple line adapters,
A storage section that stores in advance connection information for connecting between a line control section and the plurality of line adapters, and a line termination circuit, wherein the line termination circuit connects the connection information of the plurality of line adapters from the storage section to the connection information of the plurality of line adapters. A communication control device comprising: a recognition unit that reads and recognizes connection information; and a connection switching unit that switches connections between the line control unit and the plurality of adapters based on instructions from the recognition unit.
JP2292910A 1990-10-30 1990-10-30 Communication controller Pending JPH04165843A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2292910A JPH04165843A (en) 1990-10-30 1990-10-30 Communication controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2292910A JPH04165843A (en) 1990-10-30 1990-10-30 Communication controller

Publications (1)

Publication Number Publication Date
JPH04165843A true JPH04165843A (en) 1992-06-11

Family

ID=17787986

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2292910A Pending JPH04165843A (en) 1990-10-30 1990-10-30 Communication controller

Country Status (1)

Country Link
JP (1) JPH04165843A (en)

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