JPH04165801A - Differential amplifier circuit - Google Patents

Abstract

PURPOSE:To decrease an input capacity drastically, and to realize a low noise simultaneously by connecting a capacitor respectively between a pair of input terminals and a pair of output terminals outputting an in-phase signal with the input terminals, and selecting the value of the capacitor so that the value of an output terminal voltage divided by the capacitor and the input capacity becomes equal to an input terminal voltage. CONSTITUTION:The one end of a constant current source 12 is connected to the emitters of input transistors 6 and 7 commonly, and the other end is connected to the (-) side of a constant current source 13. The emitters of transistors 8 and 9 are connected to the collectors of the transistors 6 and 7 respectively. The (+) side and the (-) side of a constant current source 15 are connected to the bases of the transistors 8 and 9. A capacitor 17 is connected between the base of the transistor 7 and the collector of the transistor 8, and a capacitor 18 is connected between the base of the transistor 6 and the collector of the transistor 9. Here, the emitter size of the input transistors 6 and 7 is made bigger, a base resistance is reduced, and the noise is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a differential amplifier circuit, and more particularly to a differential amplifier circuit used in a sense amplifier of a magnetic file device.

[Conventional technology]

Conventionally, in differential amplifier circuits used in sense amplifiers and the like of magnetic file devices, as the recording density increases, the signal input to the sense amplifier decreases, so it is necessary to reduce the noise of the amplifier.

Also, as the recording density increases, the signal frequency becomes wider, so in order to bring the resonant frequency determined by the inductance connected to the input terminal of the amplifier to a wider range,
It is necessary to reduce the input capacitance of the amplifier.

FIG. 5 is a differential amplifier circuit diagram showing an example of such a conventional system.

As shown in FIG. 5, the conventional differential amplifier circuit has input terminals 2 and 3 connected to both ends of an inductance 1, respectively.
, resistors 4 and 5 whose one end is connected to input terminals 2 and 3, respectively, and whose other end is grounded, and an input quadrant transistor and 7 whose bases are connected to input terminals 2 and 3, respectively, and whose emitters are connected to each other. A low voltage source 13 whose + side is grounded, a low current source 12 whose one end is connected to the emitters of the transistors 6 and 7 and whose other end is connected to one side of the low voltage source 13, and the collectors of the transistors 6 and 7. Transistors 8 and 9, each with its emitter connected
, a low voltage source 15 whose + side is connected to the bases of transistors 8 and 9 and whose one side is grounded, and transistor 8.
and a resistor 1 whose one end is connected to the collector of 9
0 and 11, and a low voltage source 14 whose + side is connected to the other ends of resistors 10 and 11, and output terminals 19 and 20 connected to the collectors of transistors 8 and 9 are connected to the next stage input circuit 16, respectively. It is connected.

In such a differential amplifier circuit, transistors 6 and 7
constitutes an input stage of a differential amplifier circuit, and transistors 8 and 9 are connected in cascode. This transistor 8
and 9 are connected in cascode to prevent an increase in input capacitance due to the Miller effect. Furthermore, by making the collector-to-substrate capacitance of transistors 8 and 9 smaller than the collector-to-substrate capacitance of input quadrant transistors and 7, it is possible to widen the band of the amplifier. This is because the input quadrant transistors and transistors 7 need to have low base resistance in order to reduce the noise of the amplifier, and are often made with a multi-emitter structure, which increases the capacitance between the collector and the substrate. 9 because there is no need for it.

As described above, in any case, reducing the noise of the amplifier and reducing the input capacitance of the amplifier both add weight to the differential amplifier circuit.

[Problem to be solved by the invention]

The conventional differential amplifier circuit described above has a drawback in that it is not possible to achieve both at the same time because there is a trade-off between reducing the input capacitance of the amplifier and reducing input noise. In other words, if an attempt is made to reduce the base resistance by increasing the emitter area of the input transistor in order to reduce noise, the base-emitter capacitance and base-collector capacitance of the input transistor will increase, which will increase the input capacitance of the amplifier. I end up.

SUMMARY OF THE INVENTION An object of the present invention is to provide a differential amplifier circuit that can simultaneously achieve low input capacity and low noise, which are necessary for increasing the recording density of such magnetic file devices.

[Means to solve the problem]

In the differential amplifier circuit of the present invention, a capacitor is connected between a pair of input terminals and a pair of output terminals that output a signal in phase with the input terminals, and the output terminal voltage is divided by the capacitor and the input capacitance. is configured to select the value of the capacitor such that is equal to the input terminal voltage.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a differential amplifier circuit diagram showing a first embodiment of the present invention.

As shown in FIG. 1, this embodiment has input terminals 2 and 3 connected to an inductance 1, resistors 4 and 5 whose one end is connected to the input terminals 2 and 3, and the other end is grounded, and the input terminal An input quadrant transistor for differential input whose bases are connected to 2 and 3, respectively, and whose emitters are connected to each other, and 7, and a constant voltage source 1 whose + side is grounded.
3, a constant current source 12 whose one end is commonly connected to the emitters of the input quadrant transistors and 7, and whose other end is connected to one side of the constant voltage source 13, and whose emitters are connected to the collectors of the transistors 6 and 7, respectively. transistors 8 and 9, a constant voltage source 15 whose positive side is connected to the bases of upper transistors 8 and 9 and whose one side is grounded, and resistors 10 and 11 whose one ends are connected to the collectors of transistors 8 and 9, respectively. , a constant voltage source 14 whose + side is commonly connected to the other ends of the resistors 10 and 11 and whose one side is grounded, a capacitor 17 connected between the base of the transistor 7 and the collector of the transistor 8, and the transistor 6.
and a capacitor 18 connected between the base of the transistor 9 and the collector of the transistor 9.

FIGS. 2(a) and 2(b) are an equivalent circuit diagram and a half thereof, respectively, as viewed from the input terminal shown in FIG. 1.

As shown in Figure 2(a), this equivalent circuit is
When alternating current (AC) signals are applied from signal sources 21 and 22 connected to transistors 9 and 3, respectively, an amplified signal is output to the collectors of transistors 9 and 8, that is, output terminal 20.19. Signal sources 25 and 2
6 on the surface. Here, capacitors 17 and 18
is the capacitor shown in FIG. 1, and capacitors 23 and 24 are input capacitors. Such an equivalent circuit can be divided into two circuits that differ only in signal polarity.

As shown in FIG. 2(b), the − side circuit (half circuit) in FIG. 2(a) has a signal source of The voltage of 25 is Gv
・■ Becomes 1. In addition, the input capacitance of the differential amplifier circuit is C1,
, then the capacitance of the capacitor 23 is 2C,ゎ.
Here, the capacitance of capacitor 18 is Cp, and the voltage divided by capacitors 18 and 23 is v2.
Then, ■2 becomes the following margin 2C1-CF CF , and ■2 becomes equal to the voltage Vl of the signal source 21. This means that no current flows from the signal source 21 to the input capacitor 23, and this is the same as if the input capacitance became 0 when looking at the differential amplifier circuit from the input terminal 2.

FIG. 3 is a frequency/input capacitance characteristic diagram representing a simulation result of the circuit shown in FIG. 1.

As shown in FIG. 3, the characteristic A shown by the solid line is the simulation result of the present embodiment, and the characteristic B shown by the dotted line is the simulation result of each input capacitance of the conventional example. According to this, the gain Gv of the differential amplifier circuit
is 70, and the input capacitance C1m is 28PF, so from equation (1) above, the capacitance ICp of the capacitor 18 is: 2C+- C,= , = 0.81pF
Therefore, in this embodiment, the value of capacitors 17 and 18 is set to 0.8 pF for simulation. That is, in this embodiment, the input capacitance is 1/10 or less of the conventional example at frequencies below 28 MHz, and low input capacitance can be realized. Note that when the frequency exceeds 28 MHz, the input capacitance increases rapidly, but this is because as the frequency increases, the phases of the signal sources 21 and 25 shift due to the phase lag on the collector side of transistors 8 and 9. The reason for this is that this embodiment works as a low input capacitance amplifier circuit for signals of 28 MHz or less. Therefore, by increasing the emitter size of the input quadrant transistor and 7 and reducing the base resistance, noise can be reduced, and the input capacitance can be prevented from increasing due to this, so this embodiment can reduce the input capacitance. and input noise reduction can be achieved at the same time.

FIG. 4 is a differential amplifier circuit diagram showing a second embodiment of the present invention.

As shown in FIG. 4, this embodiment is compared with the embodiment shown in FIG.
and 9 and the constant voltage source 15 are omitted, and the input quadrant transistor and the collector of 7 are each resistor 1.
0 and 11 directly connected to one end. The second difference is that there are no resistors 4 and 5, which have one end connected to input terminals 2 and 3 and the other end grounded.
A resistor 27 is connected between the input terminals 2 and 3, and a constant voltage source 28 is connected to the midpoint of the inductance 1. Such cascode connected transistors 8 and 9
Even if there is no, by determining the capacitance of capacitors 17 and 18 based on equation (1) as in the first embodiment,
Input capacitance and noise can be reduced.

〔Effect of the invention〕

As explained above, the differential amplifier circuit of the present invention connects a capacitor between a pair of input terminals and an output terminal that outputs a signal in phase with the input terminals, and connects the output terminal voltage between the capacitor and the input capacitor. By selecting the value of the capacitor so that the voltage divided by is equal to the input terminal voltage, it is possible to significantly reduce the input capacitance and achieve low noise at the same time.

[Brief explanation of the drawing]

FIG. 1 is a differential amplifier circuit diagram showing a first embodiment of the present invention,
Figures 2 (a) and (b) show an equivalent circuit diagram of the circuit shown in Figure 1 as seen from the input terminal, and an equivalent circuit diagram of half thereof, and Figure 3 shows the simulation results of the circuit shown in Figure 1. FIG. 4 is a differential amplifier circuit diagram showing a second embodiment of the present invention, and FIG. 5 is a differential amplifier circuit diagram showing a conventional example. 1... Inductance, 2.3... Input terminal, 4゜5.10, 11.27... Resistance, 6, 7... Input transistor, 8, 9... Cascode connection transistor, 12... ...Constant current source, 13-15.28...Constant voltage source, 17.18...Capacitor, 19.20...Output terminal.

Claims (1)

[Claims] 1. A capacitor is connected between a pair of input terminals and a pair of output terminals that output a signal in phase with the input terminals, and the value obtained by dividing the output terminal voltage by the capacitor and the input capacitance is A differential amplifier circuit characterized in that the value of the capacitor is selected to be equal to the input terminal voltage. 2. A first input terminal for differential input whose bases are connected to the first and second input terminals and whose emitters are connected to each other.
and a second transistor, a first constant voltage source having one end grounded, one end connected to the emitters of the first and second transistors, and the other end connected to the other end of the first constant voltage source. a constant current source, third and fourth transistors whose emitters are connected to the collectors of the first and second transistors, respectively, and whose bases are biased to a constant voltage; and collectors of the third and fourth transistors. first and second resistors each having one end connected to the
a second resistor commonly connected to the other ends of the first and second resistors;
In the differential amplifier circuit having a constant voltage source, the first
a first capacitor connected between the base of the transistor and the collector of the fourth transistor; and a second capacitor connected between the base of the second transistor and the collector of the third transistor. A differential amplifier circuit characterized by: 3. A first input terminal for differential input whose bases are connected to the first and second input terminals and whose emitters are connected to each other.
and a second transistor, a first constant voltage source having one end grounded, and a constant current having one end connected to the emitters of the first and second transistors and the other end connected to the first constant voltage source. first and second transistors each having one end connected to a source and a collector of the first and second transistors;
and a second constant voltage source commonly connected to the other ends of the first and second resistors, the base of the first transistor and the collector of the second transistor A differential amplifier circuit comprising a first capacitor connected between the base of the second transistor and a collector of the first transistor.