JPH04162824A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To warrant a Voh standard even when a power supply whose voltage is lower than 5V is desired to use by setting the threshold voltage of a pull-up MOSFET lower than the threshold voltage of a pull-down MOSFET. CONSTITUTION:An output circuit provided on an input output circuit section 2 is constituted of a push-pull output bufferBFF composed of two N-channel MOSFETs Q1, Q2 connected in series between power supply voltages Vdd, Vss, a logic G1 driving the pull-up side MOSFET Q1 and a logic gate G2 driving the pull-down MOSFET Q2. In this case, the threshold voltage of the pull-up side MOSFET Q1 is designed to be sufficiently lower than the threshold voltage of the pull-down side MOSFET Q2. Thus, a high level output is decreased from the power supply voltage. Thus, even when the power supply voltage is decreased less than +5V to prevent defective breakdown voltage for the circuit operation, a high level Voh being 2.4V(min) to be the interface condition of the TTL level or above is warranted.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit technology and a technology that is particularly effective when applied to an output buffer circuit in an MO3 integrated circuit. This paper relates to effective techniques for use in push-pull type output buffers.

[Prior Art] In a conventional CMO3 integrated circuit, the output buffer is generally composed of an inverter of a P-channel MO3FET and an N-channel MO6FET. However, the CMO3 configuration output buffer has a drawback in that latch-up is likely to occur due to external noise. Therefore, JP-A-58-71
As described in Japanese Patent No. 650, there is also an output buffer circuit configured with a push-pull circuit in which two N-channel MO8FETs are connected in series.

[Problems to be Solved by the Invention] As semiconductor process technology advances and devices become smaller, there is a problem in that the pressure resistance of elements decreases. In order to avoid this problem, it is expected that a lower power supply voltage such as 3V will be used instead of the 5V power supply voltage that has been used in the past. However, the interface specifications for signal transmission between LSIs are expected to remain at the TTL level. That is,
The high level Voh of the transmission signal is still required to be 2.4V or higher. However, in the push-pull type output buffer using the two N-channel MOSFETs described above, the output high level is a value lower than the power supply voltage Vdd by the threshold voltage Vth of the FET, and the power supply voltage Vdd decreases. As a result, the output level Voh4 naturally decreases.

As a result, when the power supply voltage Vdd becomes about 3V, it is no longer possible to guarantee the TTL level interface of 2.4V (min).

The purpose of the present invention is to enable a semiconductor integrated circuit device using an NMOS push-pull type output buffer to meet the V required by a TTL level interface even when using a power supply voltage lower than 5.
The objective is to provide technology that can guarantee the C+H standard.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In other words, in a push-pull output buffer consisting of two N-channel MOS FETs connected in series, the threshold voltage of the pull-up MO3FET connected to the high power supply voltage side is set to the threshold voltage of the pull-up MO3FET connected to the low power supply voltage side. For M
The threshold voltage is set lower than the threshold voltage of the OS FET.

[Function] According to the above-mentioned means, the threshold voltage of the MOSFET on the pull-up side is reduced, so that the high level of the output decreases less from the power supply voltage, and the power supply voltage can be lowered to prevent breakdown voltage failure. Even when operating at a voltage lower than +5V, it is possible to guarantee a high level ■Oh of 2.4V (min) or higher, which is a TTL level interface condition.

[Example] Hereinafter, an example of the present invention will be described using the drawings. 1st
The figure shows an example of the configuration of an output circuit portion of a CMO8 integrated circuit to which the present invention is applied.

The entire chip of a CMO8 integrated circuit can generally be divided into an internal logic circuit section 1 and an input/output circuit section 2, as shown in FIG. The internal logic circuit section 1 is composed of, for example, padded gates, and can constitute logics having various functions. The input/output circuit section 2 is arranged outside the internal logic circuit 1, that is, at the periphery of the chip, and a bonding pad 3 is provided on the outside.

The output circuit provided in the input/output circuit section 2 in FIG.
Push-pull type output buffer BFF consisting of T Ql and Q2 connected in series and MOSFET on the pull-up side
Logic gate G1 that drives Ql and M on the pull-down side
A logic gate G2 drives an OSFET Q2. Among these, the logic gate G2 is a CMOS transistor in which a PMOS transistor Q3 and an NMOS transistor Q4 are connected in series.
Consisting of a MOS inverter, PMOS transistor Q5
and NMO8h transistor Q6 are connected in series.
The signal of the logic gate Gl consisting of an inverter is inverted to drive the output MO3FETQ2 on the pull-down side. As a result, the output NMOS FETs Ql and Q2 are driven on and off in a complementary manner, and through current is prevented.

In the conventional technology, the threshold voltage Vth (Ql, ) of the pull-up side MOSFET Ql and the pull-down side M○5FET
The threshold voltage Vth (Q2) of Q2 was designed to have the same value.

In contrast, in this embodiment, the threshold voltage of MOSFET Ql is designed to be sufficiently lower than the threshold voltage of MOSFET Q2. The threshold value of the MOSFET can be controlled by setting the impurity concentration of the substrate by ion implantation.

That is, this characteristic can be easily obtained if ion implantation into the channel portion of MOSFET Ql is performed separately from ion implantation into Q2. Specifically, by lowering the impurity concentration in the channel portion of MOSFET Ql than the impurity concentration in the channel portion of MOSFET Q2, a low Vth can be achieved.
The following characteristics are obtained.

Next, let us consider the circuit operation of the Roka buffer configured as described above.

II HI! from the internal logic circuit section 1 to the output circuit. When the level signal a is supplied, the output signal of the inverter is “L”.
It becomes I+ level. Therefore, MOSFET Q1 is turned off. On the other hand, 'inverter G2 receives the output signal S of G1 and inverts it, so that its output signal C is brought to the 'I H++ level. This turns on MOSFET G2. Therefore, the output terminal OUT is changed to low level Vol. At this time, current is extracted from the capacitive load CL connected to the output terminal OUT through the MOSFET G2.

Next, when the signal a of the "LI+ level" is received from the internal logic circuit, the output signal of the inverter G1 becomes "H+ level". MOSFET Ql is therefore turned on. on the other hand,
Inverter G2 receives the output signal of Gl and inverts it, so that its output signal C is set to the if L n level. This turns off MOS FETQ2. Therefore, the output terminal OUT is changed to high level Voh.

At this time, current flows from the output terminal 0tJT to the capacitive load CL through the turned-on MOSFET Ql.

The dependence of this high level Voh on the power supply voltage Vdd is shown in FIG. The solid line A is the characteristic of the output buffer of this embodiment, and the dashed-dotted line B is the characteristic of the conventional output sofa in which the thresholds of MOSFETs Ql and G2 are the same.

By the way, it is known that the threshold voltage of a MOSFET depends on the substrate bias voltage vb.

The relationship is shown in FIG. Since the source of MOSFET G2 is at GND level (Vss), the substrate bias voltage is zero. The threshold value at this time is Vthl
(G2). Similarly, NMOSFET Ql
Since the source of is the output voltage, Vohl becomes the substrate bias voltage in the output high level state. Therefore,
Threshold value Vthl (Ql) of MOSFET Ql
becomes higher than the threshold value Vthl (G2) of G2. However, MOSFET G2 requires a sufficient threshold to have a noise margin when switching. However, since the threshold value of MOSFET changes due to the substrate bias effect, MOSFET
If Ql and G2 are designed to be the same, as shown in Figure 4, Ql
The threshold value Vthl (Ql) of G2 is the threshold value Vthl (Ql) of G2
thl (G2). This becomes an obstacle when using the device at a lower power supply voltage. In other words, like the conventional Ryo Kabatsufa, the threshold value of Ql Vthl (Q
l) is large, the V of the TTL interface when the power supply voltage Vdd is set to 3°3V as shown by the dashed line B in Fig. 3.

h The standard value of 2.4V cannot be guaranteed.

On the other hand, in the circuit of Fig. 1, the MOSFET
The threshold characteristic of G2 is the threshold value v of MOSFET in the circuit.
th, but since the threshold characteristics of MOSF and ETQl are set low, the output high level V at that time
The oh characteristics are improved as shown by the solid line A in FIG. 3, and the TTL interface VOh standard of 2.4V can be satisfied even when the power supply voltage Vdd is 3.3V.

As explained above, the above embodiment has two N channels M
In a push-pull type output buffer in which OS FETs are connected in series, the threshold voltage of the pull-up MO8FET connected to the high power supply voltage side is the threshold voltage of the pull-down MO3FET connected to the low power supply voltage side. Since it is set lower than , the high level of the output will decrease less from the power supply voltage, and even if the power supply voltage is lower than +5V to prevent breakdown voltage failure, the TTL level interface condition will be maintained. It becomes possible to guarantee a high level Voh of 2.4 V (win) or more.

As a result, even if the CMO3 integrated circuit is miniaturized, it can be used with a power supply voltage as low as 3°3V, and high-speed characteristics can be effectively utilized while preventing deterioration of characteristics due to a decrease in breakdown voltage. Furthermore, since these characteristics can be obtained by simply adding one mask for ion implantation, conventional circuit technology and cell layout can be inherited, and design efficiency can be improved.

Furthermore, chips for 5V and chips for 3.3V can be made separately, improving product flexibility.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, an inverter is used as a logic gate to drive the MOSFET in the output stage, but a NAND gate whose control signal is a signal that controls the output state (output enable signal) is used to achieve high impedance output. It can be applied to a tri-state output buffer configured to obtain

In the above description, the invention made by the present inventor was mainly applied to the output buffer of a CMO8 integrated circuit, which is the field of application that formed the background of the invention, but the present invention is not limited thereto; circuit and B
It can be widely used in push-pull circuits in i-CMO3 integrated circuits and other live conductor integrated circuits.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, even when using a power supply voltage lower than 5V, NM
A semiconductor integrated circuit device using an OS push-pull type Hatake buffer can meet the Vo requirements of a TTL level interface.
h standard can be guaranteed.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of an output circuit to which the present invention is applied, Fig. 2 is a layout diagram showing the entire chip configuration of a CMO3 integrated circuit, and Fig. 3 is a dependence of high level Voh on power supply voltage Vdd. FIG. 4 is a characteristic diagram showing the dependence of the threshold voltage of an N-channel MOSFET on the substrate bias voltage. 1... Internal logic circuit, 2... Input/output circuit section, 3
...Pounding pad, BFF...Push-pull type resistance stage, Ql, Q2. Q4. Q6...N-channel MO6FET, Q3. Q5...O between P channels
8FET, Vth...-MOSFET threshold voltage,
OUT...Output terminal. 1st r2! J Figure 2

Claims (1)

[Claims] 1. In an output buffer circuit including a push-pull type output stage consisting of two N-channel MOSFETs connected in series between a first and a second power supply voltage terminal, the output stage is configured. An output buffer circuit characterized in that a threshold voltage of a MOSFET on a pull-up side is set lower than a threshold voltage of a MOSFET on a pull-down side. 2. The output buffer circuit according to claim 1, wherein the threshold voltages of the two MOSFETs are set to different values by changing the amount of ions implanted into their channel portions.