JPH04162714A - Method and apparatus for manufacturing semiconductor device - Google Patents
Method and apparatus for manufacturing semiconductor deviceInfo
- Publication number
- JPH04162714A JPH04162714A JP28922190A JP28922190A JPH04162714A JP H04162714 A JPH04162714 A JP H04162714A JP 28922190 A JP28922190 A JP 28922190A JP 28922190 A JP28922190 A JP 28922190A JP H04162714 A JPH04162714 A JP H04162714A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- support plate
- semiconductor
- support plates
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 79
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 239000010409 thin film Substances 0.000 claims abstract description 22
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000010408 film Substances 0.000 abstract description 13
- 238000005530 etching Methods 0.000 abstract description 4
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- 238000010276 construction Methods 0.000 abstract 1
- 229910052785 arsenic Inorganic materials 0.000 description 9
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 239000007789 gas Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 3
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 2
- 210000000078 claw Anatomy 0.000 description 2
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000006837 decompression Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
(産業上の利用分野)
この発明は半導体装置の製造方法に関し、特に減圧下に
おいて制御性良く精密な薄膜形成や薄膜加工を施す方法
に関するものである。[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention relates to a method for manufacturing a semiconductor device, and in particular to a method for forming and processing thin films with good controllability and precision under reduced pressure. .
(従来の技術)
半導体装置の高性能化に伴い、半導体や絶縁膜の薄膜を
均一性良く形成したり加工する技術が益々重要となって
いる。減圧下における薄膜形成や薄膜加工には、不純物
の混入が少ないとか、パターンのステップカバレッジが
良好であるとか、薄膜の膜厚の精密コントロールが容易
であるとかの利点がある。(Prior Art) As the performance of semiconductor devices increases, techniques for forming and processing thin films of semiconductors and insulating films with good uniformity are becoming increasingly important. Thin film formation and thin film processing under reduced pressure have advantages such as less contamination of impurities, good pattern step coverage, and ease of precise control of the thickness of the thin film.
特に、砒素ポリシリコンや窒化シリコン膜等に対して減
圧下における薄膜形成や薄膜加工が従来から実施されて
いる。In particular, thin film formation and thin film processing under reduced pressure have been conventionally performed on arsenic polysilicon, silicon nitride films, and the like.
第7図および第8図によって従来の製造方法と製造装置
について説明する。−例として減圧CVD法により半導
体基板に砒素ポリシリコン薄膜を形成する場合、減圧C
vD装置(第8図)の減圧容器である反応室201に、
第7図にも示すように半導体基板101が基板ホルダ1
00上に互いに対面して配列され、両端の半導体基板1
01の外側には補助板102が配置されて内装される。A conventional manufacturing method and manufacturing apparatus will be explained with reference to FIGS. 7 and 8. -For example, when forming an arsenic polysilicon thin film on a semiconductor substrate by low pressure CVD method,
In the reaction chamber 201, which is a vacuum container of the vD device (Fig. 8),
As shown in FIG. 7, the semiconductor substrate 101 is placed on the substrate holder 1.
Semiconductor substrates 1 at both ends are arranged facing each other on
An auxiliary plate 102 is arranged on the outside of 01 and is installed inside.
反応室201の外側には上記半導体基板群に対向しこれ
を取巻くように加熱装置202が設けられ、反応室20
1にはガス導入口203、排気口204が設けられてい
る。A heating device 202 is provided outside the reaction chamber 201 so as to face and surround the group of semiconductor substrates.
1 is provided with a gas inlet 203 and an exhaust port 204.
製造方法の一例は、反応室201を約600℃に加熱し
た状態で排気ポンプ(図示省略)により図中に矢印で示
す方向に排気後、反応室内にジクロルシランとアルシン
の混合ガスを、排気ポンプ吸気側にヘリウム(図示省略
)を夫々導入する。反応室内の気圧を約10−2気圧に
設定することにより砒素ポリシリコン薄膜を半導体基板
上に形成することができる。An example of the manufacturing method is to heat the reaction chamber 201 to about 600° C. and exhaust it in the direction shown by the arrow in the figure using an exhaust pump (not shown), and then introduce a mixed gas of dichlorosilane and arsine into the reaction chamber by inhaling the mixture gas with the exhaust pump. Helium (not shown) is introduced into each side. An arsenic polysilicon thin film can be formed on a semiconductor substrate by setting the atmospheric pressure in the reaction chamber to about 10<-2 >atmospheres.
(発明が解決しようとする課題)
上記従来の製造方法および製造装置においては、複数の
半導体基板について基板内の膜厚とシート抵抗に著しい
不均一を生ずること、極端な場合には薄膜の表面が白濁
化し所望の表面状態が得られないなどの重大な問題点が
ある。(Problems to be Solved by the Invention) In the conventional manufacturing method and manufacturing apparatus described above, significant non-uniformity occurs in the film thickness and sheet resistance within the substrate for multiple semiconductor substrates, and in extreme cases, the surface of the thin film There are serious problems such as clouding and failure to obtain the desired surface condition.
本発明は上記従来の問題点に鑑み、改良された製造方法
と製造装置を提供することを目的とする。SUMMARY OF THE INVENTION In view of the above conventional problems, an object of the present invention is to provide an improved manufacturing method and manufacturing apparatus.
(課題を解決するための手段)
本発明における半導体装置の製造方法は、減圧雰囲気に
おいて半導体基板に薄膜形成、薄膜の加工を施す工程を
含む半導体装置の製造方法において、半導体基板よりも
大きな補助板を、排気方向に対し垂直かつ、その間隔を
半導体基板がその周縁外方に有する前記半導体基板支持
板の突出長以下に配列し、これらの補助板の間に半導体
基板を設置することを特徴とする。(Means for Solving the Problems) A semiconductor device manufacturing method according to the present invention includes a step of forming a thin film on a semiconductor substrate and processing the thin film in a reduced pressure atmosphere. are arranged perpendicularly to the exhaust direction and at an interval equal to or less than the protruding length of the semiconductor substrate support plate that the semiconductor substrate has on the outside of its periphery, and the semiconductor substrate is installed between these auxiliary plates.
次に半導体装置の製造装置は、半導体基板装着機構を有
し半導体基板よりも大きい半導体基板支持板、前記半導
体基板支持板を対面させ排気方向に対し垂直かつ、その
間隔を半導体基板がその周縁外方に有する前記半導体基
板支持板の突出長以下に設けて配列された半導体基板支
持板ホルダ、前記半導体基板支持板ホルダを内装する減
圧容器、および前記半導体基板支持板に支持された半導
体基板に対する加熱装置を具備したことを特徴とするも
のである。Next, the semiconductor device manufacturing apparatus includes a semiconductor substrate support plate having a semiconductor substrate mounting mechanism and larger than the semiconductor substrate, the semiconductor substrate support plate facing each other, perpendicular to the exhaust direction, and the semiconductor substrate having an interval outside the periphery of the semiconductor substrate support plate. a semiconductor substrate support plate holder arranged so as to have a length equal to or less than the protrusion length of the semiconductor substrate support plate on the side; a vacuum container housing the semiconductor substrate support plate holder; and heating the semiconductor substrate supported by the semiconductor substrate support plate. It is characterized by being equipped with a device.
(作 用)
本発明を適用することにより成長速度やエツチング速度
の基板内及び基板間の均一性を大幅に向上することがで
きるので、半導体や絶縁膜等薄膜の精密コントロールが
可能となる。(Function) By applying the present invention, the uniformity of growth rate and etching rate within a substrate and between substrates can be greatly improved, so that precise control of thin films such as semiconductors and insulating films becomes possible.
(実施例) 以下、本発明の実施例につき図面を参照して説明する。(Example) Embodiments of the present invention will be described below with reference to the drawings.
第1実施例
減圧CVD法により半導体基板に砒素ポリシリコン薄膜
を形成する場合の半導体基板の配置につき第1図によっ
て説明する。第1図に示すように、半導体基板11は支
持板12に第4図(a)、(b)に示される装着機構1
3.−例として3個の爪によって支持され、この支持板
12は支持板ホルダ10に装着されている。そして、支
持板12は半導体基板11よりも大きく設け、これにほ
ぼ同心に半導体基板11を配置した場合の半導体基板の
周縁外方に有する突出長(b)(サイズ差で、−例とし
て支持板12が円形の場合の半径の差)だけ大きく形成
し、がっ、この(b)よりも小さく支持板12間の間隔
(a)を設定する。First Embodiment The arrangement of a semiconductor substrate when forming an arsenic polysilicon thin film on a semiconductor substrate by the low pressure CVD method will be explained with reference to FIG. As shown in FIG. 1, a semiconductor substrate 11 is mounted on a support plate 12 by a mounting mechanism 1 shown in FIGS. 4(a) and 4(b).
3. - Supported by example three claws, this support plate 12 is mounted on a support plate holder 10. The support plate 12 is provided larger than the semiconductor substrate 11, and when the semiconductor substrate 11 is arranged approximately concentrically with the support plate 12, the protrusion length (b) outside the periphery of the semiconductor substrate (due to the size difference, - for example, the support plate The distance (a) between the support plates 12 is set to be smaller than (b).
上に述べた新規の配列とし、反応室を約600℃に加熱
した状態で十分に排気したのち、反応室内にジクロルシ
ランとアルシンの混合ガスを、排気ポンプ吸気側にヘリ
ウムを夫々流入し、反応室内気圧を約10’″2気圧に
設定した。このようにして、従来の配列(第7図)に比
べて砒素ポリシリコン薄膜の膜厚均一性を大幅に向上さ
せることができた。Using the new arrangement described above, the reaction chamber is heated to about 600°C and thoroughly evacuated, and then a mixed gas of dichlorosilane and arsine is introduced into the reaction chamber, and helium is introduced into the intake side of the exhaust pump. The atmospheric pressure was set at about 10'''2 atm. In this way, it was possible to significantly improve the film thickness uniformity of the arsenic polysilicon thin film compared to the conventional arrangement (FIG. 7).
種々の実験の結果、半導体基板内の砒素ポリシリコン薄
膜の均一性は、支持板12を半導体基板11よりも大き
くし、かつ支持板12と半導体基板11のサイズ差(b
)より支持板12間の間隔(a)を小にすると向上する
ことが判った。例えば、a=15■の場合、bを変えた
ときの半導体基板内の砒素ポリシリコンの膜厚均一性を
第6図に示した。図中の又は半導体基板について膜厚の
均一性を示す周辺部膜厚/中央部膜厚である。これによ
って条件b > aの範囲内で均一性が顕著に向上して
いることが明らかである。As a result of various experiments, the uniformity of the arsenic polysilicon thin film within the semiconductor substrate was determined by making the support plate 12 larger than the semiconductor substrate 11 and by increasing the size difference (b) between the support plate 12 and the semiconductor substrate 11.
), it was found that the improvement could be achieved by reducing the distance (a) between the support plates 12. For example, in the case of a=15■, the film thickness uniformity of arsenic polysilicon in a semiconductor substrate is shown in FIG. 6 when b is varied. It is the peripheral part film thickness/central part film thickness that shows the uniformity of film thickness for the semiconductor substrate in the figure. It is clear that this significantly improves the uniformity within the range of condition b>a.
第2実施例
第2図によって別の実施例を説明する。第2図にはフレ
オン:r!&素=1=1の条件でプラズマ中で砒素ポリ
シリコンをケミカルトライエツチングを施す際の反応室
での基板ホルダ20.半導体基板21、支持板22の配
列状態を示す。なお、図中の23は支持板間、および支
持板と基板ホルダ間を連接する支柱である。そして、支
持板22と半導体基板21のサイズ差(b)と支持22
の間隔(a)の関係をb〉aとする事により半導体基板
21内のエツチング均一性を著しく向上させる事ができ
た。Second Embodiment Another embodiment will be explained with reference to FIG. Figure 2 shows freon:r! Substrate holder 20 in the reaction chamber when chemically etching arsenic polysilicon in plasma under the condition of & element = 1 = 1. The arrangement state of the semiconductor substrate 21 and the support plate 22 is shown. Note that 23 in the figure is a support that connects between the support plates and between the support plates and the substrate holder. Then, the size difference (b) between the support plate 22 and the semiconductor substrate 21 and the support 22
By setting the relationship between the distance (a) as b>a, the etching uniformity within the semiconductor substrate 21 could be significantly improved.
本発明の実施例では、半導体基板にシリコンを用いて砒
素ポリシリコンの薄膜形成や、ケミカルドライエツチン
グの場合を例にとって述べたが、この例に限らず他の化
合物半導体の基板においても、また、窒化膜等の他の薄
膜形成や加工においても同様の膜厚の均一性向上が期待
できる。In the embodiments of the present invention, the case of forming a thin film of arsenic polysilicon and chemical dry etching using silicon as a semiconductor substrate has been described as an example. A similar improvement in film thickness uniformity can be expected in the formation and processing of other thin films such as nitride films.
また、実施例では半導体基板は補助板に密着させた場合
を例示したが、離れていても本発明の条件を満足してい
る場合には同様の効果が得られた。Further, in the example, the case where the semiconductor substrate was brought into close contact with the auxiliary plate was illustrated, but the same effect could be obtained even if the semiconductor substrate was separated from the auxiliary plate if the conditions of the present invention were satisfied.
第3実施例
本発明に係る半導体装置の製造装置を第3図に断面図で
示す。Third Embodiment A sectional view of a semiconductor device manufacturing apparatus according to the present invention is shown in FIG.
第3図において、半導体基板11を係止する一例として
爪である半導体基板の装着機構13を有する支持板12
が第4図(a)、 (b)にも示されるように半導体基
板11よりも大きく設けられている。そして。In FIG. 3, a support plate 12 has a semiconductor substrate mounting mechanism 13, which is a claw, as an example of locking the semiconductor substrate 11.
is larger than the semiconductor substrate 11, as shown in FIGS. 4(a) and 4(b). and.
これらの支持板12は互いに対面させ排気方向に対し垂
直かつ、その間隔(a)を半導体基板11がその周縁外
方に有する前記支持板の突出長(b)以下に設けて支持
板ホルダ10に配列されている。また、前記支持板ホル
ダ10は減圧容器である反応室31に内装される。さら
に、前記反応室31の外側に半導体基板11に対向して
これを加熱するための加熱装置32が、また、反応室3
1にはガス導入口33、排気口34が設けられている。These support plates 12 are arranged to face each other, perpendicular to the exhaust direction, and have an interval (a) equal to or less than the protrusion length (b) of the support plates that the semiconductor substrate 11 has on the outside of the periphery of the support plate holder 10. Arranged. Further, the support plate holder 10 is placed inside a reaction chamber 31 which is a reduced pressure container. Furthermore, a heating device 32 is provided outside the reaction chamber 31 to face the semiconductor substrate 11 and heat the semiconductor substrate 11.
1 is provided with a gas inlet 33 and an exhaust port 34.
取上の実施例のような製造装置は、横型(第1実施例)
、竪型(第2実施例)のいずれにて行う場合にも全く同
様に適用できるが、竪型の場合には第5図に示すように
、複数支持板12の間、および支持板と支持板ホルダと
の間を保持するための支柱51を必要とし、これが設け
られている点のみ異なる。従って、竪型の場合を示す第
5図の各部の番号は、前記支柱51を除き第3図に付し
た各部の番号と同じくして説明を省略する。The manufacturing equipment like the example mentioned above is a horizontal type (first example)
, vertical type (second embodiment), but in the case of the vertical type, as shown in FIG. The only difference is that a support 51 is required to hold the plate holder, and this is provided. Therefore, the numbers of each part in FIG. 5, which shows the vertical type, are the same as the numbers of each part shown in FIG. 3, except for the support column 51, and a description thereof will be omitted.
本発明によれば、格段に均一性のすぐれた薄膜形成や薄
膜加工が可能となり、これにより、半導体装置の製造歩
留りの顕著な向上と性能の向上に大きく寄与することが
できる。According to the present invention, it is possible to form and process a thin film with extremely high uniformity, which can greatly contribute to a significant improvement in the manufacturing yield and performance of semiconductor devices.
第1図は本発明に係る第1実施例を説明するための側面
図、第2図は本発明に係る第2実施例を説明するための
側面図、第3図に本発明に係る第3実施例の製造装置の
断面図、第4図は本発明の第1実施例の装着機構を示す
(a)は正面図、(b)は側面図、第5図は本発明に係
る第2実施例の製造装置の断面図、第6図は本発明にょ
る膜厚均一性を説明するための線図、第7図は従来例を
説明するための側面図、第8図は従来例の製造装置の断
面図である。
10.20.100・・・基板ホルダ、]1.21.1
01・・・半導体基板、12.22・・・支持板、
13・・・装着機構、
23・・・支柱、
102・・・補助板、
31、201・・・反応室(減圧容器)、32.202
・・・加熱装置、
33.203・・・ガス導入口、
34.204・・・排気口。
代理人 弁理士 大 胡 典 夫
33: ″rr’ス鴫入口 34: 刺
ト気ロ第3図
13:装着機・構
第4図
5]: 支柱
15図
す−一十
x:1辺9暎厚/中央g族廖
第6図FIG. 1 is a side view for explaining a first embodiment according to the present invention, FIG. 2 is a side view for explaining a second embodiment according to the present invention, and FIG. 3 is a side view for explaining a second embodiment according to the present invention. FIG. 4 is a cross-sectional view of the manufacturing apparatus of the embodiment, FIG. 4 shows a mounting mechanism of the first embodiment of the present invention, (a) is a front view, (b) is a side view, and FIG. 5 is a second embodiment of the present invention. 6 is a diagram for explaining film thickness uniformity according to the present invention, FIG. 7 is a side view for explaining the conventional example, and FIG. 8 is a manufacturing apparatus for the conventional example. FIG. 2 is a cross-sectional view of the device. 10.20.100...Substrate holder, ]1.21.1
01...Semiconductor substrate, 12.22...Support plate, 13...Mounting mechanism, 23...Strut, 102...Auxiliary plate, 31, 201...Reaction chamber (decompression vessel), 32 .202
...Heating device, 33.203...Gas inlet, 34.204...Exhaust port. Agent Patent Attorney Norihiro Ogo 33: ``rr' Suzuki Entrance 34: Stitching mechanism (Fig. 3) 13: Mounting mechanism/mechanism (Fig. 4): Post 15 (10 x 9 x 1 side) Thick/Central G-family Liao Figure 6
Claims (1)
の加工を施す工程を含む半導体装置の製造方法において
、半導体基板よりも大きな支持板を、排気方向に対し垂
直かつ、その間隔を半導体基板がその周縁外方に有する
前記半導体基板支持板の突出長以下に配列し、これらの
支持板の間に半導体基板を設置することを特徴とする半
導体装置の製造方法。(2)半導体基板の装着機構を有
し半導体基板よりも大きい支持板、前記支持板を対面さ
せ排気方向に対し垂直かつ、その間隔を半導体基板がそ
の周縁外方に有する前記半導体基板支持板の突出長以下
に設けて配列された支持板ホルダ、前記支持板ホルダを
内装する減圧容器、および前記支持板に支持された半導
体基板に対する加熱装置を具備してなる半導体装置の製
造装置。(1) In a semiconductor device manufacturing method that includes a process of forming a thin film on a semiconductor substrate and processing the thin film in a reduced pressure atmosphere, a support plate larger than the semiconductor substrate is placed perpendicular to the exhaust direction, and the distance between the support plates is such that the semiconductor substrate A method for manufacturing a semiconductor device, comprising arranging the semiconductor substrates so as to have a length equal to or less than the protrusion length of the semiconductor substrate support plates provided on the outer side of the periphery, and installing semiconductor substrates between these support plates. (2) A support plate that has a mounting mechanism for a semiconductor substrate and is larger than the semiconductor substrate, and the semiconductor substrate support plate has the support plates facing each other, perpendicular to the exhaust direction, and the distance between the semiconductor substrate and the semiconductor substrate being on the outer side of the periphery thereof. What is claimed is: 1. A semiconductor device manufacturing apparatus comprising: support plate holders arranged to have a protrusion length or less; a vacuum container housing the support plate holders; and a heating device for a semiconductor substrate supported by the support plates.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28922190A JPH04162714A (en) | 1990-10-26 | 1990-10-26 | Method and apparatus for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28922190A JPH04162714A (en) | 1990-10-26 | 1990-10-26 | Method and apparatus for manufacturing semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04162714A true JPH04162714A (en) | 1992-06-08 |
Family
ID=17740356
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28922190A Pending JPH04162714A (en) | 1990-10-26 | 1990-10-26 | Method and apparatus for manufacturing semiconductor device |
Country Status (1)
Country | Link |
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JP (1) | JPH04162714A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014174627A1 (en) * | 2013-04-25 | 2014-10-30 | 株式会社島津製作所 | Sample holder |
-
1990
- 1990-10-26 JP JP28922190A patent/JPH04162714A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014174627A1 (en) * | 2013-04-25 | 2014-10-30 | 株式会社島津製作所 | Sample holder |
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