JPH04162624A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent an upper-layer interconnection material layer from being eroded by a loading effect while a practical etching speed is maintained by a method wherein a uniform-velocity etching-back operation is executed under etching conditions whose main constituent is a radical reaction and an overetching operation is executed under etching conditions whose main constituent is a sputtering reaction by means of ions. CONSTITUTION:The whole surface is coated with a resist film 8 as a flattening material layer; the surface of a base body is flattened. The base body in this state, a wafer 15, is set on a wafer stage 16 at a microwave plasma etching apparatus provided with a magnetic field; it is raised to a position which closes the opening in a plasma extraction window 14 so that the wafer 15 can be arranged and installed so as to face a plasma generation chamber 13. An etching-back operation is executed. The etching speed of the resist film 8 and that of a tungsten layer 7 become equal. An etching-back operation whose main etching seed is F*, that is, fluorine radicals, progresses at high speed. A protrusion 7a is removed, and the surface of the base body is flattened. In order to remove the resist film 8 and the tungsten layer 7 which are left a little, an overetching operation is executed. A radical property is restrained; instead of it, the dependence of ions on an etching reaction becomes large.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for improving the planarization of a substrate after connecting holes of different depths are filled by selective growth of an upper wiring material layer. Regarding how to do it with precision.

[Summary of the invention]

The present invention is capable of filling connection holes of different depths opened in an interlayer insulating film facing the lower wiring by selectively growing the upper wiring material layer or by combining selective growth and full-scale growth. In a semiconductor device manufacturing method in which the substrate is planarized by etchback using wave plasma etching equipment, radical reactions are predominant until the surface of the interlayer insulating film is almost exposed, and overetching is performed using ion sputtering. By performing etching under conditions in which reactions are the main component, it is possible to maintain a practical etching rate while preventing erosion of the upper wiring material layer due to the loading effect during overetching.

[Conventional technology]

As semiconductor devices become more highly integrated and dense, as seen in VLSI, ULSI, etc., the proportion of wiring on device chips tends to increase.
In order to prevent a significant increase in chip area due to this, multilayer wiring has now become an essential technology. Conventionally, as a wiring formation method, forming a metal thin film made of aluminum or the like by a sputtering method has been widely practiced.

However, as mentioned above, as wiring becomes more multilayered and as a result, the surface level difference of the substrate and the aspect ratio of connection holes increase, the lack of step coverage in the sputtering method results in a gap between the upper layer wiring and the semiconductor substrate. Poor connections between wires and wires have already become a serious problem.

Therefore, in recent years, attention has been paid to a technique of burying contact holes with a high aspect ratio by selectively growing high melting point metals such as tungsten, molybdenum, and tantalum, or metals such as aluminum and copper within the contact holes. A typical method for such selective growth is a selective CVD method in which a metal is deposited by reducing a gas such as a metal fluoride or an organometallic compound using a lower wiring material. When contact holes of different depths opened in an interlayer insulating film are filled with metal by selective CVD, excessive growth (overgrowth) occurs in relatively shallow contact holes when the contact holes are relatively deep or filled with just the right amount. growth) occurs, and the so-called nail growth occurs.
A head-shaped protrusion is formed. Since such protrusions are undesirable for the purpose of flattening the substrate, the substrate is usually flattened by coating the entire surface with a resist material, and then etched under conditions such that the etching rate of the flattening material and the metal are equal. It is removed by backing up.

Alternatively, a method is also known in which the selective CVD method described above is combined with a CVD method (so-called blanket CVD method) in which a metal or alloy is deposited on the entire surface of the substrate, and the substrate is planarized by etchback. For example, JP-A-63
-133551 publication describes contacts with different depths.
Tungsten is grown in the hole by selective CVD,
Subsequently, a technique has been disclosed in which a tungsten silicide layer is formed on the entire surface by a blanket CVD method, an organic coating film is further formed on the entire surface, and the substrate is planarized by etching back. According to this technology, deep contact
Even if there is a lack of metal filling (undergrowth) in the hole, the lack can be compensated for by the alloy layer deposited by the blanket CVD method, making it possible to flatten the substrate.

[Means to solve the problem]

By the way, in the above-mentioned etchback, overetching of about 5 to 10% is usually performed in consideration of uniformity within the wafer surface. However, even on the same wafer surface, the etching rate is faster in areas close to areas with relatively high plasma density in the etching equipment than in other areas, so the etching rate due to the exposure of the glabella insulating film is A rapid decrease in the etching area occurs at an early stage, and the metal embedded in the connection hole is greatly eroded by the excess etching species. This is a phenomenon well known as the so-called loading effect. This problem has been addressed as the diameter of wafers has increased as device chips have become larger, and single-wafer plasma etching equipment has become mainstream, using high-density plasma to perform high-speed etching to avoid reducing throughput. In the field of manufacturing semiconductor devices in the future, it is thought that -layers will become more prominent.

Therefore, an immediate solution is desired.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for etching back an upper layer wiring metal after selective growth at a practical speed and with high accuracy without causing the adverse effects due to the loading effect as described above.

[Means to solve the problem]

A method for manufacturing a semiconductor device according to the present invention is proposed to achieve the above-mentioned object.

That is, the method for manufacturing a semiconductor device according to the first aspect of the present invention includes a step of forming a plurality of lower layer wirings on a substrate having a step, a step of forming an interlayer insulating film on the entire surface, and a step of forming a layer facing the lower layer wirings. forming a plurality of contact holes with different depths in the interlayer insulating film; selectively growing an upper wiring material layer in the contact holes until the deep contact holes are completely filled; A step of forming a planarizing material layer to planarize the substrate, and using a magnetic field microwave plasma etching device, the planarizing material is etched under etching conditions that mainly involve radical reactions until the surface of the interlayer insulating film is exposed. This method is characterized by comprising a step of performing constant-speed etchback of the layer and the upper wiring material layer, and a step of performing over-etching by switching to etching conditions in which sputtering reaction by ions is the main ingredient.

A method for manufacturing a semiconductor device according to a second aspect of the present invention includes:
A plurality of connecting holes having different depths are formed in the same manner as in the first invention, and the connecting holes are further drilled so that the shallow connecting holes are completely filled and the deep connecting holes are not fully filled. a step of selectively growing a first upper wiring material layer, a step of forming a second upper wiring material layer on the entire surface so that the deep connection hole is completely buried, and a step of forming a planarization material layer on the entire surface. At least the planarizing material layer and the first layer are etched until the surface of the interlayer insulating film is exposed, using a magnetic field microwave plasma etching device under etching conditions that mainly involve radical reactions. 2. A step of performing etch-back under conditions where the etching rate is equal to that of the upper wiring material layer, and a step of performing over-etching by switching to etching conditions in which a sputtering reaction by ions is the main component. It is.

Furthermore, in the method for manufacturing a semiconductor device according to the third aspect of the present invention, the process up to the opening of a plurality of contact holes having different depths is carried out in the same manner as in the first invention, and furthermore, there is insufficient filling in any of the contact holes. a step of selectively growing a first upper layer wiring material layer in the connection hole so that the connection hole is completely filled with a second upper layer wiring material layer over the entire surface so that the connection hole is completely buried; , a step of flattening the substrate by forming a layer of flattening material on the entire surface, and a step of flattening the substrate using magnetic field microwave plasma.
a step of etching back the planarizing material layer and the second upper wiring material layer at a constant rate using an etching apparatus under etching conditions mainly based on radical reaction until the surface of the interlayer insulating film is exposed; This method is characterized by the step of performing over-etching by switching to etching conditions in which a sputtering reaction is the main component.

[Effect]

The methods for manufacturing a semiconductor device according to the first, second, and third aspects of the present invention all include an etch hack step until the surface of an interlayer insulating film is exposed, and a uniform processing process within the wafer surface. An important point is to switch the etching conditions between the over-etching process and the over-etching process to achieve the desired results.

First, during etchback, etching conditions are adopted in which radical reaction is the main ingredient. Magnetic field microwave plasma/
In order to achieve such conditions in an etching apparatus, a relatively high RF bias frequency may be applied and the substrate to be processed may be placed in a region of high plasma density within the etching apparatus.

Generally, when an alternating current electric field is applied between both electrodes in a plasma etching system, both ions and electrons can follow the reversal of the electric field when the frequency is low, but as the frequency of the applied electric field increases, the mass increases. It becomes impossible to follow the ions one by one, and as the frequency increases further, the electrons also become impossible to follow and begin to oscillate between the two electrodes.

The starting point of this vibration is usually in the radio frequency (RF) region. Therefore, when a high RF bias frequency is applied and electrons oscillate between the two electrodes, many radicals and ions are generated due to collisions between the electrons and gas molecules, but the ions cannot follow the electric field, so Specifically, conditions are achieved in which radical-based etching reactions are likely to occur. As a result, etchback progresses isotropically at a practical speed.

On the other hand, during over-etching, etching conditions are adopted in which sputtering reaction by ions is the main activity. Such conditions can be achieved in a magnetic field microwave plasma etching system by applying a relatively low RF bias frequency and moving the substrate away from areas of high plasma density within the etching system. Such low R
Under the F bias frequency, ions with large mass can also follow the switching of the electric field, so the radical nature is relatively weakened and the ion dependence of the etching reaction increases. Since the ions are accelerated along the electric field by their charge, high anisotropy is achieved during overetching.

The above-mentioned functions are common to all three inventions constituting the present invention, but the three inventions assume that there are three cases in which connecting holes with different depths are buried by selective growth, and in each case, This is an application of the dry etching technique described above.

That is, in the first invention, all the connection holes are filled by selective growth of the upper wiring material layer, and nail head-like protrusions are formed in the shallow connection holes or in both the shallow connection holes and the deep connection holes. Etchback is required to remove this protrusion. Therefore, the etch-back in this case is performed under conditions such that the etching rates of the planarization material layer and the upper wiring material layer are equal.

In the second invention, the shallow contact hole is buried flatly or in a nail head shape by the first upper layer wiring material layer, and since there is insufficient filling in the deep connection hole, this shortage is filled with the second upper layer wiring material layer. Layer embedding work and etchback are required.

Therefore, in this case, the etchback is performed under conditions where the etching rate of the flattening material layer and the second upper wiring material layer are equal when the shallow contact hole is buried flatly, and the etching rate of the flattening material layer and the second upper wiring material layer are equal. is formed, the etching is performed under conditions such that the etching rates of the planarizing material layer, the second upper wiring layer, and the first upper wiring layer are equal.

Furthermore, in the third invention, the first
Since there is insufficient embedding with the wiring material layer, it is necessary to bury this shortage with a second upper wiring material layer and etch back. Therefore, the etch-back in this case is performed under conditions such that the etching rates of the planarizing material layer and the second upper wiring material layer are equal.

〔Example〕

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.

First, before entering into the description of each embodiment, referring to FIG. 6(A) and FIG. 6(B) for a schematic configuration example of a magnetic field microwave plasma etching apparatus used in the present invention. explain.

This device includes a magnetron (10) that generates 2.45 GH2 microwaves, a rectangular waveguide that is connected to the magnetron (1o) via a matching box, a microwave power meter, an isolator, etc. (not shown), and that guides the microwaves. Pipe (11
), a plasma generation chamber ( ) connected to the rectangular waveguide (11) via a microwave introduction window (12) made of a quartz glass plate, etc., for generating plasma using electron cyclotron resonance (ECR). 13) In order to prevent temperature rise due to plasma generation, the plasma generation chamber (1
3) a cooling water pipe (21) that introduces water into the double-structured outer wall, a plasma extraction window (14) for drawing out the plasma generated in the plasma generation chamber (13), and a wafer that is the workpiece. a sample chamber (17) surrounding the wafer stage (16) on which the wafer (15) is placed and performing etching;
From one end of the rectangular waveguide (11) to the plasma generation chamber (
13), a solenoid coil (18) disposed so as to circulate around these, and the plasma generation chamber (13).
) for supplying etching gas to the sample chamber (17), a secondary gas supply pipe (20) for supplying etching gas to the sample chamber (17), and a secondary gas supply tube (20) for supplying etching gas to the sample chamber (17).
7) and an exhaust system (not shown) connected in the direction indicated by the arrow in the figure.

In addition to these basic components, the above device has the following three features: ■ Wafer stage (16)
(1) It is possible to switch the bias frequency applied to the wafer stage (16), and (2) the plasma extraction window (14) can be opened and closed.

First, the wafer stage (16) is connected to a wafer stage support member (22) connected to a driving means (not shown).
), it is possible to move up and down along the direction of arrow B in the figure. Additionally, a first RF power source (25) with a frequency of 13.56 MHz is installed outside the sample chamber (17).
), and a second RF power supply (24
), and both of these are connected by a changeover switch (
23) selectively removes the wafer stage support member (
22) to the wafer stage (16) to apply predetermined RF bias power at each frequency. Furthermore, the plasma drawer window (1
4) functions as a diaphragm for the plasma flow (26), constitutes a microwave reflecting surface, and has the role of making the plasma generation chamber (13) function as a microwave resonator. It is capable of reciprocating in the direction of the middle arrow C.

Here, the raising and lowering operation of the solid stage (16), the switching operation of the RF bias frequency, and the opening/closing operation of the plasma extraction window (14) are interlocked with each other.

That is, when it is desired to achieve etching conditions in which radical reactions are the main ingredient, it is advantageous to apply a relatively high RF bias frequency and place the wafer (15) in a high-density plasma discharge region. As shown in FIG. 6(A), the opening of the plasma extraction window (14) is enlarged, and the large stage (16) is raised to approximately the same height as the plasma extraction window (14) to open the opening. and connect the contacts (23a) and (23b) of the changeover switch (23) so that the first RFt source (25) is connected.

On the other hand, if it is desired to achieve etching conditions in which ion-based sputtering is the main component, it is advantageous to apply a relatively low RF bias frequency and move the wafer (15) away from the plasma generation chamber (13). Therefore, the wafer stage (16) as shown in FIG. 6(B)
is lowered to an appropriate position within the sample chamber (17), and the opening of the plasma extraction window (14) is narrowed in accordance with the lowering distance in order to make the etching uniform within the surface. As a result, from the plasma extraction window (14), a plasma flow (26) containing many ions descends along the diverging magnetic field.
can be extracted. In addition, a selector switch (
23) Contact (23a) and Contact (23c) are connected to connect the second RF power source (24).

Examples using such a magnetic field microwave plasma etching apparatus will be described below with reference to the drawings.

However, in each of the following embodiments, all of the etching gas used is partially supplied to the plasma generation chamber (13) through the gas supply pipe (19), and the secondary gas supply pipe (20) is not used. In addition, FIGS. 1(A) to 1(C), FIG. 2, FIG. 3(A) to 3(D), FIG. 4, and FIGS. 5(A) and 5( In B), parts formed by a common material layer will be described using the same numbers even if there are slight differences in shape.

Example 1 In this example, selective CVD was performed by applying the first invention of the present invention.
This is an example in which the substrate was planarized after growing a tungsten layer by a method. This is shown in Figure 1 (A) to Figure 1 (
This will be explained with reference to C).

First, as shown in FIG. 1(A), a lower wiring layer (2) on the lower stage and a lower wiring layer (3) on the upper stage, which are made of an aluminum-based material layer, etc. are placed on a substrate (1) having a step. After the entire surface is almost flatly covered with an interlayer insulating film (4) made of silicon oxide or the like, a deep first contact hole is formed in the interlayer insulating film (4) facing the lower wiring layer (2) on the lower stage side. (5) and a shallow second contact hole (6) facing the lower wiring layer (3) on the upper stage side were formed, respectively. These first connection holes (
5) and a tungsten layer (7) that will become part of the upper layer interconnection is grown inside the second contact hole (6) by selective CVD, and the first contact hole (5) is buried almost flat. Under these conditions, excessive growth occurred in the second connecting hole (6), and a nail head-shaped protrusion (7a) was formed.

Next, as shown in FIG. 1(B), a resist film (8) was applied as a planarizing material layer over the entire surface to planarize the surface of the substrate.

Next, the substrate in this state [hereinafter, this will be described as a wafer (15). ] is set on the wafer stage (16) of a magnetic field microwave plasma etching system, and the plasma extraction window (1) is set as shown in FIG. 6(A).
The wafer (15) was raised to a position where the opening of (4) was closed, and the wafer (15) was placed in the plasma generation chamber facing (13). In addition, the first RF power source (25) with a frequency of 13.56 MHz was connected by operating the changeover switch (23). Here, SF, flow rate 30SCCM, HB r flow rate 203CCM, gas pressure 0.67Pa and 5 mTor.
r), fibrous wave power 850W, RF bias
Etch back was performed at a power of 150 W. Under these conditions, the etching rates of the resist film (8) and the tungsten layer (7) are equal, and F'' (fluorine radicals)
Etchback, which is the main type of etching, progresses rapidly. At the end point of this etchback, CF, which is a reaction product of Fo and the resist film (8), is detected in the emission spectrum.
The emission intensity was observed at, for example, 251.8 nm, and the evaluation was made based on the point at which the emission intensity began to decrease as the resist film (8) was consumed. As a result, as shown in FIG. 1(C), the protrusion (7a) was removed and the surface of the base was flattened.

Next, the resist film (8) and tungsten layer (7) that remain slightly in the region not shown in FIG.
Over-etching was performed to remove. That is, the wafer stage (16) is lowered into the sample chamber (17) as shown in FIG. 800kHz 2nd RF
The power supply (24) was connected. In this state, SF, flow rate 20
SCCM, HB r flow rate 30SCCM, gas pressure 0.
Overetching was performed under the conditions of 67 Pa (=5 mTorr), fibrous wave power of 850 W, and RF bias power of 200 W. Under these conditions, the RF bias frequency applied to the wafer stage (16) is lowered, so that even ions with large mass such as Br can follow the switching of the electric field. Since the flow rate and RF bias power are higher than during etchback, radical properties are suppressed, and instead, the ion dependence of the etching reaction is increased. Therefore, even after over-etching, the state of the substrate shown in FIG. 1(C) was maintained, and the tungsten layer (7) inside the contact hole did not erode due to the loading effect.

In addition, in this example, the planarization process was explained in the case where the protrusion (7a) is formed only on the shallow second contact hole (6) after the selective growth of the tungsten layer (7). For example, as shown in FIG.
Exactly the same process can be applied to the case where the protrusion (7b) is formed in the connection hole (5).

Also, the RF bias frequency and RF bias power applied during etchback is approximately 13.56 MH
z or more and 150 W or more, and during overetching, approximately 2 MHz or less and 100 to 20 MHz or more.
It is sufficient if it is 0W.

Furthermore, the upper layer wiring material selectively grown in the contact hole is not limited to the above-mentioned tungsten, but also molybdenum,
Other high melting point metals such as tantalum, titanium, aluminum,
Metals such as copper can be used.

Example 2 In this example, selective CVD is performed by applying the second invention of the present invention.
This is an example in which a tungsten layer was grown by a method and a blanket CVD method, and then the substrate was planarized. This will be explained with reference to FIGS. 3(A) to 3(D).

FIG. 3(A) shows that in the case of selectively growing a "Nungsten layer (7)" as a first upper wiring material layer in a plurality of contact holes having different depths as in Example 1, a deep first The connection hole (5) shows insufficient filling, and the shallow second connection hole (6) shows a nail head-shaped protrusion (7a).

A blanket tungsten layer (90%
), and as shown in FIG. 3(B), the first
The connection hole (5) was completely filled.

Next, as shown in FIG. 3(C), a resist film (8
), the substrate was substantially flattened, and then etched back was performed under the same conditions as in Example 1. However, the method for determining the end point is different from that in Example 1.
The luminescence intensity of 5iF11, which is a reaction product with 9, was observed at, for example, 777 nm, and judgment was made based on the point at which the luminescence intensity suddenly increased.

Alternatively, a blanket tungsten layer (9
) can be easily checked visually by taking advantage of the fact that the metallic luster on the substrate surface sharply decreases when it disappears. It would be ideal if the luminescent species derived from tungsten could be monitored, but WF.

Generally, tungsten halides such as these have low luminous efficiency and do not give a characteristic luminescent peak, so a decrease in the overall luminescent intensity in a broad wavelength range is detected.

Further, over-etching was performed in the same manner as in Example 1, and finally good planarization was achieved as shown in FIG. 3(D).

In this example, the planarization process was explained in the case where the protrusion (7a) was formed on the shallow second connection hole (6) after the selective growth of the tungsten layer (7). A similar process can be applied to the case where the second connection hole (5) is buried flat as shown in FIG.

Furthermore, the second upper wiring material layer is not limited to the above-mentioned tungsten, but may also be made of high melting point metals such as molybdenum, tantalum, titanium, silicides of these metals, or metals such as aluminum, copper, and alloys thereof. be able to. Further, the second upper wiring material layer and the first upper wiring material layer may be formed of different metals or alloys.

Example 3 In this example, selective CVD is performed by applying the third invention of the present invention.
This is an example in which a tungsten layer was grown by a method and a blanket CVD method, and then the substrate was planarized. This will be explained with reference to FIGS. 5(A) and 5(B).

FIG. 5(A) shows the first contact hole (
5) and the second connection hole (6) are both insufficiently filled.

A blanket tungsten layer (90%
), the first contact hole (5) and the second contact hole (6) were completely buried, and a resist film (not shown) was further formed to flatten the substrate.

This substrate was subjected to etchback and overetching in the same manner as in Example 2, and the final result was as shown in FIG. 5(B).
Good planarization was achieved as shown in .

〔Effect of the invention〕

As is clear from the above explanation, if the present invention is applied, it is possible to flatten the substrate with high precision by suppressing radical properties during over-etching and by adopting etching conditions in which the sputtering reaction by ions is the main ingredient. It becomes possible. Furthermore, since the etch-back employs conditions that mainly involve radical reactions, the overall throughput does not decrease significantly. Therefore, the present invention enables extremely reliable processing even when it is necessary to embed upper layer wiring material into fine contact holes with high aspect ratios and different depths, and enables high integration.

It is extremely effective in manufacturing semiconductor devices with high performance.

[Brief explanation of drawings]

FIG. 1(A) to FIG. 1(C) are schematic cross-sectional views showing the process order of an embodiment to which the first invention of the present invention is applied, and FIG. 1(A) is a selective growth of a tungsten layer. FIG. 1(B) shows the state of the substrate after it has been flattened by the resist film, and FIG. 1(C) shows the state of the substrate after etchback and overetching are completed. FIG. 2 is a schematic sectional view showing another state after selective growth of the substrate to which the first aspect of the present invention is applied. FIG. 3(A) to FIG. 3(D) are schematic cross-sectional views showing the process order of an embodiment to which the second invention of the present invention is applied, and FIG. 3(A) shows selective growth of a tungsten layer. Figure 3(B) shows the state of the substrate after formation of the blanket tungsten layer, Figure 3(C) shows the state of the substrate flattened by the resist film, and Figure 3(D) shows the state of the substrate after etch-back and over-etching. Each represents the state of the substrate upon completion. FIG. 4 is a schematic cross-sectional view showing another state after selective growth of the substrate to which the second invention of the present invention is applied. FIG. 5(A) and FIG. 5(B) are schematic cross-sectional views showing an embodiment to which the third invention of the present invention is applied in the order of steps, and FIG. 5(A) shows selective growth of a tungsten layer. FIG. 5B shows the state of the substrate after etch-back and over-etching are completed. 6(A) and 6(B) are schematic cross-sectional views showing an example of the configuration of a magnetic field microwave plasma etching apparatus used in the present invention, and FIG. 6(A) is a high RF bias FIG. 6(B) shows the operating conditions when a low RF bias frequency is applied. 1...Substrate 2...Lower wiring layer 3 (on the lower stage side)...Lower wiring layer 4 (on the upper stage side)...Interlayer insulating film 5...First connection hole 6...No. 2 connection hole 7...Tungsten layer 7a, 7b...Protrusion 8...Resist film 9...Blanket tungsten layer 13
...Plasma generation chamber 14 ...Plasma extraction window 15 ...Wafer 16 ...Wafer stage 17 ...Sample chamber 23 ...Selector switch 24 ...Second RF power supply 25 ... First RFt source Figure 3 (C) Figure 3 (D) Figure 6 (A) Figure 6 (B)

Claims (3)

[Claims] (1) A step of forming a plurality of lower layer wirings on a substrate having a step, a step of forming an interlayer insulating film on the entire surface, and a plurality of contact holes with different depths in the interlayer insulating film facing the lower layer wirings. A step of forming a hole, a step of selectively growing an upper wiring material layer in the contact hole until the deep contact hole is completely filled, and a step of planarizing the substrate by forming a layer of planarizing material on the entire surface. , using a magnetic field microwave plasma etching device to etch back the planarization material layer and the upper wiring material layer at a constant rate under etching conditions in which radical reactions are the main component until the surface of the interlayer insulating film is exposed; A method for manufacturing a semiconductor device, comprising the steps of: performing over-etching by switching to etching conditions in which a sputtering reaction by ions is the main ingredient. (2) A step of forming a plurality of lower layer wirings on a substrate having a step, a step of forming an interlayer insulating film on the entire surface, and a plurality of contact holes with different depths in the interlayer insulating film facing the lower layer wirings. the step of selectively growing a first upper wiring material layer in the contact hole so that the shallow contact hole is completely filled and the deep contact hole is insufficiently filled; A second layer is placed on the entire surface so that the deep connection hole is completely buried.
A step of forming an upper wiring material layer, a step of forming a planarizing material layer on the entire surface to planarize the substrate, and a magnetic field microwave plasma etching device is used to perform the above etching process under etching conditions in which radical reactions are the main component. etching back under conditions such that the etching rate of at least the planarization material layer and the second upper wiring material layer are equal until the surface of the interlayer insulating film is exposed; and etching conditions in which a sputtering reaction by ions is the main component. 1. A method for manufacturing a semiconductor device, comprising the step of performing over-etching by switching to (3) A step of forming a plurality of lower layer wirings on a substrate having a step, a step of forming an interlayer insulating film on the entire surface, and a plurality of contact holes with different depths in the interlayer insulating film facing the lower layer wirings. a step of opening a hole; a step of selectively growing a first upper layer wiring material layer in the contact hole so that the filling is insufficient in any of the contact holes; and a step of completely filling the contact hole. As shown in FIG. etching back the planarization material layer and the second upper wiring material layer at a constant rate until the surface of the interlayer insulating film is exposed under etching conditions such that the etching conditions are such that a sputtering reaction by ions is the main component; 1. A method for manufacturing a semiconductor device, comprising the step of performing over-etching by switching to