JPH04162571A - Thin film transistor - Google Patents

Abstract

PURPOSE:To make it possible to inhibit the generation of a kink phenomenon and prevent device deterioration by installing a conductor layer which is partially interfaced with a source region and a channel region. CONSTITUTION:A silicon thin film is formed on an insulation film 2 which serves as an insulation board formed on a semiconductor substrate 1 by way of a gate insulation film. On this thin film are installed an N type drain region 3, a source region 5, and a P type channel region 4 where a gate electrode 7 is installed in such a manner that it may face gate insulation layer 2 on the opposite to the channel region 4. During this fabrication, the insulation layer 2 is partially removed and a conductor layer 10 is installed in such a manner that it may face partially the source region 5 and the channel region 4.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to an MIS type thin film transistor (Thin Film Transistor) using a silicon thin film formed on a semiconductor substrate or an insulating substrate.
in Film Transsiter, hereinafter referred to as TP
It's called T. ).

〔overview〕

The present invention provides a thin film transistor formed on a silicon thin film formed on an insulating substrate, in which a conductive layer is provided in contact with a part of a source region and a channel region, so that the source potential and the channel region potential can be kept the same. By making this possible, the King phenomenon, in which the drain current increases abnormally under high voltage, is suppressed and element deterioration is prevented.

[Conventional technology]

TFT is SOI (Silicon on i'n
It is used in liquid crystal displays, etc. as one of the 5ulator technologies, and has recently attracted attention as a load element for SRAM (see "Nikkei Microdevice J, September 1988 issue, P, 123-F', 130)." 3 is a schematic cross-sectional view showing the structure of a general TPT as a first conventional example. In FIG. These are a drain region, a channel region, and a source region of the TPT.Here, the conductivity type of the drain region 3 and the source region 5 is N type, and the conductivity type of the channel region 4 is P type, which is an N-channel type TPT. 6 is a gate insulating film, 7 is a gate electrode, and 8 and 9 are a drain electrode and a source electrode, respectively.

In addition, TPT used in liquid crystal displays and SRAM
The silicon thin film is often a polycrystalline silicon thin film.

In a conventional TPT as shown in FIG. 3, the channel region is surrounded by drain and source regions and an insulating film, and is therefore in an electrically floating state.

[Problem to be solved by the invention]

FIG. 4(a) is a diagram showing the terminals of the MIS type transistor, and the terminal B applies a potential to the channel region.

In an MTS transistor formed on a semiconductor substrate, the terminal B is usually set at the same potential as the source S. However, T.P.T.
In the S○■ element including the S○■ element, the terminal B is normally in a floating state, which causes an abnormal increase in the drain current called the King phenomenon. FIG. 4 et al.) are drain current characteristic curves of MIS type transistors, where ■ is the normal characteristic and ■ is the kink phenomenon.

The King phenomenon occurs when a high electric field is applied near the drain of the channel region, and carriers generated by impact ionization flow into the drain and source regions because the channel region is in a floating state.
This may cause element deterioration.

As a structure for avoiding this King phenomenon, a structure shown as a second conventional example in FIG. 5 has been proposed.

In the structure shown in FIG. 5, the insulating layer 2 below the channel region 4 is removed, the semiconductor substrate 1 and the channel region 4 are connected, and the semiconductor substrate 1 is connected to a terminal B that applies a potential to the channel region 4.
It is used as

However, TPTs applied to SRAMs and the like have a problem in that they cannot adopt the structure shown in FIG. 5, which is formed on a silicon thin film formed on the top of an element formed on the surface of a semiconductor substrate with an insulating layer interposed therebetween.

An object of the present invention is to provide a TPT that can suppress the king phenomenon and prevent element deterioration by solving the above-mentioned problems.

[Means to solve the problem]

The present invention provides a source region, a channel region, and a drain region provided in a silicon thin film formed on an insulating substrate, a gate insulating film provided in contact with one surface of the silicon thin film, and a gate insulating film provided in contact with the gate insulating film. A thin film transistor including a gate electrode provided opposite to a channel region, characterized in that the thin film transistor includes a conductor layer provided in contact with the source region and a portion of the channel region.

Further, in the present invention, the gate insulating film may be provided on the upper surface of the silicon thin film.

Further, in the present invention, the gate insulating film may be provided on the lower surface of the silicon thin film.

[Effect]

The conductor layer provided in contact with a part of the source region and the channel region serves as a common electrode for the electrode S and electrode B shown in FIG. 4(a), and the source region and the channel region are kept at the same potential. It can be done.

Therefore, the carriers generated by ion impact are
Since it is emitted through this conductor layer, it is possible to suppress the occurrence of the king phenomenon in which the drain current abnormally increases, and to prevent element deterioration.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic sectional view showing the structure of a first embodiment of the present invention.

In this embodiment, a silicon thin film is formed on an insulating layer 2 as an insulating substrate formed on a semiconductor substrate 1 via a gate insulating film, and an N-type drain region 3 and a source region are formed on this silicon thin film. 5, and a thin film transistor in which a P-type channel region 4 is provided and a gate electrode 7 is provided in contact with the gate insulating layer 2 and facing the channel region 4, which is a feature of the present invention. A conductor layer 10 is provided in contact with the source region 5 and a portion of the channel region 4 by partially removing the conductor layer 10 .

Here, by increasing the impurity concentration of the portion of the channel region 4 that contacts the conductor layer 10, the conductor layer 10 can provide the same potential to both the source region 5 and the channel region 4. Further, the material used for the conductor layer 10 may be, for example, high melting point metal silicide.

As a result, carriers generated by impact ionization can be released from the conductor layer 10, so that an abnormal increase in drain current can be suppressed and deterioration of the device can be prevented.

FIG. 2 is a schematic cross-sectional view showing the structure of a second embodiment of the present invention.

In the second embodiment, the gate insulating film 6 is provided on the lower surface of the silicon thin film, and the relationship between the gate electrode 7 and the conductor layer 10 is reversed from that in the first embodiment. However, the features and operation of the invention are similar to the first embodiment.

When using TPT in SRAM, etc., it has been proposed to share the gate electrode with the MIS type transistor on the surface of the semiconductor substrate, or to provide it under the silicon thin film (``Nikkei Microdevice J, September 1988 issue, P123~ P
130, IEDM Technical Digest Paper rI
EDM Digest of Thecnical P
aper J1988, P48-P51). The second embodiment corresponds to such a structure.

Although the above description deals with an N-channel type TPT, the present invention can be similarly applied to a P-channel type TPT.

〔Effect of the invention〕

As explained above, the present invention uses a conductor layer that is simultaneously connected to the source region and channel region of the TPT to release carriers generated by impact ionization, suppress the king phenomenon in which the drain current increases abnormally, and improve the device performance. It has the effect of preventing deterioration.

[Brief explanation of drawings]

FIG. 1 is a schematic sectional view showing the structure of a first embodiment of the present invention. FIG. 2 is a schematic sectional view showing the structure of a second embodiment of the present invention. FIG. 3 is a schematic cross-sectional view showing the structure of the first conventional example. FIG. 4(a) is a terminal diagram of an MIS type transistor. Figures 4 and 4) are voltage-current characteristic diagrams of MIS type transistors. FIG. 5 is a schematic cross-sectional view showing the structure of a second conventional example. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Insulating layer, 3... Drain region, 4... Channel region, 5... Source region,
6... Gate insulating film, 7... Gate electrode, Drain electrode, 9... Source electrode, 10... Conductor layer,
B, D, G, S...terminals.

Claims (1)

[Claims] 1. A source region, a channel region, and a drain region provided in a silicon thin film formed on an insulating substrate; a gate insulating film provided in contact with one surface of the silicon thin film; and the gate insulating film. A thin film transistor comprising a gate electrode provided in contact with a film and facing the channel region, the thin film transistor comprising: a conductor layer provided in contact with the source region and a portion of the channel region. 2. The thin film transistor according to claim 1, wherein the gate insulating film is provided on the upper surface of the silicon thin film. 3. The thin film transistor according to claim 1, wherein the gate insulating film is provided on the lower surface of the silicon thin film.