JPH04162564A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04162564A JPH04162564A JP2288810A JP28881090A JPH04162564A JP H04162564 A JPH04162564 A JP H04162564A JP 2288810 A JP2288810 A JP 2288810A JP 28881090 A JP28881090 A JP 28881090A JP H04162564 A JPH04162564 A JP H04162564A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating
- film
- resist
- fet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims abstract description 18
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 14
- 150000002500 ions Chemical class 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 3
- 230000005669 field effect Effects 0.000 claims 2
- 150000001875 compounds Chemical class 0.000 claims 1
- 239000013078 crystal Substances 0.000 claims 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical group OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 abstract description 6
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 45
- 238000009826 distribution Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、Ｅ−Ｄ ＭＥＳ
ＦＥＴ構成のＧａＡｓＩＣに関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and relates to an E-D MES
This relates to a GaAs IC having an FET configuration.
従来技術によるＧａＡｓＩＣの断面図を第４図に示す。 A cross-sectional view of a GaAs IC according to the prior art is shown in FIG.
半絶縁性（Ｓｅａｔ−Ｉｎｓｕｌａｔｉｎｇ ） Ｇａ
Ａｓ基板１にテール分布補償用のＰ型層１２が形成され
たところへ、Ｅ−ＦＥＴ用Ｎ−型層４とＤ−ＦＥＴ用Ｎ
型層５とが形成されている。Semi-insulating Ga
At the place where the P-type layer 12 for tail distribution compensation is formed on the As substrate 1, an N-type layer 4 for E-FET and an N-type layer 4 for D-FET are formed.
A mold layer 5 is formed.
このときＤ−ＦＥＴ部を覆うレジストを形成し、イオン
注入してＮ−型層４のドーピングを行ない、Ｅ−ＦＥＴ
部を覆・うレジストを形成し、異なる条件゛でイオン注
入してＮ型層５のドーピングを行なう、。At this time, a resist is formed to cover the D-FET portion, and ions are implanted to dope the N-type layer 4.
A resist is formed to cover the N-type layer 5, and ions are implanted under different conditions to dope the N-type layer 5.
Ｅ−ＦＥＴ用Ｎ−型層とＤ−ＦＥＴＪｆＩＮ型層とのキ
ャリア濃度を変えるために、交互に注入しない領域をレ
ジストで覆ってイオン注入していた゛。In order to change the carrier concentration of the N-type layer for E-FET and the JfIN-type layer for D-FET, ions were implanted while covering the regions not to be implanted alternately with resist.
すなわちレジスト工程とイオン注入工程とを各２回実施
しなければならないという欠点があった。That is, there was a drawback that the resist process and the ion implantation process had to be performed twice each.
本発明の半導体装置の製造方法は、半絶縁性ＧａＡｓ基
板に絶縁膜として酸化シリコン膜、窒化シリコン膜、ア
ンドープＡＪＧａＡｓ膜のいずれかを堆積し、その絶縁
膜を透過してイオン注入することにより、異なるしきい
値電圧のチャネル層を形成するものである。The method for manufacturing a semiconductor device of the present invention includes depositing any one of a silicon oxide film, a silicon nitride film, and an undoped AJGaAs film as an insulating film on a semi-insulating GaAs substrate, and implanting ions through the insulating film. This forms channel layers with different threshold voltages.
本発明の第１の実施例について、第１図（ａ）〜（ｅ）
を参照して説明する。Regarding the first embodiment of the present invention, FIGS. 1(a) to (e)
Explain with reference to.
はじめに第１図（ａ）に示すように、半絶縁性ＧａＡｓ
基板１の表面にＭＯ−ＣＶＤ法またはＭＢＥ法により厚
さ２００〜４００人のアンドープＧａＡｓバッファ層２
と厚さ１５０〜２００人の絶縁性ＡｌＧａＡｓ層３とを
成長する。First, as shown in Figure 1(a), semi-insulating GaAs
An undoped GaAs buffer layer 2 with a thickness of 200 to 400 nm is formed on the surface of the substrate 1 by MO-CVD or MBE.
and an insulating AlGaAs layer 3 having a thickness of 150 to 200 nm.
つぎにＥ−ＦＥＴ領域をレジスト１３で覆い、燐酸系の
エツチング液で絶縁性ＡｌＧａＡｓ層３を選択工・ンチ
ングする。Next, the E-FET region is covered with a resist 13, and the insulating AlGaAs layer 3 is selectively etched using a phosphoric acid-based etching solution.
つぎに第１図（ｂ）に示すように、レジスト１３ａをマ
スクとして、Ｓｉ＋イオンを注入エネルギー’Ｅ＝３Ｃ
１−５０ｋｅＶ、注入量（ドース）φ□５〜７Ｘ１．０
１２ｃ＋＋−２注入してＥ−ＦＥＴ用Ｎ−型層４と叶Ｆ
ＥＴ用Ｎ型層５とを同時にドーピングする。Next, as shown in FIG. 1(b), using the resist 13a as a mask, Si+ ions are implanted at an energy of 'E=3C.
1-50keV, implantation amount (dose) φ□5-7X1.0
12c++-2 implanted into N-type layer 4 and leaf F for E-FET
The N-type layer 5 for ET is doped at the same time.
Ｄ−ＦＥＴ用Ｎ型層５のｖ、ｒで注入量（ドース）を設
定した。The implantation amount (dose) was set by v and r of the N-type layer 5 for D-FET.
Ｅ−ＦＥＴ用Ｎ−型層４のＶＴは、第２図に示すイオン
注入の深さ方向分布を用いて、絶縁性ＡｌＧａＡｓ層３
で余分の不純物をキャンセルするような厚さを設定した
。The VT of the N- type layer 4 for E-FET is determined by using the depth distribution of ion implantation shown in FIG.
The thickness was set to cancel out any extra impurities.
つぎに第１図（ｃ）に示すように、ゲート金属を堆積し
てからレジスト１３ｂをマスクとして選択エツチングし
てゲート電極７を形成する。Next, as shown in FIG. 1(c), gate metal is deposited and selectively etched using the resist 13b as a mask to form the gate electrode 7.
つぎにＳｉ”イオンを注入してＮ＋型オーミック層６を
形成する。Next, Si'' ions are implanted to form an N+ type ohmic layer 6.
つぎに第１図（ｄ）に示すように、周知のリフトオフ法
によりＡｕＧｅ／Ｎｉからなるソース電極８とドレイン
電極９とを形成する。Next, as shown in FIG. 1(d), a source electrode 8 and a drain electrode 9 made of AuGe/Ni are formed by a well-known lift-off method.
つぎに第１図（ｅ）に示すように、ＳｉＯ□からなる眉
間絶縁膜１１を被覆して、スルーホールを開口し金属配
線１０を形成して素子部が完成する。Next, as shown in FIG. 1(e), a glabellar insulating film 11 made of SiO□ is coated, through holes are opened, and metal wiring 10 is formed to complete the element section.
ここでは、絶縁膜として絶縁性ＡｌＧａＡｓ層を用いた
が、ＡｌＧａＡｓ層の替りにＣＶＤ法などによるＳｉＯ
□膜やＳｉＮ膜などを用いても同様の効果が得られる。Here, an insulating AlGaAs layer was used as the insulating film, but instead of the AlGaAs layer, SiO
Similar effects can be obtained by using a □ film, a SiN film, or the like.
′
つぎに本発明の第２の実施例について、第３図を参照し
て説明する。' Next, a second embodiment of the present invention will be described with reference to FIG.
はじめに半絶縁性ＧａＡｓ基板１の表面にＭＯ−ＣＶＤ
法またはＭＢＥ法により厚さ２００〜４００人のアンド
ープＧａＡｓバッファ層２と厚さ１５０〜２００人の絶
縁性ＡｌＧａＡｓ層３とを成長する。First, MO-CVD was applied to the surface of a semi-insulating GaAs substrate 1.
An undoped GaAs buffer layer 2 with a thickness of 200 to 400 thick and an insulating AlGaAs layer 3 with a thickness of 150 to 200 thick are grown by a method or an MBE method.
つぎにＥ−ＦＥＴ領域をレジスト１３で覆い、燐酸系の
エツチング液で絶縁性ＡｌＧａＡｓ層３を途中まで選択
エツチングしてＤ−ＦＥＴ領域にも薄い絶縁性Ａ１Ｇａ
Ａｓ層３ａを残す。Next, the E-FET area is covered with a resist 13, and the insulating AlGaAs layer 3 is selectively etched halfway with a phosphoric acid-based etching solution, and the D-FET area is also covered with a thin insulating AlGaAs layer 3.
As layer 3a is left.
このあとＳｉ＋イオンを注入することにより、Ｅ−ＦＥ
Ｔ用Ｎ−型層４とＤ−ＦＥＴ用Ｎ型層５とを同時にドー
ピングする。After this, by implanting Si+ ions, E-FE
The N-type layer 4 for T and the N-type layer 5 for D-FET are doped at the same time.
絶縁性ＡｌＧａＡｓ層３と絶縁性ＡｌＧａＡｓ層３ａと
の厚さが異なるなめ、Ｅ−ＦＥＴ用Ｎ−型層４とＤ−Ｆ
ＥＴ用Ｎ型層５とで異なるＶＴを有するチャネル層を同
時に形成することができる。Since the thickness of the insulating AlGaAs layer 3 and the insulating AlGaAs layer 3a are different, the N- type layer 4 for E-FET and the D-F
A channel layer having a different VT from the N-type layer 5 for ET can be formed at the same time.
さらにＥ−ＦＥＴにおいては絶縁性ｌＧａＡｓ層３の上
に、Ｄ−ＦＥＴにおいては薄い絶縁性ＡｌＧａＡｓ層３
ａの上にゲート電極７が形成されているので、いずれも
ショットキ障壁ΦＢが高くなるという効果がある。Furthermore, in the E-FET, a thin insulating AlGaAs layer 3 is placed on the insulating IGaAs layer 3, and in the D-FET, the thin insulating AlGaAs layer 3 is placed on the insulating IGaAs layer 3.
Since the gate electrode 7 is formed on a, both have the effect of increasing the Schottky barrier ΦB.
従来技術においては交互に注入しない領域をレジストで
覆ってイオン注入して、２回に分けてＥ−ＦＥＴ用チャ
ネル層とＤ−ＦＥＴ用チャネル層とを形成していたが、
本発明においてはレジスト工程とイオン注入工程とをま
とめて１回に削減することができた。In the conventional technology, regions that are not implanted alternately are covered with a resist and ions are implanted to form the E-FET channel layer and the D-FET channel layer in two steps.
In the present invention, the resist process and the ion implantation process can be reduced to one process.
第１図（ａ）〜（ｅ）は本発明の第１の実施例を示す断
面図、第２図はイオン注入の深さ方向の不純物分布を示
すグラフ、第３図は本発明の第２の実施例を示す断面図
、第４図は従来技術によるＧａＡｓ１Ｃの断面図である
。
ｌ・・・半絶縁性ＧａＡｓ基板、２・・・アンドープＧ
ａＡｓ／＜ッコア層、３・・・絶縁性ＡｌＧａＡｓ層、
３ａ・・・薄い絶縁性ＡｌＧａＡｓ層、４ ・Ｅ−ＦＥ
Ｔ用Ｎ−型層、５−Ｄ−ＦＥＴ用Ｎ型層、６・・・Ｎ１
型オーミック層、７・・・ゲート電極、８・・・ソース
電極、９・・・ドレイン電極、１０・・・金属配線、１
１・・・層間絶縁膜、１２・・・Ｐ型層、１３．１３ａ
・・・レジスト。1(a) to (e) are cross-sectional views showing the first embodiment of the present invention, FIG. 2 is a graph showing the impurity distribution in the depth direction of ion implantation, and FIG. 3 is a cross-sectional view showing the first embodiment of the present invention. FIG. 4 is a cross-sectional view of GaAs1C according to the prior art. l... Semi-insulating GaAs substrate, 2... Undoped G
aAs/<ccoa layer, 3... insulating AlGaAs layer,
3a... Thin insulating AlGaAs layer, 4 ・E-FE
N-type layer for T, N-type layer for 5-D-FET, 6...N1
type ohmic layer, 7... gate electrode, 8... source electrode, 9... drain electrode, 10... metal wiring, 1
1... Interlayer insulating film, 12... P-type layer, 13.13a
...Resist.
Claims (1)
膜、窒化シリコン膜、アンドープＡｌＧａＡｓ膜のうち
１つを堆積し、前記絶縁膜を透過してイオン注入するこ
とにより、異なるしきい値電圧を有するチャネル層を形
成することを特徴とする半導体装置の製造方法。 ２、半絶縁性ＧａＡｓ基板にアンドープのIII−Ｖ族化
合物混晶膜を堆積してから、該半導体膜を選択エッチン
グして、イオン注入することにより、ＡｌＧａＡｓ／Ｇ
ａＡｓヘテロ接合型電界効果トランジスタとＧａＡｓホ
モ接合型電界効果トランジスタとを同一基板上に形成す
る請求項１記載の半導体装置の製造方法。[Claims] 1. By depositing one of a silicon oxide film, a silicon nitride film, and an undoped AlGaAs film as an insulating film on a semi-insulating GaAs substrate, and implanting ions through the insulating film, different A method for manufacturing a semiconductor device, comprising forming a channel layer having a threshold voltage. 2. After depositing an undoped III-V group compound mixed crystal film on a semi-insulating GaAs substrate, selectively etching the semiconductor film and implanting ions, AlGaAs/G
2. The method of manufacturing a semiconductor device according to claim 1, wherein the aAs heterojunction field effect transistor and the GaAs homojunction field effect transistor are formed on the same substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2288810A JPH04162564A (en) | 1990-10-25 | 1990-10-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2288810A JPH04162564A (en) | 1990-10-25 | 1990-10-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04162564A true JPH04162564A (en) | 1992-06-08 |
Family
ID=17735028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2288810A Pending JPH04162564A (en) | 1990-10-25 | 1990-10-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04162564A (en) |
-
1990
- 1990-10-25 JP JP2288810A patent/JPH04162564A/en active Pending
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