JPH04162289A - Dynamic memory - Google Patents

Abstract

PURPOSE:To extend an operating margin by providing a power source voltage drop circuit for supplying a large current when a sense amplifier amplifies and supplying a small current at the time of a page mode. CONSTITUTION:A power source voltage drop circuit for supplying a large current has a differential amplifier A1, an inverter I1, a NAND circuit G1, and a transistor QP1, and a power source voltage drop circuit for supplying a small current in a page mode has the amplifier A1, and a transistor QN1. A large current is supplied at the time of sense amplifying in a RAS/CAS cycle, and its output is turned ON, OFF corresponding to an activation signal. Thus, an operating margin can be extended and stably operated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic memory, and particularly to a dynamic memory having a high voltage power supply voltage circuit.

[Conventional technology]

Dynamic memory has quadrupled its memory capacity in three years. In particular, in order to increase the capacity, finer processing is required, the channel of the transistor is also becoming finer, and the withstand voltage VDS between the drain and source is becoming lower. For example, in a 16M dynamic memory, VDS is 5V or less.

In particular, regarding the cell transistor, a short channel transistor is required to make the cell smaller, and therefore a high voltage circuit as shown in FIG. 4 is used to lower the voltage applied to the cell than the power supply voltage.

This step-down circuit consists of a P-channel transistor QpH,1
2. It is a mirror type amplifier circuit consisting of N channel transistors QN11 to QN13, and if the power supply voltage Vint is lower than the reference voltage Vref, the transistor QN14
By this, the potential of Vint is raised. In addition, this Vi
Since nt is used as an internal power supply, V int only flows out current and does not flow in, so V i n
A transistor for lowering the voltage of t becomes unnecessary.

Internal power supply voltage Vint is connected to a number of sense amplifiers SA as shown in FIG. Each sense amplifier S
A bit line pair BL, BL is connected to the bit line pair BL, and a large number of cells 10 are connected to the bit line pair BL, BL to form one row 20.

Furthermore, as shown in Fig. 6, the sense amplifier SA usually consists of a clip-flop consisting of transistors QP16, 17, and QN16゜17, which are connected to transistors QNI5 and QP15 with common points Np and Nn. . Transistor QP15. The other ends of QN15 are connected to the internal voltage Vint and ground, respectively. The sense amplifier activation signal φS and a signal inverted by the NAND circuit G1 are input to the gates of the transistors QN15 and QP15, respectively.

The read operation of this memory is shown in FIG. 7(a).

Shown in (b). The bit line pair BL and BL are precharged to the same intermediate level before reading out the cell.
At time T1, when word line Wl or W2 is selected, a signal is output to bit line pair BL, BL. If word line W1 is now selected and the data to be read is "1", then the seventh
Figure (a).

As shown in (b), bit line pair B
Signals are read out to L and BL. At time T2, the sense amplifier activation signal φS is activated, and by time T3, the bit line pair BL, BI- reaches a predetermined level and the amplification is completed.

If this memory is to operate at high speed, for example, if access is 60 ns, then the time between time T2 and T3 in FIG. 7 must be approximately 15 ns. Now 16M
Assuming a bit dynamic memory, the number of bit lines to be read out at the same time is 8,000 rows. 0.3pF per line,
If the amplitude of the bit line is 1.5 .mu., the amount of charge to be charged in -times of reading is 3600 pF. Therefore, time T2T31? The current flowing through J is 240 mA.

This current is transferred to the transistor QN1 of the internal high voltage circuit in Fig. 4.
4 will flow. However, since the current supply capability of the transistor QN14 is proportional to the square of the gate and source windings, it becomes extremely slow near the completion of charging. Even if the channel width of the transistor QN14 is set to 4 mm, it takes more than 40 nS to charge the bit line, which is not suitable for high-speed memory.

An example of a circuit that improves this drawback is shown in FIG. In FIG. 8, a transistor QP1 with Vref and Vint as inputs is shown.
1, 12, and QNII-13, a mirror type amplifier circuit All is shown. The source of the transistor QPII is used as the output of the amplifier circuit and the input of the inverter II. If activation signal φa is at O level, NAND@path G
The output of 1 is at the "1" level, and the transistor QPI is in the off state. When the activation signal φa becomes a level, the output of the NAND gate follows the output of the inverter 11, that is, the output of the amplifier circuit All.

Here, if Vint is lower than Vref, the output of amplifier circuit All becomes O level, the output of NAND gate G1 becomes O level, transistor QPI is turned on, and Vint is charged. Therefore, if the activation signal φa is set to the level before the sense amplifier activation signal φS becomes the level, the bit line can be charged, and if this charging lowers the potential of Vint, the transistor QPI Turns on and charges.

Furthermore, when the voltage of Vint becomes higher than Vref, charging of the bit line is completed, and therefore transistor QPI is turned off. Here, since the gate potential of the transistor QP1 is always at the 1 or 0 level, the current capacity of the transistor in the on state is large. Therefore, the channel width of the transistor QP1 only needs to be about 1 mm, and the load on the amplifier circuit A11 is only the inverter ■1, which is small.
The amplifier circuit itself can also be made smaller.

[Problem to be solved by the invention]

However, normal dynamic memory has an operation called page mode. In this operation, once the memory is activated, cells on the same word line can be accessed one after another by changing the column address, but of course there is also a write operation, so an operation to invert the state of the bit line occurs. If this inversion operation continues, the -times of the Beige mode cycle is about 50 nS, and the current flowing out from Vint is as small as 1 mA, but when the potential of Vint decreases and becomes lower than Vref, the transistor QPI is turned off again. It will turn on. However, there is a circuit delay until Vint becomes low to Vref and transistor QPI is turned on. In particular, since the channel width of the transistor QPI is as large as 1 mm, the load on the NAND circuit G1 is 1 to 2 pF, resulting in a delay of several nS. Therefore, Vint, that is, the level of the bit line, is 0.1~. Q.2
V will fall below a predetermined level. Naturally, there is a delay until the transistor QPI turns off, and the potential of the bit line similarly increases by 0.1 to 0.2V.

Since this page mode can be stopped at any time, the potential of the final bit line will change by 0.2 to 0.4 . Since this difference is the midpoint between the 1.0 level of the previous bit line pair in the precharge state, the bit line becomes the level of the next bit line. Since the level of the cell is determined as 1.0 based on the level of the bit line, its fluctuation causes a decrease in the operating margin, and since the level of the cell is set low by the high voltage circuit, the decrease in the margin becomes more of a problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a dynamic memory that solves these problems, widens the operating margin, and enables stable operation.

[Means to solve the problem]

The configuration of the dynamic memory of the present invention is RAS/CAS
The first internal voltage drop circuit is capable of supplying a large current when amplifying the cycle sense amplifier, and its output can be turned on and off in response to an activation signal, and the second internal voltage drop circuit is capable of supplying a small current in the basic mode. and an internal voltage effect circuit.

In the present invention, the first internal voltage drop circuit includes a mirror type differential amplifier circuit that compares a reference voltage and an output voltage, an inverter that inverts the output of this differential amplifier circuit, and activates the output of this inverter. It consists of a gate circuit that is turned on and off by a signal, and a P-channel transistor whose output is connected to the gate and whose source is the output terminal.
The second internal voltage drop circuit can be composed of an N-channel transistor whose gate is connected to the output of the differential amplifier circuit and whose source is the output terminal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention. In this embodiment, the reference voltage Vref and the output Vin of the voltage drop circuit are
A mirror-type differential amplifier circuit A1 that receives t as an input, an inverter 1 that receives the output of this amplifier circuit A1 as an input, and a NAND circuit G1 that receives the output of this inverter 11 and an activation signal φa as inputs. A transistor QPI whose gate receives the output of this NAND circuit G1, and a differential amplifier circuit A.
1 and a transistor QN1 whose gate receives the output of 1 as an input. These differential amplifier circuit A1, inverter I
1. A circuit consisting of a NAND circuit G1 and a transistor QPI constitutes a power supply voltage drop circuit that supplies a large current, and a differential amplifier circuit and a transistor QNI constitute a power supply voltage drop circuit that supplies a small base-mode current. It consists of With this configuration, the page mode current can be supplied at high speed, and the variation in the level of the bit line, which is conventional, can be eliminated.

Note that the mirror type differential amplifier circuit A1 may be the mirror type differential amplifier circuit All shown in FIG. 8, but since the activation signal φa is provided in the first embodiment, the transistor QN13 in FIG. The gate may be controlled by an activation signal or an equivalent signal. In addition, the transistor QPI of the mirror type differential amplifier circuit All shown in FIG.
Since the source contacts of transistors I and 12 are in reverse phase with each other, the input of inverter 1 may be used as the source contact of transistor QPII, and an inverter may be inserted between inverter 1 and NAND circuit G1. This is a selection of whether it is better to drive the NAND circuit in two stages or in three stages.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

Reference voltage Vref (1) and voltage drop circuit output vint
A mirror-type differential amplifier circuit A1 takes the input as an input, an inverter 11 takes the output as an input, the output of the inverter 1 and the activation signal φa are connected to the NAND circuit G1, and the NAND circuit G1 receives the output of the inverter
Transistor Q input to the output gate of ND circuit G1
PI, a second mirror-type differential amplifier circuit A2 which inputs the reference voltage Vr e f (2> and the output Vint of the voltage drop circuit), and a transistor QN1 whose gate inputs the output. There is.

As in the first embodiment, the differential amplifier circuit A1, the inverter I
1. The circuit consisting of NAND circuit G1 and transistor QP1 constitutes a power supply voltage drop circuit that supplies a large current, and the differential amplifier circuit A2 and transistor QNI constitute a power supply voltage drop circuit that supplies a small current in page mode. It consists of Compared to the first embodiment, having two differential amplifier circuits means that the delay from when Vint matches V r e f (1) to when transistor QPI turns off is 5 nS or more. Since Vint will be overdriven if there is, V r e for large current and small current
f is separated so that fluctuations in the output Vint of the power supply voltage drop circuit can be further reduced.

By doing so, the page mode current can be supplied at high speed, and the variation in the level of the bit line, which is conventional, can be eliminated.

FIG. 3 is a circuit diagram of a third embodiment of the present invention. A mirror type differential amplifier circuit A1 receives the reference voltage V r e f and the output Vint of the voltage drop circuit as input, an inverter 1 receives the output thereof as input, and the output of this inverter 11 and the activation signal T1 are input. NOR circuit G2 and this NOR circuit G2
Transistor Q that inputs the output of OR circuit G2 to its gate
PI, and a transistor QNI whose gate input is the output of the mirror-type differential amplifier circuit A1.

The activation signal T7 is a level when inactive and is O level when active. When inactive, the output of the NOR circuit G2 is 0 level, and the transistor QPI is always on and Vi
Set nt to power level. However, since the transistor QP15 in FIG. 5 is in an off state when it is inactive, the voltage of Vint is not applied to the sense amplifier. The transistor QPI supplies a large current and the transistor QNI supplies a small current, as in the first embodiment.

〔Effect of the invention〕

As explained above, the present invention has a power supply voltage drop circuit that supplies a large current when the sense amplifier is amplifying and supplies a small current when in page mode, so that the normal RAS
In both /CAS cycle and page mode, variations in bit line levels can be eliminated and the operating margin can be expanded.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a power supply voltage drop circuit according to an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams of second and third embodiments of the present invention, and FIG. 4 is a circuit diagram of a conventional power supply voltage drop circuit. Schematic diagram of voltage effect circuit,
Figure 5 is a circuit diagram of the memory array part of a general dynamic memory, Figure 6 is a circuit diagram of its sense amplifier part,
Figure 7(a). (b) is a waveform diagram when reading and amplifying the memory cell,
FIG. 8 is a circuit diagram of a conventional improved power supply voltage drop circuit. Al, A2. All... Mirror type differential amplifier circuit, BL
, BL...Bit line pair, G1...NAND circuit, G
2...NOR circuit, 11...Inverter, QPI. 11-17...P channel transistor, QN1.
11 to 17...N channel transistor, V r
e f---Reference voltage, Wl, W2 word line, φa...
- Activation signal, 10... Cell, 11... Sense amplifier (SA), 20... One row of array.

Claims (1)

[Claims] 1. A first internal voltage drop circuit capable of supplying a large current during sense amplifier amplification in the RAS/CAS cycle and capable of turning on/off its output in response to an activation signal. , and a second internal voltage effect circuit capable of supplying a small page mode current. 2. The first internal voltage drop circuit includes a mirror type differential amplifier circuit that compares a reference voltage and an output voltage, an inverter that inverts the output of this differential amplifier circuit, and an activation signal that inverts the output of this inverter. It consists of a gate circuit that turns on and off, and a P-channel transistor whose gate is connected to the output of this gate circuit and whose source is its output terminal.A second internal voltage drop circuit connects the output of the differential amplifier circuit to its gate. 2. The dynamic memory according to claim 1, comprising an N-channel transistor connected to each other and having a source as an output terminal.