JPH023159A - Semiconductor device - Google Patents

Abstract

PURPOSE:To drive a load at a constant current to a constant current source fixed in advance in a current mirror circuit, to arbitrary control a charging/ discharging current and to reduce noise in an LSI by the suppression of an over current by providing the current mirror circuit controlled with an input pulse as a load driving circuit independently of the circuit for the charging/ discharging of the load. CONSTITUTION:The current mirror circuit of a driving circuit DRV of a semiconductor device is controlled by an inverter consisting of transistors TrQ1 and Q2, and when the TrQ2 is off and the Q1 is off, a mirror circuit is formed between a TrQ3, a constant current source (i/n) and an output driving TrQD. Besides, when the TrQ2 is off and the Q1 is on, the TrQD becomes off, the current entrance of a current source is i/n, the gate width of an MOSTr is W/n, the gate width of the gate of a QD is W, and the on current of the TrQD is a constant current (i). Then, even if the gate width W or the threshold voltage of the Tr change by the dispersion of a producing process, the i/n is constant and the driving of the TrQD is approximately constant.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device, and in particular to a circuit suitable for suppressing transient current, coupling noise due to unbalanced anti-phase signals, or amplitude of pulse voltage. Regarding.

[Conventional technology]

Conventionally, when charging and discharging a large load capacity at high speed, it has been considered a problem that the transient current becomes excessive. For example, in dynamic random access memory (hereinafter referred to as DRAM) that uses dynamic memory cells, excessive transient current when charging and discharging a large number of data at once has become a problem, and as a result, in 1986 , Solid State Device Conference Digest, pp307-310. A voltage limiter circuit system as shown in Figure 1 has been proposed.

[Problem to be solved by the invention]

However, this method charges and discharges the data line using the internal power supply voltage, which is obtained by lowering the external power supply voltage within the chip.
They only achieved low current by effectively lowering the power supply voltage, and charging and discharging were left unchecked. For this reason, an imbalance occurs between the charging speed of one of the data line pairs precharged to a voltage that is 1/2 of the power supply voltage and the discharging speed of the other, and the start time of charging and discharging, which causes an imbalance between the other conductor (substrate).

Coupling noise occurs on non-selected word lines, etc.).

Such noise is a particularly serious problem in circuits that operate at high speeds and at low amplitudes using external or internal power supply voltages.

In addition, the charge/discharge transient currents that change in response to variations in the load driving ability of MOS transistors due to variations in the gate length or threshold voltage of MOS transistors due to manufacturing variations are not actively controlled, so there is a limit to the ability to reduce the current. there were.

An object of the present invention is to provide a semiconductor that charges and discharges a load capacitor at any predetermined constant current, independently controls charging time and discharging time, and achieves low transient current independent of manufacturing variations. Another object of the present invention is to provide a semiconductor device with low transient current and low power consumption by combining it with a voltage limiter circuit system. moreover.

It is an object of the present invention to provide a semiconductor device in which the resistances of an operating circuit, a high voltage power supply, and a low voltage power supply are set to be equal, and the charging and discharging times are not equal due to the difference in the resistance values.

[Means to solve the problem]

The above purpose is to provide a current mirror circuit that is controlled by input pulses as a load drive circuit and independently provide it for charging and discharging the load, thereby supporting a predetermined constant current source within the current mirror circuit. This is achieved by driving the load with a constant current and setting the resistance of the wiring through which this current flows to be equal on both the charging and discharging sides.

[Effect]

Current mirror circuits are less susceptible to variations in process conditions and can therefore reduce transient currents. Furthermore, by providing separate charging and discharging,
Charging time and discharging time can be controlled independently.

Furthermore, by using a voltage limiter, it is possible to maintain a low constant voltage, thereby reducing power consumption.

〔Example〕

An embodiment of the circuit of the present invention will be described below with reference to FIG.

The operation timing will be explained with reference to FIG.

In a DRAM, one of the data pair lines is connected to a memory cell (one M
Depending on the read information of an OS transistor ((hereinafter referred to as MO8T)) and a memory cell consisting of one capacitor, a well-known sense amplifier formed of pMO8T is charged, and the other is Discharging is performed at MOST.

In this case, for example, in the latest megabit DRAM, 1
It is necessary to simultaneously charge and discharge 024 pairs of data lines at high speed. The total capacitance of this data line is 500 to 1000 pF
Since the voltage reaches even more, overcurrent becomes a problem. This charge is pM
This is performed by the drive circuit DRV connected to the common line cQ of the flip-flop, which is a sense amplifier formed of O8T.
The discharge is caused by the drive circuit D connected to the common line cQ of the flip-flop with a sense amplifier formed by MOST.
It will be held in the RV. This embodiment is characterized in that each of these drive circuits is composed of a current mirror circuit or a current mirror circuit and a comparison circuit.

FIG. 1 shows an example in which the drive circuit DRV is composed of a current mirror circuit and a comparison circuit, and the drive circuit DRV' is composed of a current mirror circuit. Even if DRV' is configured with a current mirror circuit and a comparison circuit, it is acceptable.

The characteristics of these circuits will be explained below using DRV as an example. The current mirror circuit is controlled by a type of inverter consisting of transistors Q 1 +Qz. When Qz is on and Qt is off, Q3 and constant current source (i/n)
A current mirror circuit is formed between Qz and output drive transistor Qn, and when Qz is off and 01 is on, QD
is off. The current inlet of the current source in the mirror circuit is i
/n, MOS 'r gate width w/n, Qo
Let W be the gate width of .

The on-current of Qo becomes a constant current i. Even if W, gate length, or transistor threshold voltage changes due to manufacturing process variations, if I/O is kept constant, Q
The drive current of o becomes approximately constant.

The reason why the constant current sources are i/n and w/n is to reduce the current consumption and the occupied area.
The larger n is, the better.

The comparator is connected to a predetermined internal power supply Vc, for example, 4
V) and the output voltage Vo.

When VCL>Vo, the output of the comparator becomes a high voltage, and conversely, when Vct<Vo, it becomes a low voltage. Furthermore, Vc
t, may be generated within the chip from Vcc (externally applied power supply voltage).

The operation will be explained based on the above preparation.

In a normal DRAM, the data pair line is set to approximately half the value of vO during the precharge period. Since this is a so-called half precharge method, the common drive line aQ or all the data pair lines are precharged to Vat, /2 during the precharge period. In this state, when a pulse is applied to the selected word line, a minute differential read signal appears on each data pair line. This situation is shown in Figure 2.
, Do symmetry is representatively shown. Then nMO8T
In the sense amplifier formed of pMO3T and pMO3T, the low voltage side is discharged to Ov, and the high voltage side is charged to VCL. The discharge is applied to the common drive line aQ' of each nMOST.
' by applying low voltage pulses.

Here, only an example in which charging is performed by a pulse applied to the common drive line aQ of PMO3T will be described below. cQ is driven by applying an input pulse φ. When the input pulse φ turns on (high voltage is input), the control circuit AN
The output voltage of D becomes a high voltage, the gate voltage vO of Qo becomes the output voltage Vs of the constant current source, and Qo drives the load with a constant current i. As a result, the load voltage vO is Vat, /
The voltage rises at a constant speed from 2, but when it exceeds VCL, the comparator operates and the output of the control circuit AND becomes a low voltage, turning on Ql, turning off Qz, turning off Qo, and Vo is clamped at approximately Vat. It will be done. As a result, one data line of each data pair is charged from VCL/2 to approximately vO.

According to the embodiments described above, since the data line can be charged with a substantially constant current, the data line can be charged at high speed without increasing transient current. Also, by keeping 10 constant,
Even if there are fluctuations in power supply voltage or manufacturing variations, the effects can be minimized. The same applies to discharge. Furthermore, since the data line voltage can be kept low, power consumption is also reduced.

As described above, the drive circuit using the current mirror circuit allows the data line to be charged with a nearly constant current. To obtain constant current using this current mirror circuit, 1M03
TQo is in the saturation region (l Vo −Vcc l 2
It is preferable to operate at Vs Vcc VT1 ). However, as shown in FIG. 3, this condition may not be satisfied over time depending on the operating conditions and the like. In other words, the potential of vO is VCL/
2 and becomes higher than the voltage of Vs 1Vtl (VT is the threshold voltage of Qo, and because it is a P channel type, it generally has a negative value), Vo Vcc l < l Vx - Vcc - Vt
1, and MO8Qo operates in a non-saturated region. As a result, the current i becomes smaller and Vo becomes Vct, (4V
) will also be delayed. Further, even if Qo operates in the saturation region, as QD channels become shorter in the future, the dependence of the drain current on the drain-source voltage will become more pronounced, causing the same problem as above.

FIG. 4 shows another embodiment that solves the above problem and enables even better constant current charging.

In this example, MO8T constituting the current mirror circuit
Qoti-m (indicated here as m = 4) are provided, and these are sequentially turned on over time to achieve a constant current. That is, as shown in FIG. 5,
By sequentially applying φ work to φ number, ANDz to ANDa, SW1 to SWt consisting of a kind of CMOS inverter,
Connect the gates of Qo to QD4 to Vs in sequence, and connect each M
Turn on O8T. This increases the driving capacity over time.

Aim for constant current. Thereafter, as in FIG. 1, the comparator detects that Vo has reached Vcm, turns off Qot=Qoa, and stops the operation. As a result, the data line voltage is set to approximately Vat.

According to this embodiment, by appropriately selecting the gate width of each MOS Qoz to QD4, it is possible to keep the current i substantially constant over the entire operation period. Note that since each MO3 originally has a current mirror configuration, the current 10 is kept constant, and as described above, the influence of manufacturing variations can be minimized.

Discharge can be done in the same way.

Furthermore, as is well known, when charging and discharging data lines, after the start of charging and discharging, when the signal difference between Do and Do is small, charging and discharging is performed slowly, and when the signal difference between DO and DO becomes large to a certain extent, charging and discharging is started at high speed. In this method, the sensitivity of the sense amplifier is excellent. This method can also be easily implemented in the embodiment of FIG. Note that a plurality of constant current sources of the current switch may be provided and switched between them.

FIG. 6 shows a more preferable embodiment for keeping the current i constant, in which the voltage conversion circuit vPS provided in the chip
The external power supply voltage Vcc, for example, 5V, is set to a certain voltage Vc in advance.
c' It is operated with an internal voltage converted to a constant voltage of, for example, 4.5 V.

The vPS of this embodiment is constructed of a circuit described in Section 244 of Volume 2 of the 1981 Institute of Electronics and Communication Engineers General Conference National Conference.
c' and comparison voltage VC! A comparator is provided to compare the voltage with L' (4,5V), and its output voltage is applied to the gate of MoS transistor Qv, and the current flowing through Qv is controlled to keep its output voltage VCC equal to VCL'. This is because I gave negative feedback. In addition, the current source iv shown by the broken line in the same figure is a bias current to keep Vcc' constant with high accuracy even if the DRV is off and the VPS output current is O, and it can be provided depending on the purpose. You can also
It may be omitted in some cases. Alternatively, in synchronization with the DRV operation, for example, if the DRV is off, iv is played,
A method in which iv is set to O when it is on may also be considered.

According to this embodiment, since the DRV always operates at a constant voltage Vcc', the output current of the DRV can be kept constant regardless of fluctuations in the power supply voltage.

It should be noted that the vPS circuit may be modified in various ways other than those shown in this embodiment, such as those disclosed in Japanese Patent Application No. 56-168698
The voltage conversion circuit disclosed in Japanese Patent Application No. 57-220083 can be applied as is.

FIG. 7 shows that in the embodiment of FIG. 6, by setting Vcc to a desired data line voltage, for example 4, the function of DRV as an electrical limiter is substituted by VPS, and DRV is operated only as a current limiter. It is something that Therefore, parts necessary for voltage setting such as a voltage comparator in the DRV are removed.

According to this embodiment, the data line voltage is controlled by VPS, and the photoelectric current is controlled by DRV, and the circuit configuration is simpler than that in FIG. 6, and it has the same effect, that is, it is not affected by fluctuations in the power supply voltage. The output current i can be kept constant.

Note that the embodiment shown in FIG. 6 or 7 can also be applied to the embodiment shown in FIG. 4. By these.

The current i can be kept constant without being affected by the power supply voltage or the operating range of the MOS.

The explanation has been given above mainly using DRV as an example.

DRV' driving CQ' can be configured in a similar manner.

Furthermore, DRV and DRV' are also current source circuits.

Since the comparison circuits and the like can be configured completely independently, it is easy to charge and discharge the data line pair Do, Do simultaneously and to make the charging time and the discharging time equal. Therefore, Do,
Other conductors (
The present invention has the advantage of not generating noise on the substrate (substrate, unselected word lines, etc.), but this noise has become a serious problem as the latest megabit DRAMs become more integrated due to miniaturization. Furthermore, in the future, DRA
As the amplitude of the logic signals in the M internal circuits continues to decrease, and when they reach the ECL level, the DRAM no longer operates normally due to this noise.Therefore, the present invention is essential to prevent such R
This is essential for ensuring the reliability of AM.

For example, BiCMO3 technology can be used to realize a DRAM with an ECL interface that operates at high speed and with stable operation.

Furthermore, the present invention is not limited to application to DRAM data line charge/discharge circuits, but is applicable to all multi-bit configurations (configurations in which multiple data outputs are output from one chip) where transient currents are a particular problem. If applied to the data output section of a memory or the address output section of a microcomputer, it is effective as a countermeasure against transient currents.

When the present invention is applied to a data line charging/discharging circuit of a DRAM, and charging and discharging of the data line are started at the same time, and the charging time and the discharging time are made equal, the driven DRV and DRV' are set according to the desired circuit according to the present invention. However, the wiring resistance from these circuits to the sense amplifier, or the wiring resistance from the external Vcc power supply and ground power supply to these circuits remains a problem.

That is, for example, if the resistances from the DRV and DRV' circuits to the sense amplifier are different, the balance between charging and discharging will be immediately lost. An example for solving this problem will be described below.

FIG. 8 shows an embodiment of the present invention. An external low voltage power supply (
For example, a bonding pad P1 connected to an external high-voltage power WX (for example, 5V) and a bonding pad P2 connected to an external high-voltage power WX (for example, 5V) are generally arranged on both sides of the chip as shown in the figure, and both are connected to one side of the chip. It is arranged so that there is no For this reason, the distances from the two pads PL and P2 are not equal except at the center of the chip, and if the wiring is directly connected from the one pad PL and P2, there will be a difference in resistance.

The imbalance in data line charging and discharging operations caused by this difference in resistance also becomes a major cause of noise.

Therefore, in this embodiment, the low voltage power supply wiring is first conducted from the pad P1 to the center of the chip using the wiring Ω, &, then in the long side direction of the chip using the wiring Qab, and then the power supply to the desired circuit is connected using the switches Sax to 5axn. The high-voltage power supply wiring for wiring 12111 to Qdxn is similarly routed from pad P2 to the center of the chip using wiring Ω, then crosses the chip using wiring Qub as shown in the figure, and then is connected using switches Sux to Suxn. Power supply wiring flu to Quz to desired circuit. Do the following.

For example, in the case of the sense amplifier S shown in the figure, the distances from the pads to both power supplies of this circuit can be made the same, and the sheet resistances can be made the same very easily. The same applies to any other sense amplifiers in memory array MA. In this figure, PR indicates a peripheral circuit, but other layouts are also possible, and Sar to S
42n l S ul to S uxn may be combined into one.

Further, in this embodiment, PL and P2 are used as pads for connecting to an external power supply, but for example, the position of Pl in FIG.

The DRV' shown in the embodiment of FIGS. 4, 6, and 7 is placed, and the DRV shown in the embodiment of the figure is placed at the location P2, and the DRV'/7) output 1cQia is obtained.

Similarly, when ρah is connected to the output of the DRV, there is an advantage that the resistances from these circuits to the sense amplifier can be made the same. In addition, the DRV and DRV' may be distributed in several locations, or the MO8Q for output of the DRV and DRV' may be arranged in several locations.
o and Qo' are respectively Su1~Suxnr Sd
t~S,i. The same is true when used in place of ``. Furthermore, the entire DRV and DRV' are switched S ut~
It may be used instead of 5uzn l 5ate 5azn.

FIG. 9 is a diagram showing another embodiment of the present invention.

In this embodiment, the power supply lines are routed from pads PL and P2 to the center of the chip by wirings Qdl and Qo, respectively.The wirings Ω-b and Qub that traverse the chip are connected to the outer periphery of the chip of memory array MA as shown in the figure. The switch S ax”” S man HS ut~S ur
Power supply wiring 941 to A to the desired sense amplifier by n
azn * (Connect to I Lll-Q uxn.

By these.

For example, in the sense amplifier Sa, although there is a difference in resistance due to Qmx and Qul, this is small, and there is an advantage that the difference in resistance between the two power supply lines in the main long side direction of the chip can be eliminated. The example using DRV and DRV' is the same as that shown in FIG.

FIG. 10 is a diagram showing another embodiment of the present invention.

In this embodiment, wiring is done in the long side direction of the chip using 1, for example, Pl to Q, &, and then connected to the power supply wiring (1m1 to QdZn) by switches Sm1 to 5d2n. At this time, the closer the distance between the pad PL and the switch, the lower the resistance of the switch. This allows the resistance of the power supply line in the long side direction of the chip to be the same.The same applies to the wiring from P2.It can also be applied when using DRV and DRV'.

FIG. 11 is a diagram showing another embodiment of the present invention.

In this embodiment, for example, the wiring Qull+ Qull+ u
When the sense amplifier connected to dllrQ alz operates.

Other wiring uuxl+ QuxtHQaxLr Qaxl
CX=2 to 2n) are connected to switches 582 (x=
2 to 2n, y=1 to 4). This prevents other sense amplifiers from operating. At this time Q ull
In the sense amplifier connected to lQ axl, the length of the low voltage power supply wiring from Pl is short, and therefore the resistance is small. On the other hand, although the length of the high voltage power supply wiring from P2 is long, at this time, as shown in the figure, a large number of wirings are connected in parallel from the switch Su. This has the advantage that the resistance difference can be reduced. There are similar advantages when using DRV and DRV'.

The present invention is not limited to application to the power supply wiring of a sense amplifier, but it is desired to equalize the wiring resistance from two power supplies arranged at a distance such as PL and P2 to a circuit using the power supply. Applicable to cases.

〔Effect of the invention〕

As described above, by controlling the current mirror circuit and equalizing the wiring resistance as in the present invention, it is possible to arbitrarily control the charging and discharging current, which was left unchecked in the past, so that transient currents can be suppressed, and therefore LSI chips Since the internal noise is reduced, chip design becomes easier, and the user can also easily design the card because the noise from the chip mounted on the card is reduced. Furthermore, since constant voltage output pulses can be obtained at low voltage, the power consumption of the chip can also be reduced.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a timing diagram explaining the addition of new advantages to FIG. 1, FIG. 4 is a circuit diagram showing an embodiment of the present invention, and FIG. 6 and 7 are circuit diagrams showing another embodiment of the present invention, and FIGS. 8 to 11 show an embodiment of the present invention regarding wiring resistance. It is a circuit diagram. DRV, DRV'...Drive circuit, PP, PN-...
Control signal, Q da, Q ah, Q as ~ Q az
n ”'Low voltage power supply wiring, Quh+ QubHQu
x ~ Quxn - High voltage power supply wiring, S^, Ss...
・Sense amplifier.

Claims (1)

Claims: 1. A semiconductor device characterized in that at least one current mirror circuit is formed by at least one pulse input voltage, and the output current of the mirror circuit is a constant current. 2. The output voltage of the current mirror circuit is compared with a predetermined comparison voltage by a comparator, and the mirror circuit is controlled with the output voltage of the comparator according to the comparison result. The semiconductor device according to item 1. 3. In a semiconductor device configured with a circuit that requires a high voltage power supply used for charging a load and a third voltage power supply used for discharging the load, the resistance of the power supply wiring connecting the high voltage power supply and the circuit is A semiconductor device characterized in that a low voltage power supply and a resistance of a power supply wiring connecting the rotation are set to the same value.