JPH04160642A - Computer system - Google Patents

Abstract

PURPOSE:To simply test a program by generating an interruption by means of a timer counter. CONSTITUTION:This computer system is provided with the timer counter 5 started by the interruption start of an interruption controller 4 to add '1' to its count value in each fixed time, a reading means for reading out the count value of the counter 5 to a CPU 3 and the CPU 3 for comparing the read count value with the count value of the preceding interruption, and when their difference exceeds a prescribed value, displaying abnormality on a display device 6 in order to indicate that a tested program illegally inhibits interruption for a long period. Namely, when interruption is executed, the count value of the counter 5 is compared with that of the preceding interruption, and when their difference exceeds the prescribed value, the generation of abnormality is decided and an alarm is generated. Consequently, the time of illegal interruption inhibition due to the execution of a tested program is simply checked and error detection in interruption control is easily executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for program testing of computer systems. The present invention relates to a computer system that can easily detect errors in interrupt control.

〔overview〕

The present invention uses a timer counter to generate an interrupt in a computer system equipped with a central processing unit and a display device, and compares the current count value with the previous count value to determine whether or not there is an abnormality. By doing so, it is possible to easily check the time period during which interrupts were illegally disabled due to the execution of the program under test.

[Conventional technology]

Conventionally, this type of program test has been performed by checking the interrupt-disabled execution time from the program list or by using hardware test equipment such as a logic analyzer.

[Problem to be solved by the invention]

The above-mentioned conventional program testing has the disadvantage that errors are likely to occur because the list is checked manually, and checking using hardware testing equipment requires time and effort to install the equipment.

The present invention solves these problems by providing a system that can eliminate confirmation errors and, when using equipment for hardware testing, allows testing without the hassle of installing the equipment. The purpose is to provide.

[Means for Solving the Problems] The present invention provides a computer system that includes a central processing unit that executes a program under test and an interrupt processing program, an interrupt controller that generates an interrupt for the central processing unit, and a display device. , comprising a timer counter that is activated by the start of an interrupt from the interrupt controller and increments the counter by 1 at regular intervals; the central processing unit includes means for reading the count value of the timer counter; and a count value of , and when the difference is greater than or equal to a predetermined value, the program under test indicates that the program under test has illegally prohibited interrupts for a long time, and displays an abnormality on the display device.

The central processing unit includes means for automatically interrupting the processing as well as displaying the abnormality display means, and the central processing unit displays the read count value when the difference between the read count value and the previous count value does not exceed a predetermined value. It is desirable to include means for storing the previous value in place of the previous value.

[Effect]

When an interrupt is executed, detect the interrupt, read the count value of the timer counter, compare the read count value with the count value of the previous interrupt, and detect an error if the difference is greater than a predetermined value. It is determined that this is the case and a warning is issued.

It also automatically stops processing.

As a result, it is possible to easily check the time period during which unauthorized interrupts are disabled due to the execution of the program under test, and it is possible to easily detect errors in interrupt control.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

The embodiment of the present invention includes a central processing unit 3 that executes a program under test 1 and an interrupt processing program 2, an interrupt controller 4 that generates an interrupt to the central processing unit 3, and a display device 6. The features include a timer counter 5 that increments the counter by 1 at regular intervals, and a timer counter 5 in the central processing unit 3.
A means for reading out a 0 count value compares the read count value with the previous count value, and when the difference is greater than a predetermined value, the display device 6 indicates that the program under test 1 has illegally prohibited interrupts for a long time. a means for displaying an abnormality;
The central processing unit 3 is provided with a means for displaying the abnormality and a means for automatically interrupting the processing, and the central processing unit 3 is provided with a means for displaying the abnormality and a means for automatically interrupting the processing. and means for storing the count value in place of the previous value.

Next, the operation of the embodiment of the present invention configured as described above will be explained. FIG. 2 is a flowchart showing the flow of operation of the embodiment of the present invention.

The program under test 1 and the interrupt processing program 2 are executed by the central processing unit 3, and the timer counter 5 increments the counter by 1 at regular intervals and requests an interrupt to the interrupt controller 4. Generates an interrupt for 3. Even when the program under test 1 is being executed, the central processing unit 3 executes control by the interrupt processing program 2 if interrupts are permitted.

The central processing unit 3 reads the count value of the timer counter 5 using the interrupt processing program 2, displays the count value on the display device 6, and interrupts processing if the timer counter 5 has advanced by 2 or more compared to the value read last time. The abnormality is displayed on the display device 6.

〔Effect of the invention〕

As explained above, according to the present invention, a program can be easily tested by generating an interrupt using a timer counter, and in a normal computer system, an interrupt controller is provided, and the expansion slot receives the signal. Since the timer counter is pulled out, it is possible to easily construct a test environment by mounting the timer counter in the expansion slot.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a flowchart showing the operation flow of the embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Program under test, 2... Interrupt processing program, 3... Central processing unit, 4... Interrupt controller, 5... Timer counter, 6... Display device.

Claims (1)

[Scope of Claims] 1. A computer system comprising a central processing unit that executes a program under test and an interrupt processing program, an interrupt controller that generates an interrupt to the central processing unit, and a display device, comprising: a timer counter that is activated by the start of an interrupt and increments the counter by 1 at regular intervals; the central processing unit is provided with means for reading the count value of the timer counter; and a means for reading the count value of the timer counter; Compare,
A computer system comprising: means for displaying an abnormality on the display device, indicating that the program under test has illegally prohibited interrupts for a long time when the difference is greater than or equal to a predetermined value. 2. The computer system according to claim 1, further comprising means for automatically interrupting the processing at the same time as the means for displaying the abnormality. 3. The central processing unit includes means for storing the read count value in place of the previous value when the difference between the read count value and the previous count value does not exceed a predetermined value. computer system.